src/soc/regfile/regfiles.py

   1 # POWER9 Register Files
   2 """POWER9 regfiles
   3
   4 Defines the following register files:
   5
   6     * INT regfile
   7     * SPR regfile
   8     * CR regfile
   9     * XER regfile
  10     * FAST regfile
  11
  12 Links:
  13
  14 * https://bugs.libre-soc.org/show_bug.cgi?id=345
  15 * https://libre-soc.org/3d_gpu/architecture/regfile/
  16 * https://libre-soc.org/openpower/isatables/sprs.csv
  17 """
  18
  19 # TODO