src/soc/scoreboard/addr_split.py

   1 # LDST Address Splitter.  For misaligned address crossing cache line boundary
   2
   3 from nmigen import Elaboratable, Module, Signal, Record
   4 from nmutil.latch import SRLatch, latchregister
   5 from nmigen.compat.sim import run_simulation
   6 from nmigen.cli import verilog, rtlil
   7
   8 from soc.scoreboard.addr_match import LenSplitter
   9 from nmutil.queue import Queue
  10
  11
  12 class LDQueue(Elaboratable):
  13
  14     def __init__(self, dwidth, awidth, mlen):
  15         self.addr_i = Signal(awidth, reset_less=True)
  16         self.mask_i = Signal(mlen, reset_less=True)
  17         self.ld_i = Record((('err', 1), ('data', dwidth))
  18         self.ld_o = Record((('err', 1), ('data', dwidth))
  19
  20     def elaborate(self, platform):
  21         m = Module()
  22         comb = m.d.comb
  23         m.submodules.q = q = Queue(width=self.ld_o.shape()[0], 1, fwft=True)
  24
  25
  26 class LDSTSplitter(Elaboratable):
  27
  28     def __init__(self, dwidth, awidth, dlen):
  29         self.addr_i = Signal(awidth, reset_less=True)
  30         self.len_i = Signal(dlen, reset_less=True)
  31         self.is_ld_i = Signal(reset_less=True)
  32         self.ld_data_o = Signal(dwidth, reset_less=True)
  33
  34         self.is_st_i = Signal(reset_less=True)
  35         self.st_data_i = Signal(dwidth, reset_less=True)