3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 the principle here is to take the Function Units, analyse their regspecs,
8 and turn their requirements for access to register file read/write ports
9 into groupings by Register File and Register File Port name.
11 under each grouping - by regfile/port - a list of Function Units that
12 need to connect to that port is created. as these are a contended
13 resource a "Broadcast Bus" per read/write port is then also created,
14 with access to it managed by a PriorityPicker.
16 the brain-dead part of this module is that even though there is no
17 conflict of access, regfile read/write hazards are *not* analysed,
18 and consequently it is safer to wait for the Function Unit to complete
19 before allowing a new instruction to proceed.
20 (update: actually this is being added now:
21 https://bugs.libre-soc.org/show_bug.cgi?id=737)
24 from nmigen
import (Elaboratable
, Module
, Signal
, ResetSignal
, Cat
, Mux
,
26 from nmigen
.cli
import rtlil
28 from openpower
.decoder
.power_decoder2
import PowerDecodeSubset
29 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
30 from openpower
.decoder
.power_regspec_map
import regspec_decode_write
31 from openpower
.sv
.svp64
import SVP64Rec
33 from nmutil
.picker
import PriorityPicker
34 from nmutil
.util
import treereduce
35 from nmutil
.singlepipe
import ControlBase
37 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
, LDSTFunctionUnit
38 from soc
.regfile
.regfiles
import RegFiles
39 from openpower
.decoder
.power_decoder2
import get_rdflags
40 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
# test only
41 from soc
.config
.test
.test_loadstore
import TestMemPspec
42 from openpower
.decoder
.power_enums
import MicrOp
, Function
43 from soc
.simple
.core_data
import CoreInput
, CoreOutput
45 from collections
import defaultdict
, namedtuple
48 from nmutil
.util
import rising_edge
50 FUSpec
= namedtuple("FUSpec", ["funame", "fu", "idx"])
51 ByRegSpec
= namedtuple("ByRegSpec", ["rdport", "wrport", "read",
52 "write", "wid", "specs"])
54 # helper function for reducing a list of signals down to a parallel
56 def ortreereduce(tree
, attr
="o_data"):
57 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
60 def ortreereduce_sig(tree
):
61 return treereduce(tree
, operator
.or_
, lambda x
: x
)
64 # helper function to place full regs declarations first
65 def sort_fuspecs(fuspecs
):
67 for (regname
, fspec
) in fuspecs
.items():
68 if regname
.startswith("full"):
69 res
.append((regname
, fspec
))
70 for (regname
, fspec
) in fuspecs
.items():
71 if not regname
.startswith("full"):
72 res
.append((regname
, fspec
))
73 return res
# enumerate(res)
76 # derive from ControlBase rather than have a separate Stage instance,
77 # this is simpler to do
78 class NonProductionCore(ControlBase
):
79 def __init__(self
, pspec
):
82 # test is SVP64 is to be enabled
83 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
85 # test to see if regfile ports should be reduced
86 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
87 (pspec
.regreduce
== True))
89 # test to see if overlapping of instructions is allowed
90 # (not normally enabled for TestIssuer FSM but useful for checking
91 # the bitvector hazard detection, before doing In-Order)
92 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
93 (pspec
.allow_overlap
== True))
96 self
.make_hazard_vecs
= self
.allow_overlap
97 self
.core_type
= "fsm"
98 if hasattr(pspec
, "core_type"):
99 self
.core_type
= pspec
.core_type
101 super().__init
__(stage
=self
)
103 # single LD/ST funnel for memory access
104 self
.l0
= l0
= TstL0CacheBuffer(pspec
, n_units
=1)
107 # function units (only one each)
108 # only include mmu if enabled in pspec
109 self
.fus
= AllFunctionUnits(pspec
, pilist
=[pi
])
111 # link LoadStore1 into MMU
112 mmu
= self
.fus
.get_fu('mmu0')
113 print ("core pspec", pspec
.ldst_ifacetype
)
114 print ("core mmu", mmu
)
116 print ("core lsmem.lsi", l0
.cmpi
.lsmem
.lsi
)
117 mmu
.alu
.set_ldst_interface(l0
.cmpi
.lsmem
.lsi
)
119 # register files (yes plural)
120 self
.regs
= RegFiles(pspec
, make_hazard_vecs
=self
.make_hazard_vecs
)
122 # set up input and output: unusual requirement to set data directly
123 # (due to the way that the core is set up in a different domain,
124 # see TestIssuer.setup_peripherals
125 self
.p
.i_data
, self
.n
.o_data
= self
.new_specs(None)
126 self
.i
, self
.o
= self
.p
.i_data
, self
.n
.o_data
128 # actual internal input data used (captured)
129 self
.ireg
= self
.ispec()
131 # create per-FU instruction decoders (subsetted). these "satellite"
132 # decoders reduce wire fan-out from the one (main) PowerDecoder2
133 # (used directly by the trap unit) to the *twelve* (or more)
134 # Function Units. we can either have 32 wires (the instruction)
135 # to each, or we can have well over a 200 wire fan-out (to 12
136 # ALUs). it's an easy choice to make.
140 for funame
, fu
in self
.fus
.fus
.items():
141 f_name
= fu
.fnunit
.name
142 fnunit
= fu
.fnunit
.value
143 opkls
= fu
.opsubsetkls
145 # TRAP decoder is the *main* decoder
146 self
.trapunit
= funame
148 self
.decoders
[funame
] = PowerDecodeSubset(None, opkls
, f_name
,
150 state
=self
.ireg
.state
,
151 svp64_en
=self
.svp64_en
,
152 regreduce_en
=self
.regreduce_en
)
153 self
.des
[funame
] = self
.decoders
[funame
].do
155 # create per-Function Unit write-after-write hazard signals
156 # yes, really, this should have been added in ReservationStations
158 for funame
, fu
in self
.fus
.fus
.items():
159 fu
._waw
_hazard
= Signal(name
="waw_%s" % funame
)
161 # share the SPR decoder with the MMU if it exists
162 if "mmu0" in self
.decoders
:
163 self
.decoders
["mmu0"].mmu0_spr_dec
= self
.decoders
["spr0"]
165 # next 3 functions are Stage API Compliance
166 def setup(self
, m
, i
):
170 return CoreInput(self
.pspec
, self
.svp64_en
, self
.regreduce_en
)
175 # elaborate function to create HDL
176 def elaborate(self
, platform
):
177 m
= super().elaborate(platform
)
179 # for testing purposes, to cut down on build time in coriolis2
180 if hasattr(self
.pspec
, "nocore") and self
.pspec
.nocore
== True:
181 x
= Signal() # dummy signal
186 m
.submodules
.fus
= self
.fus
187 m
.submodules
.l0
= l0
= self
.l0
188 self
.regs
.elaborate_into(m
, platform
)
192 # set FU hazards default to 1 (as a test)
193 for funame
, fu
in self
.fus
.fus
.items():
194 comb
+= fu
._waw
_hazard
.eq(1)
197 self
.connect_satellite_decoders(m
)
199 # ssh, cheat: trap uses the main decoder because of the rewriting
200 self
.des
[self
.trapunit
] = self
.ireg
.e
.do
202 # connect up Function Units, then read/write ports, and hazard conflict
203 self
.issue_conflict
= Signal()
204 fu_bitdict
, fu_selected
= self
.connect_instruction(m
)
205 raw_hazard
= self
.connect_rdports(m
, fu_bitdict
, fu_selected
)
206 self
.connect_wrports(m
, fu_bitdict
, fu_selected
)
207 if self
.allow_overlap
:
208 comb
+= self
.issue_conflict
.eq(raw_hazard
)
210 # note if an exception happened. in a pipelined or OoO design
211 # this needs to be accompanied by "shadowing" (or stalling)
213 for exc
in self
.fus
.excs
.values():
214 el
.append(exc
.happened
)
215 if len(el
) > 0: # at least one exception
216 comb
+= self
.o
.exc_happened
.eq(Cat(*el
).bool())
220 def connect_satellite_decoders(self
, m
):
222 for k
, v
in self
.decoders
.items():
223 # connect each satellite decoder and give it the instruction.
224 # as subset decoders this massively reduces wire fanout given
225 # the large number of ALUs
226 setattr(m
.submodules
, "dec_%s" % v
.fn_name
, v
)
227 comb
+= v
.dec
.raw_opcode_in
.eq(self
.ireg
.raw_insn_i
)
228 comb
+= v
.dec
.bigendian
.eq(self
.ireg
.bigendian_i
)
229 # sigh due to SVP64 RA_OR_ZERO detection connect these too
230 comb
+= v
.sv_a_nz
.eq(self
.ireg
.sv_a_nz
)
232 comb
+= v
.pred_sm
.eq(self
.ireg
.sv_pred_sm
)
233 comb
+= v
.pred_dm
.eq(self
.ireg
.sv_pred_dm
)
234 if k
!= self
.trapunit
:
235 comb
+= v
.sv_rm
.eq(self
.ireg
.sv_rm
) # pass through SVP64 RM
236 comb
+= v
.is_svp64_mode
.eq(self
.ireg
.is_svp64_mode
)
237 # only the LDST PowerDecodeSubset *actually* needs to
238 # know to use the alternative decoder. this is all
240 if k
.lower().startswith("ldst"):
241 comb
+= v
.use_svp64_ldst_dec
.eq(
242 self
.ireg
.use_svp64_ldst_dec
)
244 def connect_instruction(self
, m
):
245 """connect_instruction
247 uses decoded (from PowerOp) function unit information from CSV files
248 to ascertain which Function Unit should deal with the current
251 some (such as OP_ATTN, OP_NOP) are dealt with here, including
252 ignoring it and halting the processor. OP_NOP is a bit annoying
253 because the issuer expects busy flag still to be raised then lowered.
254 (this requires a fake counter to be set).
256 comb
, sync
= m
.d
.comb
, m
.d
.sync
259 # indicate if core is busy
260 busy_o
= self
.o
.busy_o
261 any_busy_o
= self
.o
.any_busy_o
263 # connect up temporary copy of incoming instruction. the FSM will
264 # either blat the incoming instruction (if valid) into self.ireg
265 # or if the instruction could not be delivered, keep dropping the
266 # latched copy into ireg
267 ilatch
= self
.ispec()
268 self
.instr_active
= Signal()
270 # enable/busy-signals for each FU, get one bit for each FU (by name)
271 fu_enable
= Signal(len(fus
), reset_less
=True)
272 fu_busy
= Signal(len(fus
), reset_less
=True)
275 for i
, funame
in enumerate(fus
.keys()):
276 fu_bitdict
[funame
] = fu_enable
[i
]
277 fu_selected
[funame
] = fu_busy
[i
]
279 # identify function units and create a list by fnunit so that
280 # PriorityPickers can be created for selecting one of them that
281 # isn't busy at the time the incoming instruction needs passing on
282 by_fnunit
= defaultdict(list)
283 for fname
, member
in Function
.__members
__.items():
284 for funame
, fu
in fus
.items():
285 fnunit
= fu
.fnunit
.value
286 if member
.value
& fnunit
: # this FU handles this type of op
287 by_fnunit
[fname
].append((funame
, fu
)) # add by Function
289 # ok now just print out the list of FUs by Function, because we can
290 for fname
, fu_list
in by_fnunit
.items():
291 print ("FUs by type", fname
, fu_list
)
293 # now create a PriorityPicker per FU-type such that only one
294 # non-busy FU will be picked
296 fu_found
= Signal() # take a note if no Function Unit was available
297 for fname
, fu_list
in by_fnunit
.items():
298 i_pp
= PriorityPicker(len(fu_list
))
299 m
.submodules
['i_pp_%s' % fname
] = i_pp
301 for i
, (funame
, fu
) in enumerate(fu_list
):
302 # match the decoded instruction (e.do.fn_unit) against the
303 # "capability" of this FU, gate that by whether that FU is
304 # busy, and drop that into the PriorityPicker.
305 # this will give us an output of the first available *non-busy*
306 # Function Unit (Reservation Statio) capable of handling this
308 fnunit
= fu
.fnunit
.value
309 en_req
= Signal(name
="issue_en_%s" % funame
, reset_less
=True)
310 fnmatch
= (self
.ireg
.e
.do
.fn_unit
& fnunit
).bool()
311 comb
+= en_req
.eq(fnmatch
& ~fu
.busy_o
&
313 i_l
.append(en_req
) # store in list for doing the Cat-trick
314 # picker output, gated by enable: store in fu_bitdict
315 po
= Signal(name
="o_issue_pick_"+funame
) # picker output
316 comb
+= po
.eq(i_pp
.o
[i
] & i_pp
.en_o
)
317 comb
+= fu_bitdict
[funame
].eq(po
)
318 comb
+= fu_selected
[funame
].eq(fu
.busy_o | po
)
319 # if we don't do this, then when there are no FUs available,
320 # the "p.o_ready" signal will go back "ok we accepted this
321 # instruction" which of course isn't true.
322 with m
.If(i_pp
.en_o
):
323 comb
+= fu_found
.eq(1)
324 # for each input, Cat them together and drop them into the picker
325 comb
+= i_pp
.i
.eq(Cat(*i_l
))
327 # rdmask, which is for registers needs to come from the *main* decoder
328 for funame
, fu
in fus
.items():
329 rdmask
= get_rdflags(self
.ireg
.e
, fu
)
330 comb
+= fu
.rdmaskn
.eq(~rdmask
)
332 # sigh - need a NOP counter
334 with m
.If(counter
!= 0):
335 sync
+= counter
.eq(counter
- 1)
338 # default to reading from incoming instruction: may be overridden
339 # by copy from latch when "waiting"
340 comb
+= self
.ireg
.eq(self
.i
)
341 # always say "ready" except if overridden
342 comb
+= self
.p
.o_ready
.eq(1)
345 with m
.State("READY"):
346 with m
.If(self
.p
.i_valid
): # run only when valid
347 with m
.Switch(self
.ireg
.e
.do
.insn_type
):
348 # check for ATTN: halt if true
349 with m
.Case(MicrOp
.OP_ATTN
):
350 m
.d
.sync
+= self
.o
.core_terminate_o
.eq(1)
352 # fake NOP - this isn't really used (Issuer detects NOP)
353 with m
.Case(MicrOp
.OP_NOP
):
354 sync
+= counter
.eq(2)
358 comb
+= self
.instr_active
.eq(1)
359 comb
+= self
.p
.o_ready
.eq(0)
360 # connect instructions. only one enabled at a time
361 for funame
, fu
in fus
.items():
362 do
= self
.des
[funame
]
363 enable
= fu_bitdict
[funame
]
365 # run this FunctionUnit if enabled route op,
366 # issue, busy, read flags and mask to FU
368 # operand comes from the *local* decoder
369 comb
+= fu
.oper_i
.eq_from(do
)
370 comb
+= fu
.issue_i
.eq(1) # issue when valid
371 # instruction ok, indicate ready
372 comb
+= self
.p
.o_ready
.eq(1)
374 if self
.allow_overlap
:
375 with m
.If(~fu_found
):
376 # latch copy of instruction
377 sync
+= ilatch
.eq(self
.i
)
378 comb
+= self
.p
.o_ready
.eq(1) # accept
382 with m
.State("WAITING"):
383 comb
+= self
.instr_active
.eq(1)
384 comb
+= self
.p
.o_ready
.eq(0)
386 # using copy of instruction, keep waiting until an FU is free
387 comb
+= self
.ireg
.eq(ilatch
)
388 with m
.If(fu_found
): # wait for conflict to clear
389 # connect instructions. only one enabled at a time
390 for funame
, fu
in fus
.items():
391 do
= self
.des
[funame
]
392 enable
= fu_bitdict
[funame
]
394 # run this FunctionUnit if enabled route op,
395 # issue, busy, read flags and mask to FU
397 # operand comes from the *local* decoder
398 comb
+= fu
.oper_i
.eq_from(do
)
399 comb
+= fu
.issue_i
.eq(1) # issue when valid
400 comb
+= self
.p
.o_ready
.eq(1)
404 print ("core: overlap allowed", self
.allow_overlap
)
405 busys
= map(lambda fu
: fu
.busy_o
, fus
.values())
406 comb
+= any_busy_o
.eq(Cat(*busys
).bool())
407 if not self
.allow_overlap
:
408 # for simple non-overlap, if any instruction is busy, set
409 # busy output for core.
410 comb
+= busy_o
.eq(any_busy_o
)
412 # sigh deal with a fun situation that needs to be investigated
414 with m
.If(self
.issue_conflict
):
417 # return both the function unit "enable" dict as well as the "busy".
418 # the "busy-or-issued" can be passed in to the Read/Write port
419 # connecters to give them permission to request access to regfiles
420 return fu_bitdict
, fu_selected
422 def connect_rdport(self
, m
, fu_bitdict
, fu_selected
,
423 rdpickers
, regfile
, regname
, fspec
):
424 comb
, sync
= m
.d
.comb
, m
.d
.sync
430 # select the required read port. these are pre-defined sizes
431 rfile
= regs
.rf
[regfile
.lower()]
432 rport
= rfile
.r_ports
[rpidx
]
433 print("read regfile", rpidx
, regfile
, regs
.rf
.keys(),
436 # for checking if the read port has an outstanding write
437 if self
.make_hazard_vecs
:
438 wv
= regs
.wv
[regfile
.lower()]
439 wvchk
= wv
.r_ports
["issue"] # write-vec bit-level hazard check
441 # if a hazard is detected on this read port, simply blithely block
442 # every FU from reading on it. this is complete overkill but very
444 hazard_detected
= Signal(name
="raw_%s_%s" % (regfile
, rpidx
))
447 if not isinstance(fspecs
, list):
453 for i
, fspec
in enumerate(fspecs
):
454 # get the regfile specs for this regfile port
455 (rf
, wf
, _read
, _write
, wid
, fuspecs
) = \
456 (fspec
.rdport
, fspec
.wrport
, fspec
.read
, fspec
.write
,
457 fspec
.wid
, fspec
.specs
)
458 print ("fpsec", i
, fspec
, len(fuspecs
))
459 ppoffs
.append(pplen
) # record offset for picker
460 pplen
+= len(fspec
.specs
)
461 name
= "rdflag_%s_%s_%d" % (regfile
, regname
, i
)
462 rdflag
= Signal(name
=name
, reset_less
=True)
463 comb
+= rdflag
.eq(fspec
.rdport
)
464 rdflags
.append(rdflag
)
466 print ("pplen", pplen
)
468 # create a priority picker to manage this port
469 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(pplen
)
470 setattr(m
.submodules
, "rdpick_%s_%s" % (regfile
, rpidx
), rdpick
)
476 for i
, fspec
in enumerate(fspecs
):
477 (rf
, wf
, _read
, _write
, wid
, fuspecs
) = \
478 (fspec
.rdport
, fspec
.wrport
, fspec
.read
, fspec
.write
,
479 fspec
.wid
, fspec
.specs
)
480 # connect up the FU req/go signals, and the reg-read to the FU
481 # and create a Read Broadcast Bus
482 for pi
, fuspec
in enumerate(fspec
.specs
):
483 (funame
, fu
, idx
) = (fuspec
.funame
, fuspec
.fu
, fuspec
.idx
)
485 name
= "%s_%s_%s_%i" % (regfile
, rpidx
, funame
, pi
)
486 fu_active
= fu_selected
[funame
]
487 fu_issued
= fu_bitdict
[funame
]
489 # get (or set up) a latched copy of read register number
490 rname
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, pi
)
491 read
= Signal
.like(_read
, name
="read_"+name
)
492 if rname
not in fu
.rd_latches
:
493 rdl
= Signal
.like(_read
, name
="rdlatch_"+rname
)
494 fu
.rd_latches
[rname
] = rdl
495 with m
.If(fu
.issue_i
):
496 sync
+= rdl
.eq(_read
)
498 rdl
= fu
.rd_latches
[rname
]
499 # latch to make the read immediately available on issue cycle
500 # after the read cycle, use the latched copy
501 with m
.If(fu
.issue_i
):
502 comb
+= read
.eq(_read
)
506 # connect request-read to picker input, and output to go-rd
507 addr_en
= Signal
.like(read
, name
="addr_en_"+name
)
508 pick
= Signal(name
="pick_"+name
) # picker input
509 rp
= Signal(name
="rp_"+name
) # picker output
510 delay_pick
= Signal(name
="dp_"+name
) # read-enable "underway"
511 rhazard
= Signal(name
="rhaz_"+name
)
513 # exclude any currently-enabled read-request (mask out active)
514 # entirely block anything hazarded from being picked
515 comb
+= pick
.eq(fu
.rd_rel_o
[idx
] & fu_active
& rdflags
[i
] &
516 ~delay_pick
& ~rhazard
)
517 comb
+= rdpick
.i
[pi
].eq(pick
)
518 comb
+= fu
.go_rd_i
[idx
].eq(delay_pick
) # pass in *delayed* pick
520 # if picked, select read-port "reg select" number to port
521 comb
+= rp
.eq(rdpick
.o
[pi
] & rdpick
.en_o
)
522 sync
+= delay_pick
.eq(rp
) # delayed "pick"
523 comb
+= addr_en
.eq(Mux(rp
, read
, 0))
525 # the read-enable happens combinatorially (see mux-bus below)
526 # but it results in the data coming out on a one-cycle delay.
530 addrs
.append(addr_en
)
533 # use the *delayed* pick signal to put requested data onto bus
534 with m
.If(delay_pick
):
535 # connect regfile port to input, creating fan-out Bus
537 print("reg connect widths",
538 regfile
, regname
, pi
, funame
,
539 src
.shape(), rport
.o_data
.shape())
540 # all FUs connect to same port
541 comb
+= src
.eq(rport
.o_data
)
543 if not self
.make_hazard_vecs
:
546 # read the write-hazard bitvector (wv) for any bit that is
547 wvchk_en
= Signal(len(wvchk
.ren
), name
="wv_chk_addr_en_"+name
)
548 issue_active
= Signal(name
="rd_iactive_"+name
)
549 # XXX combinatorial loop here
550 comb
+= issue_active
.eq(fu_active
& rf
)
551 with m
.If(issue_active
):
553 comb
+= wvchk_en
.eq(read
)
555 comb
+= wvchk_en
.eq(1<<read
)
556 # if FU is busy (which doesn't get set at the same time as
557 # issue) and no hazard was detected, clear wvchk_en (i.e.
558 # stop checking for hazards). there is a loop here, but it's
559 # via a DFF, so is ok. some linters may complain, but hey.
560 with m
.If(fu
.busy_o
& ~rhazard
):
561 comb
+= wvchk_en
.eq(0)
563 # read-hazard is ANDed with (filtered by) what is actually
565 comb
+= rhazard
.eq((wvchk
.o_data
& wvchk_en
).bool())
567 wvens
.append(wvchk_en
)
569 # or-reduce the muxed read signals
571 # for unary-addressed
572 comb
+= rport
.ren
.eq(ortreereduce_sig(rens
))
574 # for binary-addressed
575 comb
+= rport
.addr
.eq(ortreereduce_sig(addrs
))
576 comb
+= rport
.ren
.eq(Cat(*rens
).bool())
577 print ("binary", regfile
, rpidx
, rport
, rport
.ren
, rens
, addrs
)
579 if not self
.make_hazard_vecs
:
580 return Const(0) # declare "no hazards"
582 # enable the read bitvectors for this issued instruction
583 # and return whether any write-hazard bit is set
584 comb
+= wvchk
.ren
.eq(ortreereduce_sig(wvens
))
585 comb
+= hazard_detected
.eq(wvchk
.o_data
.bool())
586 return hazard_detected
588 def connect_rdports(self
, m
, fu_bitdict
, fu_selected
):
589 """connect read ports
591 orders the read regspecs into a dict-of-dicts, by regfile, by
592 regport name, then connects all FUs that want that regport by
593 way of a PriorityPicker.
595 comb
, sync
= m
.d
.comb
, m
.d
.sync
600 # dictionary of lists of regfile read ports
601 byregfiles_rd
, byregfiles_rdspec
= self
.get_byregfiles(True)
603 # okaay, now we need a PriorityPicker per regfile per regfile port
604 # loootta pickers... peter piper picked a pack of pickled peppers...
606 for regfile
, spec
in byregfiles_rd
.items():
607 fuspecs
= byregfiles_rdspec
[regfile
]
608 rdpickers
[regfile
] = {}
610 # argh. an experiment to merge RA and RB in the INT regfile
611 # (we have too many read/write ports)
612 if self
.regreduce_en
:
614 fuspecs
['rabc'] = [fuspecs
.pop('rb')]
615 fuspecs
['rabc'].append(fuspecs
.pop('rc'))
616 fuspecs
['rabc'].append(fuspecs
.pop('ra'))
617 if regfile
== 'FAST':
618 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
619 if 'fast2' in fuspecs
:
620 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
621 if 'fast3' in fuspecs
:
622 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
624 # for each named regfile port, connect up all FUs to that port
625 # also return (and collate) hazard detection)
626 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
627 print("connect rd", regname
, fspec
)
628 rh
= self
.connect_rdport(m
, fu_bitdict
, fu_selected
,
633 return Cat(*rd_hazard
).bool()
635 def make_hazards(self
, m
, regfile
, rfile
, wvclr
, wvset
,
636 funame
, regname
, idx
,
637 addr_en
, wp
, fu
, fu_active
, wrflag
, write
,
639 """make_hazards: a setter and a clearer for the regfile write ports
641 setter is at issue time (using PowerDecoder2 regfile write numbers)
642 clearer is at regfile write time (when FU has said what to write to)
644 there is *one* unusual case here which has to be dealt with:
645 when the Function Unit does *NOT* request a write to the regfile
646 (has its data.ok bit CLEARED). this is perfectly legitimate.
649 comb
, sync
= m
.d
.comb
, m
.d
.sync
650 name
= "%s_%s_%d" % (funame
, regname
, idx
)
652 # connect up the bitvector write hazard. unlike the
653 # regfile writeports, a ONE must be written to the corresponding
654 # bit of the hazard bitvector (to indicate the existence of
657 # the detection of what shall be written to is based
659 print ("write vector (for regread)", regfile
, wvset
)
660 wviaddr_en
= Signal(len(wvset
.wen
), name
="wv_issue_addr_en_"+name
)
661 issue_active
= Signal(name
="iactive_"+name
)
662 comb
+= issue_active
.eq(fu
.issue_i
& fu_active
& wrflag
)
663 with m
.If(issue_active
):
665 comb
+= wviaddr_en
.eq(write
)
667 comb
+= wviaddr_en
.eq(1<<write
)
669 # deal with write vector clear: this kicks in when the regfile
670 # is written to, and clears the corresponding bitvector entry
671 print ("write vector", regfile
, wvclr
)
672 wvaddr_en
= Signal(len(wvclr
.wen
), name
="wvaddr_en_"+name
)
674 comb
+= wvaddr_en
.eq(addr_en
)
677 comb
+= wvaddr_en
.eq(1<<addr_en
)
679 # XXX ASSUME that LDSTFunctionUnit always sets the data it intends to
680 # this may NOT be the case when an exception occurs
681 if isinstance(fu
, LDSTFunctionUnit
):
682 return wvaddr_en
, wviaddr_en
684 # okaaay, this is preparation for the awkward case.
685 # * latch a copy of wrflag when issue goes high.
686 # * when the fu_wrok (data.ok) flag is NOT set,
687 # but the FU is done, the FU is NEVER going to write
688 # so the bitvector has to be cleared.
689 latch_wrflag
= Signal(name
="latch_wrflag_"+name
)
690 with m
.If(~fu
.busy_o
):
691 sync
+= latch_wrflag
.eq(0)
692 with m
.If(fu
.issue_i
& fu_active
):
693 sync
+= latch_wrflag
.eq(wrflag
)
694 with m
.If(fu
.alu_done_o
& latch_wrflag
& ~fu_wrok
):
696 comb
+= wvaddr_en
.eq(write
) # addr_en gated with wp, don't use
698 comb
+= wvaddr_en
.eq(1<<addr_en
) # binary addr_en not gated
700 return wvaddr_en
, wviaddr_en
702 def connect_wrport(self
, m
, fu_bitdict
, fu_selected
,
703 wrpickers
, regfile
, regname
, fspec
):
704 comb
, sync
= m
.d
.comb
, m
.d
.sync
710 # select the required write port. these are pre-defined sizes
711 rfile
= regs
.rf
[regfile
.lower()]
712 wport
= rfile
.w_ports
[rpidx
]
714 print("connect wr", regname
, "unary", rfile
.unary
, fspec
)
715 print(regfile
, regs
.rf
.keys())
717 # select the write-protection hazard vector. note that this still
718 # requires to WRITE to the hazard bitvector! read-requests need
719 # to RAISE the bitvector (set it to 1), which, duh, requires a WRITE
720 if self
.make_hazard_vecs
:
721 wv
= regs
.wv
[regfile
.lower()]
722 wvset
= wv
.w_ports
["set"] # write-vec bit-level hazard ctrl
723 wvclr
= wv
.w_ports
["clr"] # write-vec bit-level hazard ctrl
726 if not isinstance(fspecs
, list):
734 for i
, fspec
in enumerate(fspecs
):
735 # get the regfile specs for this regfile port
736 (rf
, wf
, _read
, _write
, wid
, fuspecs
) = \
737 (fspec
.rdport
, fspec
.wrport
, fspec
.read
, fspec
.write
,
738 fspec
.wid
, fspec
.specs
)
739 print ("fpsec", i
, "wrflag", wf
, fspec
, len(fuspecs
))
740 ppoffs
.append(pplen
) # record offset for picker
741 pplen
+= len(fuspecs
)
743 name
= "%s_%s_%d" % (regfile
, regname
, i
)
744 rdflag
= Signal(name
="rd_flag_"+name
)
745 wrflag
= Signal(name
="wr_flag_"+name
)
747 comb
+= rdflag
.eq(rf
)
751 comb
+= wrflag
.eq(wf
)
754 rdflags
.append(rdflag
)
755 wrflags
.append(wrflag
)
757 # create a priority picker to manage this port
758 wrpickers
[regfile
][rpidx
] = wrpick
= PriorityPicker(pplen
)
759 setattr(m
.submodules
, "wrpick_%s_%s" % (regfile
, rpidx
), wrpick
)
767 for i
, fspec
in enumerate(fspecs
):
768 # connect up the FU req/go signals and the reg-read to the FU
769 # these are arbitrated by Data.ok signals
770 (rf
, wf
, _read
, _write
, wid
, fuspecs
) = \
771 (fspec
.rdport
, fspec
.wrport
, fspec
.read
, fspec
.write
,
772 fspec
.wid
, fspec
.specs
)
773 for pi
, fuspec
in enumerate(fspec
.specs
):
774 (funame
, fu
, idx
) = (fuspec
.funame
, fuspec
.fu
, fuspec
.idx
)
776 name
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, idx
)
777 # get (or set up) a write-latched copy of write register number
778 write
= Signal
.like(_write
, name
="write_"+name
)
779 rname
= "%s_%s_%s" % (funame
, regfile
, regname
)
780 if rname
not in fu
.wr_latches
:
781 wrl
= Signal
.like(_write
, name
="wrlatch_"+rname
)
782 fu
.wr_latches
[rname
] = write
783 with m
.If(fu
.issue_i
):
784 sync
+= wrl
.eq(_write
)
785 comb
+= write
.eq(_write
)
787 comb
+= write
.eq(wrl
)
789 write
= fu
.wr_latches
[rname
]
791 # write-request comes from dest.ok
792 dest
= fu
.get_out(idx
)
793 fu_dest_latch
= fu
.get_fu_out(idx
) # latched output
794 name
= "fu_wrok_%s_%s_%d" % (funame
, regname
, idx
)
795 fu_wrok
= Signal(name
=name
, reset_less
=True)
796 comb
+= fu_wrok
.eq(dest
.ok
& fu
.busy_o
)
798 # connect request-write to picker input, and output to go-wr
799 fu_active
= fu_selected
[funame
]
800 pick
= fu
.wr
.rel_o
[idx
] & fu_active
801 comb
+= wrpick
.i
[pi
].eq(pick
)
802 # create a single-pulse go write from the picker output
803 wr_pick
= Signal(name
="wpick_%s_%s_%d" % (funame
, regname
, idx
))
804 comb
+= wr_pick
.eq(wrpick
.o
[pi
] & wrpick
.en_o
)
805 comb
+= fu
.go_wr_i
[idx
].eq(rising_edge(m
, wr_pick
))
807 # connect the regspec write "reg select" number to this port
808 # only if one FU actually requests (and is granted) the port
809 # will the write-enable be activated
810 wname
= "waddr_en_%s_%s_%d" % (funame
, regname
, idx
)
811 addr_en
= Signal
.like(write
, name
=wname
)
813 comb
+= wp
.eq(wr_pick
& wrpick
.en_o
)
814 comb
+= addr_en
.eq(Mux(wp
, write
, 0))
818 addrs
.append(addr_en
)
821 # connect regfile port to input
822 print("reg connect widths",
823 regfile
, regname
, pi
, funame
,
824 dest
.shape(), wport
.i_data
.shape())
825 wsigs
.append(fu_dest_latch
)
827 # now connect up the bitvector write hazard
828 if not self
.make_hazard_vecs
:
830 res
= self
.make_hazards(m
, regfile
, rfile
, wvclr
, wvset
,
831 funame
, regname
, idx
,
832 addr_en
, wp
, fu
, fu_active
,
833 wrflags
[i
], write
, fu_wrok
)
834 wvaddr_en
, wv_issue_en
= res
835 wvclren
.append(wvaddr_en
) # set only: no data => clear bit
836 wvseten
.append(wv_issue_en
) # set data same as enable
837 wvsets
.append(wv_issue_en
) # because enable needs a 1
839 # here is where we create the Write Broadcast Bus. simple, eh?
840 comb
+= wport
.i_data
.eq(ortreereduce_sig(wsigs
))
842 # for unary-addressed
843 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
845 # for binary-addressed
846 comb
+= wport
.addr
.eq(ortreereduce_sig(addrs
))
847 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
849 if not self
.make_hazard_vecs
:
853 comb
+= wvclr
.wen
.eq(ortreereduce_sig(wvclren
)) # clear (regfile write)
854 comb
+= wvset
.wen
.eq(ortreereduce_sig(wvseten
)) # set (issue time)
855 comb
+= wvset
.i_data
.eq(ortreereduce_sig(wvsets
))
857 def connect_wrports(self
, m
, fu_bitdict
, fu_selected
):
858 """connect write ports
860 orders the write regspecs into a dict-of-dicts, by regfile,
861 by regport name, then connects all FUs that want that regport
862 by way of a PriorityPicker.
864 note that the write-port wen, write-port data, and go_wr_i all need to
865 be on the exact same clock cycle. as there is a combinatorial loop bug
866 at the moment, these all use sync.
868 comb
, sync
= m
.d
.comb
, m
.d
.sync
871 # dictionary of lists of regfile write ports
872 byregfiles_wr
, byregfiles_wrspec
= self
.get_byregfiles(False)
874 # same for write ports.
875 # BLECH! complex code-duplication! BLECH!
877 for regfile
, spec
in byregfiles_wr
.items():
878 fuspecs
= byregfiles_wrspec
[regfile
]
879 wrpickers
[regfile
] = {}
881 if self
.regreduce_en
:
882 # argh, more port-merging
884 fuspecs
['o'] = [fuspecs
.pop('o')]
885 fuspecs
['o'].append(fuspecs
.pop('o1'))
886 if regfile
== 'FAST':
887 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
888 if 'fast2' in fuspecs
:
889 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
890 if 'fast3' in fuspecs
:
891 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
893 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
894 self
.connect_wrport(m
, fu_bitdict
, fu_selected
, wrpickers
,
895 regfile
, regname
, fspec
)
897 def get_byregfiles(self
, readmode
):
899 mode
= "read" if readmode
else "write"
902 e
= self
.ireg
.e
# decoded instruction to execute
904 # dictionary of dictionaries of lists/tuples of regfile ports.
905 # first key: regfile. second key: regfile port name
906 byregfiles
= defaultdict(lambda: defaultdict(list))
907 byregfiles_spec
= defaultdict(dict)
909 for (funame
, fu
) in fus
.items():
910 # create in each FU a receptacle for the read/write register
911 # hazard numbers. to be latched in connect_rd/write_ports
912 # XXX better that this is moved into the actual FUs, but
913 # the issue there is that this function is actually better
914 # suited at the moment
920 print("%s ports for %s" % (mode
, funame
))
921 for idx
in range(fu
.n_src
if readmode
else fu
.n_dst
):
922 # construct regfile specs: read uses inspec, write outspec
924 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
926 (regfile
, regname
, wid
) = fu
.get_out_spec(idx
)
927 print(" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
929 # the PowerDecoder2 (main one, not the satellites) contains
930 # the decoded regfile numbers. obtain these now
932 rdport
, read
= regspec_decode_read(e
, regfile
, regname
)
933 wrport
, write
= None, None
935 rdport
, read
= None, None
936 wrport
, write
= regspec_decode_write(e
, regfile
, regname
)
938 # construct the dictionary of regspec information by regfile
939 if regname
not in byregfiles_spec
[regfile
]:
940 byregfiles_spec
[regfile
][regname
] = \
941 ByRegSpec(rdport
, wrport
, read
, write
, wid
, [])
942 # here we start to create "lanes"
943 fuspec
= FUSpec(funame
, fu
, idx
)
944 byregfiles
[regfile
][idx
].append(fuspec
)
945 byregfiles_spec
[regfile
][regname
].specs
.append(fuspec
)
948 # append a latch Signal to the FU's list of latches
949 rname
= "%s_%s" % (regfile
, regname
)
951 if rname
not in fu
.rd_latches
:
952 rdl
= Signal
.like(read
, name
="rdlatch_"+rname
)
953 fu
.rd_latches
[rname
] = rdl
955 if rname
not in fu
.wr_latches
:
956 wrl
= Signal
.like(write
, name
="wrlatch_"+rname
)
957 fu
.wr_latches
[rname
] = wrl
959 # ok just print that all out, for convenience
960 for regfile
, spec
in byregfiles
.items():
961 print("regfile %s ports:" % mode
, regfile
)
962 fuspecs
= byregfiles_spec
[regfile
]
963 for regname
, fspec
in fuspecs
.items():
964 [rdport
, wrport
, read
, write
, wid
, fuspecs
] = fspec
965 print(" rf %s port %s lane: %s" % (mode
, regfile
, regname
))
966 print(" %s" % regname
, wid
, read
, write
, rdport
, wrport
)
967 for (funame
, fu
, idx
) in fuspecs
:
968 fusig
= fu
.src_i
[idx
] if readmode
else fu
.dest
[idx
]
969 print(" ", funame
, fu
.__class
__.__name
__, idx
, fusig
)
972 return byregfiles
, byregfiles_spec
975 yield from self
.fus
.ports()
976 yield from self
.i
.e
.ports()
977 yield from self
.l0
.ports()
984 if __name__
== '__main__':
985 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
990 dut
= NonProductionCore(pspec
)
991 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
992 with
open("test_core.il", "w") as f
: