src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal, ResetSignal, Cat, Mux
  23 from nmigen.cli import rtlil
  24
  25 from openpower.decoder.power_decoder2 import PowerDecodeSubset
  26 from openpower.decoder.power_regspec_map import regspec_decode_read
  27 from openpower.decoder.power_regspec_map import regspec_decode_write
  28 from openpower.sv.svp64 import SVP64Rec
  29
  30 from nmutil.picker import PriorityPicker
  31 from nmutil.util import treereduce
  32 from nmutil.singlepipe import ControlBase
  33
  34 from soc.fu.compunits.compunits import AllFunctionUnits
  35 from soc.regfile.regfiles import RegFiles
  36 from openpower.decoder.decode2execute1 import Decode2ToExecute1Type
  37 from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
  38 from openpower.decoder.power_decoder2 import get_rdflags
  39 from openpower.decoder.decode2execute1 import Data
  40 from soc.experiment.l0_cache import TstL0CacheBuffer  # test only
  41 from soc.config.test.test_loadstore import TestMemPspec
  42 from openpower.decoder.power_enums import MicrOp, Function
  43 from soc.config.state import CoreState
  44
  45 from collections import defaultdict
  46 import operator
  47
  48 from nmutil.util import rising_edge
  49
  50
  51 # helper function for reducing a list of signals down to a parallel
  52 # ORed single signal.
  53 def ortreereduce(tree, attr="o_data"):
  54     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  55
  56
  57 def ortreereduce_sig(tree):
  58     return treereduce(tree, operator.or_, lambda x: x)
  59
  60
  61 # helper function to place full regs declarations first
  62 def sort_fuspecs(fuspecs):
  63     res = []
  64     for (regname, fspec) in fuspecs.items():
  65         if regname.startswith("full"):
  66             res.append((regname, fspec))
  67     for (regname, fspec) in fuspecs.items():
  68         if not regname.startswith("full"):
  69             res.append((regname, fspec))
  70     return res  # enumerate(res)
  71
  72
  73 class CoreInput:
  74     """CoreInput: this is the input specification for Signals coming into core.
  75
  76     * state.  this contains PC, MSR, and SVSTATE. this is crucial information.
  77       (TODO: bigendian_i should really be read from the relevant MSR bit)
  78
  79     * the previously-decoded instruction goes into the Decode2Execute1Type
  80       data structure. no need for Core to re-decode that.  however note
  81       that *satellite* decoders *are* part of Core.
  82
  83     * the raw instruction. this is used by satellite decoders internal to
  84       Core, to provide Function-Unit-specific information.  really, they
  85       should be part of the actual ALU itself (in order to reduce wires),
  86       but hey.
  87
  88     * other stuff is related to SVP64.  the 24-bit SV REMAP field containing
  89       Vector context, etc.
  90     """
  91     def __init__(self, pspec, svp64_en, regreduce_en):
  92         self.pspec = pspec
  93         self.svp64_en = svp64_en
  94         self.e = Decode2ToExecute1Type("core", opkls=IssuerDecode2ToOperand,
  95                                 regreduce_en=regreduce_en)
  96
  97         # SVP64 RA_OR_ZERO needs to know if the relevant EXTRA2/3 field is zero
  98         self.sv_a_nz = Signal()
  99
 100         # state and raw instruction (and SVP64 ReMap fields)
 101         self.state = CoreState("core")
 102         self.raw_insn_i = Signal(32) # raw instruction
 103         self.bigendian_i = Signal() # bigendian - TODO, set by MSR.BE
 104         if svp64_en:
 105             self.sv_rm = SVP64Rec(name="core_svp64_rm") # SVP64 RM field
 106             self.is_svp64_mode = Signal() # set if SVP64 mode is enabled
 107             self.use_svp64_ldst_dec = Signal() # use alternative LDST decoder
 108             self.sv_pred_sm = Signal() # TODO: SIMD width
 109             self.sv_pred_dm = Signal() # TODO: SIMD width
 110
 111     def eq(self, i):
 112         self.e.eq(i.e)
 113         self.sv_a_nz.eq(i.sv_a_nz)
 114         self.state.eq(i.state)
 115         self.raw_insn_i.eq(i.raw_insn_i)
 116         self.bigendian_i.eq(i.bigendian_i)
 117         if not self.svp64_en:
 118             return
 119         self.sv_rm.eq(i.sv_rm)
 120         self.is_svp64_mode.eq(i.is_svp64_mode)
 121         self.use_svp64_ldst_dec.eq(i.use_svp64_ldst_dec)
 122         self.sv_pred_sm.eq(i.sv_pred_sm)
 123         self.sv_pred_dm.eq(i.sv_pred_dm)
 124
 125
 126 class CoreOutput:
 127     def __init__(self):
 128         # start/stop and terminated signalling
 129         self.core_terminate_o = Signal()  # indicates stopped
 130         self.busy_o = Signal(name="corebusy_o")  # at least one ALU busy
 131         self.exc_happened = Signal()             # exception happened
 132
 133     def eq(self, i):
 134         self.core_terminate_o.eq(i.core_terminate_o)
 135         self.busy_o.eq(i.busy_o)
 136         self.exc_happened.eq(i.exc_happened)
 137
 138
 139 # derive from ControlBase rather than have a separate Stage instance,
 140 # this is simpler to do
 141 class NonProductionCore(ControlBase):
 142     def __init__(self, pspec):
 143         self.pspec = pspec
 144
 145         # test is SVP64 is to be enabled
 146         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
 147
 148         # test to see if regfile ports should be reduced
 149         self.regreduce_en = (hasattr(pspec, "regreduce") and
 150                              (pspec.regreduce == True))
 151
 152         super().__init__(stage=self)
 153
 154         # single LD/ST funnel for memory access
 155         self.l0 = l0 = TstL0CacheBuffer(pspec, n_units=1)
 156         pi = l0.l0.dports[0]
 157
 158         # function units (only one each)
 159         # only include mmu if enabled in pspec
 160         self.fus = AllFunctionUnits(pspec, pilist=[pi])
 161
 162         # link LoadStore1 into MMU
 163         mmu = self.fus.get_fu('mmu0')
 164         print ("core pspec", pspec.ldst_ifacetype)
 165         print ("core mmu", mmu)
 166         print ("core lsmem.lsi", l0.cmpi.lsmem.lsi)
 167         if mmu is not None:
 168             mmu.alu.set_ldst_interface(l0.cmpi.lsmem.lsi)
 169
 170         # register files (yes plural)
 171         self.regs = RegFiles(pspec)
 172
 173         # set up input and output: unusual requirement to set data directly
 174         # (due to the way that the core is set up in a different domain,
 175         # see TestIssuer.setup_peripherals
 176         self.i, self.o = self.new_specs(None)
 177         self.i, self.o = self.p.i_data, self.n.o_data
 178
 179         # create per-FU instruction decoders (subsetted)
 180         self.decoders = {}
 181         self.des = {}
 182
 183         for funame, fu in self.fus.fus.items():
 184             f_name = fu.fnunit.name
 185             fnunit = fu.fnunit.value
 186             opkls = fu.opsubsetkls
 187             if f_name == 'TRAP':
 188                 # TRAP decoder is the *main* decoder
 189                 self.trapunit = funame
 190                 continue
 191             self.decoders[funame] = PowerDecodeSubset(None, opkls, f_name,
 192                                                       final=True,
 193                                                       state=self.i.state,
 194                                             svp64_en=self.svp64_en,
 195                                             regreduce_en=self.regreduce_en)
 196             self.des[funame] = self.decoders[funame].do
 197
 198         if "mmu0" in self.decoders:
 199             self.decoders["mmu0"].mmu0_spr_dec = self.decoders["spr0"]
 200
 201     def setup(self, m, i):
 202         pass
 203
 204     def ispec(self):
 205         return CoreInput(self.pspec, self.svp64_en, self.regreduce_en)
 206
 207     def ospec(self):
 208         return CoreOutput()
 209
 210     def elaborate(self, platform):
 211         m = super().elaborate(platform)
 212
 213         # for testing purposes, to cut down on build time in coriolis2
 214         if hasattr(self.pspec, "nocore") and self.pspec.nocore == True:
 215             x = Signal() # dummy signal
 216             m.d.sync += x.eq(~x)
 217             return m
 218         comb = m.d.comb
 219
 220         m.submodules.fus = self.fus
 221         m.submodules.l0 = l0 = self.l0
 222         self.regs.elaborate_into(m, platform)
 223         regs = self.regs
 224         fus = self.fus.fus
 225
 226         # connect decoders
 227         self.connect_satellite_decoders(m)
 228
 229         # ssh, cheat: trap uses the main decoder because of the rewriting
 230         self.des[self.trapunit] = self.i.e.do
 231
 232         # connect up Function Units, then read/write ports
 233         fu_bitdict, fu_selected = self.connect_instruction(m)
 234         self.connect_rdports(m, fu_selected)
 235         self.connect_wrports(m, fu_selected)
 236
 237         # note if an exception happened.  in a pipelined or OoO design
 238         # this needs to be accompanied by "shadowing" (or stalling)
 239         el = []
 240         for exc in self.fus.excs.values():
 241             el.append(exc.happened)
 242         if len(el) > 0: # at least one exception
 243             comb += self.o.exc_happened.eq(Cat(*el).bool())
 244
 245         return m
 246
 247     def connect_satellite_decoders(self, m):
 248         comb = m.d.comb
 249         for k, v in self.decoders.items():
 250             # connect each satellite decoder and give it the instruction.
 251             # as subset decoders this massively reduces wire fanout given
 252             # the large number of ALUs
 253             setattr(m.submodules, "dec_%s" % v.fn_name, v)
 254             comb += v.dec.raw_opcode_in.eq(self.i.raw_insn_i)
 255             comb += v.dec.bigendian.eq(self.i.bigendian_i)
 256             # sigh due to SVP64 RA_OR_ZERO detection connect these too
 257             comb += v.sv_a_nz.eq(self.i.sv_a_nz)
 258             if self.svp64_en:
 259                 comb += v.pred_sm.eq(self.i.sv_pred_sm)
 260                 comb += v.pred_dm.eq(self.i.sv_pred_dm)
 261                 if k != self.trapunit:
 262                     comb += v.sv_rm.eq(self.i.sv_rm) # pass through SVP64 ReMap
 263                     comb += v.is_svp64_mode.eq(self.i.is_svp64_mode)
 264                     # only the LDST PowerDecodeSubset *actually* needs to
 265                     # know to use the alternative decoder.  this is all
 266                     # a terrible hack
 267                     if k.lower().startswith("ldst"):
 268                         comb += v.use_svp64_ldst_dec.eq(
 269                                         self.i.use_svp64_ldst_dec)
 270
 271     def connect_instruction(self, m):
 272         """connect_instruction
 273
 274         uses decoded (from PowerOp) function unit information from CSV files
 275         to ascertain which Function Unit should deal with the current
 276         instruction.
 277
 278         some (such as OP_ATTN, OP_NOP) are dealt with here, including
 279         ignoring it and halting the processor.  OP_NOP is a bit annoying
 280         because the issuer expects busy flag still to be raised then lowered.
 281         (this requires a fake counter to be set).
 282         """
 283         comb, sync = m.d.comb, m.d.sync
 284         fus = self.fus.fus
 285
 286         # indicate if core is busy
 287         busy_o = self.o.busy_o
 288
 289         # enable/busy-signals for each FU, get one bit for each FU (by name)
 290         fu_enable = Signal(len(fus), reset_less=True)
 291         fu_busy = Signal(len(fus), reset_less=True)
 292         fu_bitdict = {}
 293         fu_selected = {}
 294         for i, funame in enumerate(fus.keys()):
 295             fu_bitdict[funame] = fu_enable[i]
 296             fu_selected[funame] = fu_busy[i]
 297
 298         # identify function units and create a list by fnunit so that
 299         # PriorityPickers can be created for selecting one of them that
 300         # isn't busy at the time the incoming instruction needs passing on
 301         by_fnunit = defaultdict(list)
 302         for fname, member in Function.__members__.items():
 303             for funame, fu in fus.items():
 304                 fnunit = fu.fnunit.value
 305                 if member.value & fnunit: # this FU handles this type of op
 306                     by_fnunit[fname].append((funame, fu)) # add by Function
 307
 308         # ok now just print out the list of FUs by Function, because we can
 309         for fname, fu_list in by_fnunit.items():
 310             print ("FUs by type", fname, fu_list)
 311
 312         # now create a PriorityPicker per FU-type such that only one
 313         # non-busy FU will be picked
 314         issue_pps = {}
 315         fu_found = Signal() # take a note if no Function Unit was available
 316         for fname, fu_list in by_fnunit.items():
 317             i_pp = PriorityPicker(len(fu_list))
 318             m.submodules['i_pp_%s' % fname] = i_pp
 319             i_l = []
 320             for i, (funame, fu) in enumerate(fu_list):
 321                 # match the decoded instruction (e.do.fn_unit) against the
 322                 # "capability" of this FU, gate that by whether that FU is
 323                 # busy, and drop that into the PriorityPicker.
 324                 # this will give us an output of the first available *non-busy*
 325                 # Function Unit (Reservation Statio) capable of handling this
 326                 # instruction.
 327                 fnunit = fu.fnunit.value
 328                 en_req = Signal(name="issue_en_%s" % funame, reset_less=True)
 329                 fnmatch = (self.i.e.do.fn_unit & fnunit).bool()
 330                 comb += en_req.eq(fnmatch & ~fu.busy_o & self.p.i_valid)
 331                 i_l.append(en_req) # store in list for doing the Cat-trick
 332                 # picker output, gated by enable: store in fu_bitdict
 333                 po = Signal(name="o_issue_pick_"+funame) # picker output
 334                 comb += po.eq(i_pp.o[i] & i_pp.en_o)
 335                 comb += fu_bitdict[funame].eq(po)
 336                 comb += fu_selected[funame].eq(fu.busy_o | po)
 337                 # if we don't do this, then when there are no FUs available,
 338                 # the "p.o_ready" signal will go back "ok we accepted this
 339                 # instruction" which of course isn't true.
 340                 comb += fu_found.eq(~fnmatch | i_pp.en_o)
 341             # for each input, Cat them together and drop them into the picker
 342             comb += i_pp.i.eq(Cat(*i_l))
 343
 344         # sigh - need a NOP counter
 345         counter = Signal(2)
 346         with m.If(counter != 0):
 347             sync += counter.eq(counter - 1)
 348             comb += busy_o.eq(1)
 349
 350         with m.If(self.p.i_valid): # run only when valid
 351             with m.Switch(self.i.e.do.insn_type):
 352                 # check for ATTN: halt if true
 353                 with m.Case(MicrOp.OP_ATTN):
 354                     m.d.sync += self.o.core_terminate_o.eq(1)
 355
 356                 # fake NOP - this isn't really used (Issuer detects NOP)
 357                 with m.Case(MicrOp.OP_NOP):
 358                     sync += counter.eq(2)
 359                     comb += busy_o.eq(1)
 360
 361                 with m.Default():
 362                     # connect up instructions.  only one enabled at a time
 363                     for funame, fu in fus.items():
 364                         do = self.des[funame]
 365                         enable = fu_bitdict[funame]
 366
 367                         # run this FunctionUnit if enabled
 368                         # route op, issue, busy, read flags and mask to FU
 369                         with m.If(enable):
 370                             # operand comes from the *local*  decoder
 371                             comb += fu.oper_i.eq_from(do)
 372                             comb += fu.issue_i.eq(1) # issue when input valid
 373                             # rdmask, which is for registers, needs to come
 374                             # from the *main* decoder
 375                             rdmask = get_rdflags(self.i.e, fu)
 376                             comb += fu.rdmaskn.eq(~rdmask)
 377
 378         # if instruction is busy, set busy output for core.
 379         busys = map(lambda fu: fu.busy_o, fus.values())
 380         comb += busy_o.eq(Cat(*busys).bool())
 381
 382         # ready/valid signalling.  if busy, means refuse incoming issue.
 383         # (this is a global signal, TODO, change to one which allows
 384         # overlapping instructions)
 385         # also, if there was no fu found we must not send back a valid
 386         # indicator.  BUT, of course, when there is no instruction
 387         # we must ignore the fu_found flag, otherwise o_ready will never
 388         # be set when everything is idle
 389         comb += self.p.o_ready.eq(fu_found | ~self.p.i_valid)
 390
 391         # return both the function unit "enable" dict as well as the "busy".
 392         # the "busy-or-issued" can be passed in to the Read/Write port
 393         # connecters to give them permission to request access to regfiles
 394         return fu_bitdict, fu_selected
 395
 396     def connect_rdport(self, m, fu_bitdict, rdpickers, regfile, regname, fspec):
 397         comb, sync = m.d.comb, m.d.sync
 398         fus = self.fus.fus
 399         regs = self.regs
 400
 401         rpidx = regname
 402
 403         # select the required read port.  these are pre-defined sizes
 404         rfile = regs.rf[regfile.lower()]
 405         rport = rfile.r_ports[rpidx]
 406         print("read regfile", rpidx, regfile, regs.rf.keys(),
 407                               rfile, rfile.unary)
 408
 409         fspecs = fspec
 410         if not isinstance(fspecs, list):
 411             fspecs = [fspecs]
 412
 413         rdflags = []
 414         pplen = 0
 415         reads = []
 416         ppoffs = []
 417         for i, fspec in enumerate(fspecs):
 418             # get the regfile specs for this regfile port
 419             (rf, read, write, wid, fuspec) = fspec
 420             print ("fpsec", i, fspec, len(fuspec))
 421             ppoffs.append(pplen) # record offset for picker
 422             pplen += len(fuspec)
 423             name = "rdflag_%s_%s_%d" % (regfile, regname, i)
 424             rdflag = Signal(name=name, reset_less=True)
 425             comb += rdflag.eq(rf)
 426             rdflags.append(rdflag)
 427             reads.append(read)
 428
 429         print ("pplen", pplen)
 430
 431         # create a priority picker to manage this port
 432         rdpickers[regfile][rpidx] = rdpick = PriorityPicker(pplen)
 433         setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
 434
 435         rens = []
 436         addrs = []
 437         for i, fspec in enumerate(fspecs):
 438             (rf, read, write, wid, fuspec) = fspec
 439             # connect up the FU req/go signals, and the reg-read to the FU
 440             # and create a Read Broadcast Bus
 441             for pi, (funame, fu, idx) in enumerate(fuspec):
 442                 pi += ppoffs[i]
 443
 444                 # connect request-read to picker input, and output to go-rd
 445                 fu_active = fu_bitdict[funame]
 446                 name = "%s_%s_%s_%i" % (regfile, rpidx, funame, pi)
 447                 addr_en = Signal.like(reads[i], name="addr_en_"+name)
 448                 pick = Signal(name="pick_"+name)     # picker input
 449                 rp = Signal(name="rp_"+name)         # picker output
 450                 delay_pick = Signal(name="dp_"+name) # read-enable "underway"
 451
 452                 # exclude any currently-enabled read-request (mask out active)
 453                 comb += pick.eq(fu.rd_rel_o[idx] & fu_active & rdflags[i] &
 454                                 ~delay_pick)
 455                 comb += rdpick.i[pi].eq(pick)
 456                 comb += fu.go_rd_i[idx].eq(delay_pick) # pass in *delayed* pick
 457
 458                 # if picked, select read-port "reg select" number to port
 459                 comb += rp.eq(rdpick.o[pi] & rdpick.en_o)
 460                 sync += delay_pick.eq(rp) # delayed "pick"
 461                 comb += addr_en.eq(Mux(rp, reads[i], 0))
 462
 463                 # the read-enable happens combinatorially (see mux-bus below)
 464                 # but it results in the data coming out on a one-cycle delay.
 465                 if rfile.unary:
 466                     rens.append(addr_en)
 467                 else:
 468                     addrs.append(addr_en)
 469                     rens.append(rp)
 470
 471                 # use the *delayed* pick signal to put requested data onto bus
 472                 with m.If(delay_pick):
 473                     # connect regfile port to input, creating fan-out Bus
 474                     src = fu.src_i[idx]
 475                     print("reg connect widths",
 476                           regfile, regname, pi, funame,
 477                           src.shape(), rport.o_data.shape())
 478                     # all FUs connect to same port
 479                     comb += src.eq(rport.o_data)
 480
 481         # or-reduce the muxed read signals
 482         if rfile.unary:
 483             # for unary-addressed
 484             comb += rport.ren.eq(ortreereduce_sig(rens))
 485         else:
 486             # for binary-addressed
 487             comb += rport.addr.eq(ortreereduce_sig(addrs))
 488             comb += rport.ren.eq(Cat(*rens).bool())
 489             print ("binary", regfile, rpidx, rport, rport.ren, rens, addrs)
 490
 491     def connect_rdports(self, m, fu_bitdict):
 492         """connect read ports
 493
 494         orders the read regspecs into a dict-of-dicts, by regfile, by
 495         regport name, then connects all FUs that want that regport by
 496         way of a PriorityPicker.
 497         """
 498         comb, sync = m.d.comb, m.d.sync
 499         fus = self.fus.fus
 500         regs = self.regs
 501
 502         # dictionary of lists of regfile read ports
 503         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 504
 505         # okaay, now we need a PriorityPicker per regfile per regfile port
 506         # loootta pickers... peter piper picked a pack of pickled peppers...
 507         rdpickers = {}
 508         for regfile, spec in byregfiles_rd.items():
 509             fuspecs = byregfiles_rdspec[regfile]
 510             rdpickers[regfile] = {}
 511
 512             # argh.  an experiment to merge RA and RB in the INT regfile
 513             # (we have too many read/write ports)
 514             if self.regreduce_en:
 515                 if regfile == 'INT':
 516                     fuspecs['rabc'] = [fuspecs.pop('rb')]
 517                     fuspecs['rabc'].append(fuspecs.pop('rc'))
 518                     fuspecs['rabc'].append(fuspecs.pop('ra'))
 519                 if regfile == 'FAST':
 520                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
 521                     if 'fast2' in fuspecs:
 522                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
 523                     if 'fast3' in fuspecs:
 524                         fuspecs['fast1'].append(fuspecs.pop('fast3'))
 525
 526             # for each named regfile port, connect up all FUs to that port
 527             for (regname, fspec) in sort_fuspecs(fuspecs):
 528                 print("connect rd", regname, fspec)
 529                 self.connect_rdport(m, fu_bitdict, rdpickers, regfile,
 530                                        regname, fspec)
 531
 532     def connect_wrport(self, m, fu_bitdict, wrpickers, regfile, regname, fspec):
 533         comb, sync = m.d.comb, m.d.sync
 534         fus = self.fus.fus
 535         regs = self.regs
 536
 537         print("connect wr", regname, fspec)
 538         rpidx = regname
 539
 540         # select the required write port.  these are pre-defined sizes
 541         print(regfile, regs.rf.keys())
 542         rfile = regs.rf[regfile.lower()]
 543         wport = rfile.w_ports[rpidx]
 544
 545         fspecs = fspec
 546         if not isinstance(fspecs, list):
 547             fspecs = [fspecs]
 548
 549         pplen = 0
 550         writes = []
 551         ppoffs = []
 552         for i, fspec in enumerate(fspecs):
 553             # get the regfile specs for this regfile port
 554             (rf, read, write, wid, fuspec) = fspec
 555             print ("fpsec", i, fspec, len(fuspec))
 556             ppoffs.append(pplen) # record offset for picker
 557             pplen += len(fuspec)
 558
 559         # create a priority picker to manage this port
 560         wrpickers[regfile][rpidx] = wrpick = PriorityPicker(pplen)
 561         setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
 562
 563         wsigs = []
 564         wens = []
 565         addrs = []
 566         for i, fspec in enumerate(fspecs):
 567             # connect up the FU req/go signals and the reg-read to the FU
 568             # these are arbitrated by Data.ok signals
 569             (rf, read, write, wid, fuspec) = fspec
 570             for pi, (funame, fu, idx) in enumerate(fuspec):
 571                 pi += ppoffs[i]
 572
 573                 # write-request comes from dest.ok
 574                 dest = fu.get_out(idx)
 575                 fu_dest_latch = fu.get_fu_out(idx)  # latched output
 576                 name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 577                 wrflag = Signal(name=name, reset_less=True)
 578                 comb += wrflag.eq(dest.ok & fu.busy_o)
 579
 580                 # connect request-write to picker input, and output to go-wr
 581                 fu_active = fu_bitdict[funame]
 582                 pick = fu.wr.rel_o[idx] & fu_active  # & wrflag
 583                 comb += wrpick.i[pi].eq(pick)
 584                 # create a single-pulse go write from the picker output
 585                 wr_pick = Signal(name="wpick_%s_%s_%d" % (funame, regname, idx))
 586                 comb += wr_pick.eq(wrpick.o[pi] & wrpick.en_o)
 587                 comb += fu.go_wr_i[idx].eq(rising_edge(m, wr_pick))
 588
 589                 # connect the regspec write "reg select" number to this port
 590                 # only if one FU actually requests (and is granted) the port
 591                 # will the write-enable be activated
 592                 addr_en = Signal.like(write)
 593                 wp = Signal()
 594                 comb += wp.eq(wr_pick & wrpick.en_o)
 595                 comb += addr_en.eq(Mux(wp, write, 0))
 596                 if rfile.unary:
 597                     wens.append(addr_en)
 598                 else:
 599                     addrs.append(addr_en)
 600                     wens.append(wp)
 601
 602                 # connect regfile port to input
 603                 print("reg connect widths",
 604                       regfile, regname, pi, funame,
 605                       dest.shape(), wport.i_data.shape())
 606                 wsigs.append(fu_dest_latch)
 607
 608         # here is where we create the Write Broadcast Bus. simple, eh?
 609         comb += wport.i_data.eq(ortreereduce_sig(wsigs))
 610         if rfile.unary:
 611             # for unary-addressed
 612             comb += wport.wen.eq(ortreereduce_sig(wens))
 613         else:
 614             # for binary-addressed
 615             comb += wport.addr.eq(ortreereduce_sig(addrs))
 616             comb += wport.wen.eq(ortreereduce_sig(wens))
 617
 618     def connect_wrports(self, m, fu_bitdict):
 619         """connect write ports
 620
 621         orders the write regspecs into a dict-of-dicts, by regfile,
 622         by regport name, then connects all FUs that want that regport
 623         by way of a PriorityPicker.
 624
 625         note that the write-port wen, write-port data, and go_wr_i all need to
 626         be on the exact same clock cycle.  as there is a combinatorial loop bug
 627         at the moment, these all use sync.
 628         """
 629         comb, sync = m.d.comb, m.d.sync
 630         fus = self.fus.fus
 631         regs = self.regs
 632         # dictionary of lists of regfile write ports
 633         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 634
 635         # same for write ports.
 636         # BLECH!  complex code-duplication! BLECH!
 637         wrpickers = {}
 638         for regfile, spec in byregfiles_wr.items():
 639             fuspecs = byregfiles_wrspec[regfile]
 640             wrpickers[regfile] = {}
 641
 642             if self.regreduce_en:
 643                 # argh, more port-merging
 644                 if regfile == 'INT':
 645                     fuspecs['o'] = [fuspecs.pop('o')]
 646                     fuspecs['o'].append(fuspecs.pop('o1'))
 647                 if regfile == 'FAST':
 648                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
 649                     if 'fast2' in fuspecs:
 650                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
 651                     if 'fast3' in fuspecs:
 652                         fuspecs['fast1'].append(fuspecs.pop('fast3'))
 653
 654             for (regname, fspec) in sort_fuspecs(fuspecs):
 655                 self.connect_wrport(m, fu_bitdict, wrpickers,
 656                                         regfile, regname, fspec)
 657
 658     def get_byregfiles(self, readmode):
 659
 660         mode = "read" if readmode else "write"
 661         regs = self.regs
 662         fus = self.fus.fus
 663         e = self.i.e # decoded instruction to execute
 664
 665         # dictionary of lists of regfile ports
 666         byregfiles = {}
 667         byregfiles_spec = {}
 668         for (funame, fu) in fus.items():
 669             print("%s ports for %s" % (mode, funame))
 670             for idx in range(fu.n_src if readmode else fu.n_dst):
 671                 if readmode:
 672                     (regfile, regname, wid) = fu.get_in_spec(idx)
 673                 else:
 674                     (regfile, regname, wid) = fu.get_out_spec(idx)
 675                 print("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 676                 if readmode:
 677                     rdflag, read = regspec_decode_read(e, regfile, regname)
 678                     write = None
 679                 else:
 680                     rdflag, read = None, None
 681                     wrport, write = regspec_decode_write(e, regfile, regname)
 682                 if regfile not in byregfiles:
 683                     byregfiles[regfile] = {}
 684                     byregfiles_spec[regfile] = {}
 685                 if regname not in byregfiles_spec[regfile]:
 686                     byregfiles_spec[regfile][regname] = \
 687                         (rdflag, read, write, wid, [])
 688                 # here we start to create "lanes"
 689                 if idx not in byregfiles[regfile]:
 690                     byregfiles[regfile][idx] = []
 691                 fuspec = (funame, fu, idx)
 692                 byregfiles[regfile][idx].append(fuspec)
 693                 byregfiles_spec[regfile][regname][4].append(fuspec)
 694
 695         # ok just print that out, for convenience
 696         for regfile, spec in byregfiles.items():
 697             print("regfile %s ports:" % mode, regfile)
 698             fuspecs = byregfiles_spec[regfile]
 699             for regname, fspec in fuspecs.items():
 700                 [rdflag, read, write, wid, fuspec] = fspec
 701                 print("  rf %s port %s lane: %s" % (mode, regfile, regname))
 702                 print("  %s" % regname, wid, read, write, rdflag)
 703                 for (funame, fu, idx) in fuspec:
 704                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 705                     print("    ", funame, fu, idx, fusig)
 706                     print()
 707
 708         return byregfiles, byregfiles_spec
 709
 710     def __iter__(self):
 711         yield from self.fus.ports()
 712         yield from self.i.e.ports()
 713         yield from self.l0.ports()
 714         # TODO: regs
 715
 716     def ports(self):
 717         return list(self)
 718
 719
 720 if __name__ == '__main__':
 721     pspec = TestMemPspec(ldst_ifacetype='testpi',
 722                          imem_ifacetype='',
 723                          addr_wid=48,
 724                          mask_wid=8,
 725                          reg_wid=64)
 726     dut = NonProductionCore(pspec)
 727     vl = rtlil.convert(dut, ports=dut.ports())
 728     with open("test_core.il", "w") as f:
 729         f.write(vl)