3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 the principle here is to take the Function Units, analyse their regspecs,
8 and turn their requirements for access to register file read/write ports
9 into groupings by Register File and Register File Port name.
11 under each grouping - by regfile/port - a list of Function Units that
12 need to connect to that port is created. as these are a contended
13 resource a "Broadcast Bus" per read/write port is then also created,
14 with access to it managed by a PriorityPicker.
16 the brain-dead part of this module is that even though there is no
17 conflict of access, regfile read/write hazards are *not* analysed,
18 and consequently it is safer to wait for the Function Unit to complete
19 before allowing a new instruction to proceed.
20 (update: actually this is being added now:
21 https://bugs.libre-soc.org/show_bug.cgi?id=737)
24 from nmigen
import (Elaboratable
, Module
, Signal
, ResetSignal
, Cat
, Mux
,
26 from nmigen
.cli
import rtlil
28 from openpower
.decoder
.power_decoder2
import PowerDecodeSubset
29 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
30 from openpower
.decoder
.power_regspec_map
import regspec_decode_write
31 from openpower
.sv
.svp64
import SVP64Rec
33 from nmutil
.picker
import PriorityPicker
34 from nmutil
.util
import treereduce
35 from nmutil
.singlepipe
import ControlBase
37 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
, LDSTFunctionUnit
38 from soc
.regfile
.regfiles
import RegFiles
39 from openpower
.decoder
.power_decoder2
import get_rdflags
40 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
# test only
41 from soc
.config
.test
.test_loadstore
import TestMemPspec
42 from openpower
.decoder
.power_enums
import MicrOp
, Function
43 from soc
.simple
.core_data
import CoreInput
, CoreOutput
45 from collections
import defaultdict
, namedtuple
48 from nmutil
.util
import rising_edge
50 FUSpec
= namedtuple("FUSpec", ["funame", "fu", "idx"])
51 ByRegSpec
= namedtuple("ByRegSpec", ["okflag", "regport", "wid", "specs"])
53 # helper function for reducing a list of signals down to a parallel
55 def ortreereduce(tree
, attr
="o_data"):
56 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
59 def ortreereduce_sig(tree
):
60 return treereduce(tree
, operator
.or_
, lambda x
: x
)
63 # helper function to place full regs declarations first
64 def sort_fuspecs(fuspecs
):
66 for (regname
, fspec
) in fuspecs
.items():
67 if regname
.startswith("full"):
68 res
.append((regname
, fspec
))
69 for (regname
, fspec
) in fuspecs
.items():
70 if not regname
.startswith("full"):
71 res
.append((regname
, fspec
))
72 return res
# enumerate(res)
75 # derive from ControlBase rather than have a separate Stage instance,
76 # this is simpler to do
77 class NonProductionCore(ControlBase
):
78 def __init__(self
, pspec
):
81 # test is SVP64 is to be enabled
82 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
84 # test to see if regfile ports should be reduced
85 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
86 (pspec
.regreduce
== True))
88 # test to see if overlapping of instructions is allowed
89 # (not normally enabled for TestIssuer FSM but useful for checking
90 # the bitvector hazard detection, before doing In-Order)
91 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
92 (pspec
.allow_overlap
== True))
95 self
.make_hazard_vecs
= self
.allow_overlap
96 self
.core_type
= "fsm"
97 if hasattr(pspec
, "core_type"):
98 self
.core_type
= pspec
.core_type
100 super().__init
__(stage
=self
)
102 # single LD/ST funnel for memory access
103 self
.l0
= l0
= TstL0CacheBuffer(pspec
, n_units
=1)
106 # function units (only one each)
107 # only include mmu if enabled in pspec
108 self
.fus
= AllFunctionUnits(pspec
, pilist
=[pi
])
110 # link LoadStore1 into MMU
111 mmu
= self
.fus
.get_fu('mmu0')
112 print ("core pspec", pspec
.ldst_ifacetype
)
113 print ("core mmu", mmu
)
115 print ("core lsmem.lsi", l0
.cmpi
.lsmem
.lsi
)
116 mmu
.alu
.set_ldst_interface(l0
.cmpi
.lsmem
.lsi
)
118 # register files (yes plural)
119 self
.regs
= RegFiles(pspec
, make_hazard_vecs
=self
.make_hazard_vecs
)
121 # set up input and output: unusual requirement to set data directly
122 # (due to the way that the core is set up in a different domain,
123 # see TestIssuer.setup_peripherals
124 self
.p
.i_data
, self
.n
.o_data
= self
.new_specs(None)
125 self
.i
, self
.o
= self
.p
.i_data
, self
.n
.o_data
127 # actual internal input data used (captured)
128 self
.ireg
= self
.ispec()
130 # create per-FU instruction decoders (subsetted). these "satellite"
131 # decoders reduce wire fan-out from the one (main) PowerDecoder2
132 # (used directly by the trap unit) to the *twelve* (or more)
133 # Function Units. we can either have 32 wires (the instruction)
134 # to each, or we can have well over a 200 wire fan-out (to 12
135 # ALUs). it's an easy choice to make.
139 # eep, these should be *per FU* i.e. for FunctionUnitBaseMulti
140 # they should be shared (put into the ALU *once*).
142 for funame
, fu
in self
.fus
.fus
.items():
143 f_name
= fu
.fnunit
.name
144 fnunit
= fu
.fnunit
.value
145 opkls
= fu
.opsubsetkls
147 # TRAP decoder is the *main* decoder
148 self
.trapunit
= funame
150 assert funame
not in self
.decoders
151 self
.decoders
[funame
] = PowerDecodeSubset(None, opkls
, f_name
,
153 state
=self
.ireg
.state
,
154 svp64_en
=self
.svp64_en
,
155 regreduce_en
=self
.regreduce_en
)
156 self
.des
[funame
] = self
.decoders
[funame
].do
158 # create per-Function Unit write-after-write hazard signals
159 # yes, really, this should have been added in ReservationStations
161 for funame
, fu
in self
.fus
.fus
.items():
162 fu
._waw
_hazard
= Signal(name
="waw_%s" % funame
)
164 # share the SPR decoder with the MMU if it exists
165 if "mmu0" in self
.decoders
:
166 self
.decoders
["mmu0"].mmu0_spr_dec
= self
.decoders
["spr0"]
168 # next 3 functions are Stage API Compliance
169 def setup(self
, m
, i
):
173 return CoreInput(self
.pspec
, self
.svp64_en
, self
.regreduce_en
)
178 # elaborate function to create HDL
179 def elaborate(self
, platform
):
180 m
= super().elaborate(platform
)
182 # for testing purposes, to cut down on build time in coriolis2
183 if hasattr(self
.pspec
, "nocore") and self
.pspec
.nocore
== True:
184 x
= Signal() # dummy signal
189 m
.submodules
.fus
= self
.fus
190 m
.submodules
.l0
= l0
= self
.l0
191 self
.regs
.elaborate_into(m
, platform
)
195 # amalgamate write-hazards into a single top-level Signal
196 self
.waw_hazard
= Signal()
198 for funame
, fu
in self
.fus
.fus
.items():
199 whaz
.append(fu
._waw
_hazard
)
200 comb
+= self
.waw_hazard
.eq(Cat(*whaz
).bool())
203 self
.connect_satellite_decoders(m
)
205 # ssh, cheat: trap uses the main decoder because of the rewriting
206 self
.des
[self
.trapunit
] = self
.ireg
.e
.do
208 # connect up Function Units, then read/write ports, and hazard conflict
209 self
.issue_conflict
= Signal()
210 fu_bitdict
, fu_selected
= self
.connect_instruction(m
)
211 raw_hazard
= self
.connect_rdports(m
, fu_bitdict
, fu_selected
)
212 self
.connect_wrports(m
, fu_bitdict
, fu_selected
)
213 if self
.allow_overlap
:
214 comb
+= self
.issue_conflict
.eq(raw_hazard
)
216 # note if an exception happened. in a pipelined or OoO design
217 # this needs to be accompanied by "shadowing" (or stalling)
219 for exc
in self
.fus
.excs
.values():
220 el
.append(exc
.happened
)
221 if len(el
) > 0: # at least one exception
222 comb
+= self
.o
.exc_happened
.eq(Cat(*el
).bool())
226 def connect_satellite_decoders(self
, m
):
228 for k
, v
in self
.decoders
.items():
229 # connect each satellite decoder and give it the instruction.
230 # as subset decoders this massively reduces wire fanout given
231 # the large number of ALUs
232 m
.submodules
["dec_%s" % k
] = v
233 comb
+= v
.dec
.raw_opcode_in
.eq(self
.ireg
.raw_insn_i
)
234 comb
+= v
.dec
.bigendian
.eq(self
.ireg
.bigendian_i
)
235 # sigh due to SVP64 RA_OR_ZERO detection connect these too
236 comb
+= v
.sv_a_nz
.eq(self
.ireg
.sv_a_nz
)
238 comb
+= v
.pred_sm
.eq(self
.ireg
.sv_pred_sm
)
239 comb
+= v
.pred_dm
.eq(self
.ireg
.sv_pred_dm
)
240 if k
!= self
.trapunit
:
241 comb
+= v
.sv_rm
.eq(self
.ireg
.sv_rm
) # pass through SVP64 RM
242 comb
+= v
.is_svp64_mode
.eq(self
.ireg
.is_svp64_mode
)
243 # only the LDST PowerDecodeSubset *actually* needs to
244 # know to use the alternative decoder. this is all
246 if k
.lower().startswith("ldst"):
247 comb
+= v
.use_svp64_ldst_dec
.eq(
248 self
.ireg
.use_svp64_ldst_dec
)
250 def connect_instruction(self
, m
):
251 """connect_instruction
253 uses decoded (from PowerOp) function unit information from CSV files
254 to ascertain which Function Unit should deal with the current
257 some (such as OP_ATTN, OP_NOP) are dealt with here, including
258 ignoring it and halting the processor. OP_NOP is a bit annoying
259 because the issuer expects busy flag still to be raised then lowered.
260 (this requires a fake counter to be set).
262 comb
, sync
= m
.d
.comb
, m
.d
.sync
265 # indicate if core is busy
266 busy_o
= self
.o
.busy_o
267 any_busy_o
= self
.o
.any_busy_o
269 # connect up temporary copy of incoming instruction. the FSM will
270 # either blat the incoming instruction (if valid) into self.ireg
271 # or if the instruction could not be delivered, keep dropping the
272 # latched copy into ireg
273 ilatch
= self
.ispec()
274 self
.instr_active
= Signal()
276 # enable/busy-signals for each FU, get one bit for each FU (by name)
277 fu_enable
= Signal(len(fus
), reset_less
=True)
278 fu_busy
= Signal(len(fus
), reset_less
=True)
281 for i
, funame
in enumerate(fus
.keys()):
282 fu_bitdict
[funame
] = fu_enable
[i
]
283 fu_selected
[funame
] = fu_busy
[i
]
285 # identify function units and create a list by fnunit so that
286 # PriorityPickers can be created for selecting one of them that
287 # isn't busy at the time the incoming instruction needs passing on
288 by_fnunit
= defaultdict(list)
289 for fname
, member
in Function
.__members
__.items():
290 for funame
, fu
in fus
.items():
291 fnunit
= fu
.fnunit
.value
292 if member
.value
& fnunit
: # this FU handles this type of op
293 by_fnunit
[fname
].append((funame
, fu
)) # add by Function
295 # ok now just print out the list of FUs by Function, because we can
296 for fname
, fu_list
in by_fnunit
.items():
297 print ("FUs by type", fname
, fu_list
)
299 # now create a PriorityPicker per FU-type such that only one
300 # non-busy FU will be picked
302 fu_found
= Signal() # take a note if no Function Unit was available
303 for fname
, fu_list
in by_fnunit
.items():
304 i_pp
= PriorityPicker(len(fu_list
))
305 m
.submodules
['i_pp_%s' % fname
] = i_pp
307 for i
, (funame
, fu
) in enumerate(fu_list
):
308 # match the decoded instruction (e.do.fn_unit) against the
309 # "capability" of this FU, gate that by whether that FU is
310 # busy, and drop that into the PriorityPicker.
311 # this will give us an output of the first available *non-busy*
312 # Function Unit (Reservation Statio) capable of handling this
314 fnunit
= fu
.fnunit
.value
315 en_req
= Signal(name
="issue_en_%s" % funame
, reset_less
=True)
316 fnmatch
= (self
.ireg
.e
.do
.fn_unit
& fnunit
).bool()
317 comb
+= en_req
.eq(fnmatch
& ~fu
.busy_o
&
319 i_l
.append(en_req
) # store in list for doing the Cat-trick
320 # picker output, gated by enable: store in fu_bitdict
321 po
= Signal(name
="o_issue_pick_"+funame
) # picker output
322 comb
+= po
.eq(i_pp
.o
[i
] & i_pp
.en_o
)
323 comb
+= fu_bitdict
[funame
].eq(po
)
324 comb
+= fu_selected
[funame
].eq(fu
.busy_o | po
)
325 # if we don't do this, then when there are no FUs available,
326 # the "p.o_ready" signal will go back "ok we accepted this
327 # instruction" which of course isn't true.
328 with m
.If(i_pp
.en_o
):
329 comb
+= fu_found
.eq(1)
330 # for each input, Cat them together and drop them into the picker
331 comb
+= i_pp
.i
.eq(Cat(*i_l
))
333 # rdmask, which is for registers needs to come from the *main* decoder
334 for funame
, fu
in fus
.items():
335 rdmask
= get_rdflags(self
.ireg
.e
, fu
)
336 comb
+= fu
.rdmaskn
.eq(~rdmask
)
338 # sigh - need a NOP counter
340 with m
.If(counter
!= 0):
341 sync
+= counter
.eq(counter
- 1)
344 # default to reading from incoming instruction: may be overridden
345 # by copy from latch when "waiting"
346 comb
+= self
.ireg
.eq(self
.i
)
347 # always say "ready" except if overridden
348 comb
+= self
.p
.o_ready
.eq(1)
351 with m
.State("READY"):
352 with m
.If(self
.p
.i_valid
): # run only when valid
353 with m
.Switch(self
.ireg
.e
.do
.insn_type
):
354 # check for ATTN: halt if true
355 with m
.Case(MicrOp
.OP_ATTN
):
356 m
.d
.sync
+= self
.o
.core_terminate_o
.eq(1)
358 # fake NOP - this isn't really used (Issuer detects NOP)
359 with m
.Case(MicrOp
.OP_NOP
):
360 sync
+= counter
.eq(2)
364 comb
+= self
.instr_active
.eq(1)
365 comb
+= self
.p
.o_ready
.eq(0)
366 # connect instructions. only one enabled at a time
367 for funame
, fu
in fus
.items():
368 do
= self
.des
[funame
]
369 enable
= fu_bitdict
[funame
]
371 # run this FunctionUnit if enabled route op,
372 # issue, busy, read flags and mask to FU
374 # operand comes from the *local* decoder
375 # do not actually issue, though, if there
376 # is a waw hazard. decoder has to still
377 # be asserted in order to detect that, tho
378 comb
+= fu
.oper_i
.eq_from(do
)
379 # issue when valid (and no write-hazard)
380 comb
+= fu
.issue_i
.eq(~self
.waw_hazard
)
381 # instruction ok, indicate ready
382 comb
+= self
.p
.o_ready
.eq(1)
384 if self
.allow_overlap
:
385 with m
.If(~fu_found | self
.waw_hazard
):
386 # latch copy of instruction
387 sync
+= ilatch
.eq(self
.i
)
388 comb
+= self
.p
.o_ready
.eq(1) # accept
392 with m
.State("WAITING"):
393 comb
+= self
.instr_active
.eq(1)
394 comb
+= self
.p
.o_ready
.eq(0)
396 # using copy of instruction, keep waiting until an FU is free
397 comb
+= self
.ireg
.eq(ilatch
)
398 with m
.If(fu_found
): # wait for conflict to clear
399 # connect instructions. only one enabled at a time
400 for funame
, fu
in fus
.items():
401 do
= self
.des
[funame
]
402 enable
= fu_bitdict
[funame
]
404 # run this FunctionUnit if enabled route op,
405 # issue, busy, read flags and mask to FU
407 # operand comes from the *local* decoder,
408 # which is asserted even if not issued,
409 # so that WaW-detection can check for hazards.
410 # only if the waw hazard is clear does the
411 # instruction actually get issued
412 comb
+= fu
.oper_i
.eq_from(do
)
414 comb
+= fu
.issue_i
.eq(~self
.waw_hazard
)
415 with m
.If(~self
.waw_hazard
):
416 comb
+= self
.p
.o_ready
.eq(1)
420 print ("core: overlap allowed", self
.allow_overlap
)
421 # true when any FU is busy (including the cycle where it is perhaps
422 # to be issued - because that's what fu_busy is)
423 comb
+= any_busy_o
.eq(fu_busy
.bool())
424 if not self
.allow_overlap
:
425 # for simple non-overlap, if any instruction is busy, set
426 # busy output for core.
427 comb
+= busy_o
.eq(any_busy_o
)
429 # sigh deal with a fun situation that needs to be investigated
431 with m
.If(self
.issue_conflict
):
433 # make sure that LDST, SPR, MMU, Branch and Trap all say "busy"
434 # and do not allow overlap. these are all the ones that
435 # are non-forward-progressing: exceptions etc. that otherwise
436 # change CoreState for some reason (MSR, PC, SVSTATE)
437 for funame
, fu
in fus
.items():
438 if (funame
.lower().startswith('ldst') or
439 funame
.lower().startswith('branch') or
440 funame
.lower().startswith('mmu') or
441 funame
.lower().startswith('spr') or
442 funame
.lower().startswith('trap')):
443 with m
.If(fu
.busy_o
):
446 # return both the function unit "enable" dict as well as the "busy".
447 # the "busy-or-issued" can be passed in to the Read/Write port
448 # connecters to give them permission to request access to regfiles
449 return fu_bitdict
, fu_selected
451 def connect_rdport(self
, m
, fu_bitdict
, fu_selected
,
452 rdpickers
, regfile
, regname
, fspec
):
453 comb
, sync
= m
.d
.comb
, m
.d
.sync
459 # select the required read port. these are pre-defined sizes
460 rfile
= regs
.rf
[regfile
.lower()]
461 rport
= rfile
.r_ports
[rpidx
]
462 print("read regfile", rpidx
, regfile
, regs
.rf
.keys(),
465 # for checking if the read port has an outstanding write
466 if self
.make_hazard_vecs
:
467 wv
= regs
.wv
[regfile
.lower()]
468 wvchk
= wv
.q_int
# write-vec bit-level hazard check
470 # if a hazard is detected on this read port, simply blithely block
471 # every FU from reading on it. this is complete overkill but very
473 hazard_detected
= Signal(name
="raw_%s_%s" % (regfile
, rpidx
))
476 if not isinstance(fspecs
, list):
482 for i
, fspec
in enumerate(fspecs
):
483 # get the regfile specs for this regfile port
484 print ("fpsec", i
, fspec
, len(fspec
.specs
))
485 name
= "%s_%s_%d" % (regfile
, regname
, i
)
486 ppoffs
.append(pplen
) # record offset for picker
487 pplen
+= len(fspec
.specs
)
488 rdflag
= Signal(name
="rdflag_"+name
, reset_less
=True)
489 comb
+= rdflag
.eq(fspec
.okflag
)
490 rdflags
.append(rdflag
)
492 print ("pplen", pplen
)
494 # create a priority picker to manage this port
495 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(pplen
)
496 m
.submodules
["rdpick_%s_%s" % (regfile
, rpidx
)] = rdpick
502 for i
, fspec
in enumerate(fspecs
):
503 (rf
, _read
, wid
, fuspecs
) = \
504 (fspec
.okflag
, fspec
.regport
, fspec
.wid
, fspec
.specs
)
505 # connect up the FU req/go signals, and the reg-read to the FU
506 # and create a Read Broadcast Bus
507 for pi
, fuspec
in enumerate(fspec
.specs
):
508 (funame
, fu
, idx
) = (fuspec
.funame
, fuspec
.fu
, fuspec
.idx
)
510 name
= "%s_%s_%s_%i" % (regfile
, rpidx
, funame
, pi
)
511 fu_active
= fu_selected
[funame
]
512 fu_issued
= fu_bitdict
[funame
]
514 # get (or set up) a latched copy of read register number
515 # and (sigh) also the read-ok flag
516 # TODO: use nmutil latchregister
517 rhname
= "%s_%s_%d" % (regfile
, regname
, i
)
518 rdflag
= Signal(name
="rdflag_%s_%s" % (funame
, rhname
),
520 if rhname
not in fu
.rf_latches
:
521 rfl
= Signal(name
="rdflag_latch_"+rhname
)
522 fu
.rf_latches
[rhname
] = rfl
523 with m
.If(fu
.issue_i
):
524 sync
+= rfl
.eq(rdflags
[i
])
526 rfl
= fu
.rf_latches
[rhname
]
528 # now the register port
529 rname
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, pi
)
530 read
= Signal
.like(_read
, name
="read_"+rname
)
531 if rname
not in fu
.rd_latches
:
532 rdl
= Signal
.like(_read
, name
="rdlatch_"+rname
)
533 fu
.rd_latches
[rname
] = rdl
534 with m
.If(fu
.issue_i
):
535 sync
+= rdl
.eq(_read
)
537 rdl
= fu
.rd_latches
[rname
]
539 # make the read immediately available on issue cycle
540 # after the read cycle, otherwies use the latched copy.
541 # this captures the regport and okflag on issue
542 with m
.If(fu
.issue_i
):
543 comb
+= read
.eq(_read
)
544 comb
+= rdflag
.eq(rdflags
[i
])
547 comb
+= rdflag
.eq(rfl
)
549 # connect request-read to picker input, and output to go-rd
550 addr_en
= Signal
.like(read
, name
="addr_en_"+name
)
551 pick
= Signal(name
="pick_"+name
) # picker input
552 rp
= Signal(name
="rp_"+name
) # picker output
553 delay_pick
= Signal(name
="dp_"+name
) # read-enable "underway"
554 rhazard
= Signal(name
="rhaz_"+name
)
556 # exclude any currently-enabled read-request (mask out active)
557 # entirely block anything hazarded from being picked
558 comb
+= pick
.eq(fu
.rd_rel_o
[idx
] & fu_active
& rdflag
&
559 ~delay_pick
& ~rhazard
)
560 comb
+= rdpick
.i
[pi
].eq(pick
)
561 comb
+= fu
.go_rd_i
[idx
].eq(delay_pick
) # pass in *delayed* pick
563 # if picked, select read-port "reg select" number to port
564 comb
+= rp
.eq(rdpick
.o
[pi
] & rdpick
.en_o
)
565 sync
+= delay_pick
.eq(rp
) # delayed "pick"
566 comb
+= addr_en
.eq(Mux(rp
, read
, 0))
568 # the read-enable happens combinatorially (see mux-bus below)
569 # but it results in the data coming out on a one-cycle delay.
573 addrs
.append(addr_en
)
576 # use the *delayed* pick signal to put requested data onto bus
577 with m
.If(delay_pick
):
578 # connect regfile port to input, creating fan-out Bus
580 print("reg connect widths",
581 regfile
, regname
, pi
, funame
,
582 src
.shape(), rport
.o_data
.shape())
583 # all FUs connect to same port
584 comb
+= src
.eq(rport
.o_data
)
586 if not self
.make_hazard_vecs
:
589 # read the write-hazard bitvector (wv) for any bit that is
590 wvchk_en
= Signal(len(wvchk
), name
="wv_chk_addr_en_"+name
)
591 issue_active
= Signal(name
="rd_iactive_"+name
)
592 # XXX combinatorial loop here
593 comb
+= issue_active
.eq(fu_active
& rdflag
)
594 with m
.If(issue_active
):
596 comb
+= wvchk_en
.eq(read
)
598 comb
+= wvchk_en
.eq(1<<read
)
599 # if FU is busy (which doesn't get set at the same time as
600 # issue) and no hazard was detected, clear wvchk_en (i.e.
601 # stop checking for hazards). there is a loop here, but it's
602 # via a DFF, so is ok. some linters may complain, but hey.
603 with m
.If(fu
.busy_o
& ~rhazard
):
604 comb
+= wvchk_en
.eq(0)
606 # read-hazard is ANDed with (filtered by) what is actually
608 comb
+= rhazard
.eq((wvchk
& wvchk_en
).bool())
610 wvens
.append(wvchk_en
)
612 # or-reduce the muxed read signals
614 # for unary-addressed
615 comb
+= rport
.ren
.eq(ortreereduce_sig(rens
))
617 # for binary-addressed
618 comb
+= rport
.addr
.eq(ortreereduce_sig(addrs
))
619 comb
+= rport
.ren
.eq(Cat(*rens
).bool())
620 print ("binary", regfile
, rpidx
, rport
, rport
.ren
, rens
, addrs
)
622 if not self
.make_hazard_vecs
:
623 return Const(0) # declare "no hazards"
625 # enable the read bitvectors for this issued instruction
626 # and return whether any write-hazard bit is set
627 wvchk_and
= Signal(len(wvchk
), name
="wv_chk_"+name
)
628 comb
+= wvchk_and
.eq(wvchk
& ortreereduce_sig(wvens
))
629 comb
+= hazard_detected
.eq(wvchk_and
.bool())
630 return hazard_detected
632 def connect_rdports(self
, m
, fu_bitdict
, fu_selected
):
633 """connect read ports
635 orders the read regspecs into a dict-of-dicts, by regfile, by
636 regport name, then connects all FUs that want that regport by
637 way of a PriorityPicker.
639 comb
, sync
= m
.d
.comb
, m
.d
.sync
644 # dictionary of lists of regfile read ports
645 byregfiles_rd
, byregfiles_rdspec
= self
.get_byregfiles(True)
647 # okaay, now we need a PriorityPicker per regfile per regfile port
648 # loootta pickers... peter piper picked a pack of pickled peppers...
650 for regfile
, spec
in byregfiles_rd
.items():
651 fuspecs
= byregfiles_rdspec
[regfile
]
652 rdpickers
[regfile
] = {}
654 # argh. an experiment to merge RA and RB in the INT regfile
655 # (we have too many read/write ports)
656 if self
.regreduce_en
:
658 fuspecs
['rabc'] = [fuspecs
.pop('rb')]
659 fuspecs
['rabc'].append(fuspecs
.pop('rc'))
660 fuspecs
['rabc'].append(fuspecs
.pop('ra'))
661 if regfile
== 'FAST':
662 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
663 if 'fast2' in fuspecs
:
664 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
665 if 'fast3' in fuspecs
:
666 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
668 # for each named regfile port, connect up all FUs to that port
669 # also return (and collate) hazard detection)
670 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
671 print("connect rd", regname
, fspec
)
672 rh
= self
.connect_rdport(m
, fu_bitdict
, fu_selected
,
677 return Cat(*rd_hazard
).bool()
679 def make_hazards(self
, m
, regfile
, rfile
, wvclr
, wvset
,
680 funame
, regname
, idx
,
681 addr_en
, wp
, fu
, fu_active
, wrflag
, write
,
683 """make_hazards: a setter and a clearer for the regfile write ports
685 setter is at issue time (using PowerDecoder2 regfile write numbers)
686 clearer is at regfile write time (when FU has said what to write to)
688 there is *one* unusual case here which has to be dealt with:
689 when the Function Unit does *NOT* request a write to the regfile
690 (has its data.ok bit CLEARED). this is perfectly legitimate.
693 comb
, sync
= m
.d
.comb
, m
.d
.sync
694 name
= "%s_%s_%d" % (funame
, regname
, idx
)
696 # connect up the bitvector write hazard. unlike the
697 # regfile writeports, a ONE must be written to the corresponding
698 # bit of the hazard bitvector (to indicate the existence of
701 # the detection of what shall be written to is based
702 # on *issue*. it is delayed by 1 cycle so that instructions
703 # "addi 5,5,0x2" do not cause combinatorial loops due to
704 # fake-dependency on *themselves*. this will totally fail
705 # spectacularly when doing multi-issue
706 print ("write vector (for regread)", regfile
, wvset
)
707 wviaddr_en
= Signal(len(wvset
), name
="wv_issue_addr_en_"+name
)
708 issue_active
= Signal(name
="iactive_"+name
)
709 sync
+= issue_active
.eq(fu
.issue_i
& fu_active
& wrflag
)
710 with m
.If(issue_active
):
712 comb
+= wviaddr_en
.eq(write
)
714 comb
+= wviaddr_en
.eq(1<<write
)
716 # deal with write vector clear: this kicks in when the regfile
717 # is written to, and clears the corresponding bitvector entry
718 print ("write vector", regfile
, wvclr
)
719 wvaddr_en
= Signal(len(wvclr
), name
="wvaddr_en_"+name
)
721 comb
+= wvaddr_en
.eq(addr_en
)
724 comb
+= wvaddr_en
.eq(1<<addr_en
)
726 # XXX ASSUME that LDSTFunctionUnit always sets the data it intends to
727 # this may NOT be the case when an exception occurs
728 if isinstance(fu
, LDSTFunctionUnit
):
729 return wvaddr_en
, wviaddr_en
731 # okaaay, this is preparation for the awkward case.
732 # * latch a copy of wrflag when issue goes high.
733 # * when the fu_wrok (data.ok) flag is NOT set,
734 # but the FU is done, the FU is NEVER going to write
735 # so the bitvector has to be cleared.
736 latch_wrflag
= Signal(name
="latch_wrflag_"+name
)
737 with m
.If(~fu
.busy_o
):
738 sync
+= latch_wrflag
.eq(0)
739 with m
.If(fu
.issue_i
& fu_active
):
740 sync
+= latch_wrflag
.eq(wrflag
)
741 with m
.If(fu
.alu_done_o
& latch_wrflag
& ~fu_wrok
):
743 comb
+= wvaddr_en
.eq(write
) # addr_en gated with wp, don't use
745 comb
+= wvaddr_en
.eq(1<<addr_en
) # binary addr_en not gated
747 return wvaddr_en
, wviaddr_en
749 def connect_wrport(self
, m
, fu_bitdict
, fu_selected
,
750 wrpickers
, regfile
, regname
, fspec
):
751 comb
, sync
= m
.d
.comb
, m
.d
.sync
757 # select the required write port. these are pre-defined sizes
758 rfile
= regs
.rf
[regfile
.lower()]
759 wport
= rfile
.w_ports
[rpidx
]
761 print("connect wr", regname
, "unary", rfile
.unary
, fspec
)
762 print(regfile
, regs
.rf
.keys())
764 # select the write-protection hazard vector. note that this still
765 # requires to WRITE to the hazard bitvector! read-requests need
766 # to RAISE the bitvector (set it to 1), which, duh, requires a WRITE
767 if self
.make_hazard_vecs
:
768 wv
= regs
.wv
[regfile
.lower()]
769 wvset
= wv
.s
# write-vec bit-level hazard ctrl
770 wvclr
= wv
.r
# write-vec bit-level hazard ctrl
771 wvchk
= wv
.q
# write-after-write hazard check
772 wvchk_qint
= wv
.q
# write-after-write hazard check, NOT delayed
775 if not isinstance(fspecs
, list):
782 for i
, fspec
in enumerate(fspecs
):
783 # get the regfile specs for this regfile port
784 (wf
, _write
, wid
, fuspecs
) = \
785 (fspec
.okflag
, fspec
.regport
, fspec
.wid
, fspec
.specs
)
786 print ("fpsec", i
, "wrflag", wf
, fspec
, len(fuspecs
))
787 ppoffs
.append(pplen
) # record offset for picker
788 pplen
+= len(fuspecs
)
790 name
= "%s_%s_%d" % (regfile
, regname
, i
)
791 wrflag
= Signal(name
="wr_flag_"+name
)
793 comb
+= wrflag
.eq(wf
)
796 wrflags
.append(wrflag
)
798 # create a priority picker to manage this port
799 wrpickers
[regfile
][rpidx
] = wrpick
= PriorityPicker(pplen
)
800 m
.submodules
["wrpick_%s_%s" % (regfile
, rpidx
)] = wrpick
807 #wvens = [] - not needed: reading of writevec is permanently held hi
809 for i
, fspec
in enumerate(fspecs
):
810 # connect up the FU req/go signals and the reg-read to the FU
811 # these are arbitrated by Data.ok signals
812 (wf
, _write
, wid
, fuspecs
) = \
813 (fspec
.okflag
, fspec
.regport
, fspec
.wid
, fspec
.specs
)
814 for pi
, fuspec
in enumerate(fspec
.specs
):
815 (funame
, fu
, idx
) = (fuspec
.funame
, fuspec
.fu
, fuspec
.idx
)
816 fu_requested
= fu_bitdict
[funame
]
818 name
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, idx
)
819 # get (or set up) a write-latched copy of write register number
820 write
= Signal
.like(_write
, name
="write_"+name
)
821 rname
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, idx
)
822 if rname
not in fu
.wr_latches
:
823 wrl
= Signal
.like(_write
, name
="wrlatch_"+rname
)
824 fu
.wr_latches
[rname
] = write
825 # do not depend on fu.issue_i here, it creates a
826 # combinatorial loop on waw checking. using the FU
827 # "enable" bitdict entry for this FU is sufficient,
828 # because the PowerDecoder2 read/write nums are
829 # valid continuously when the instruction is valid
830 with m
.If(fu_requested
):
831 sync
+= wrl
.eq(_write
)
832 comb
+= write
.eq(_write
)
834 comb
+= write
.eq(wrl
)
836 write
= fu
.wr_latches
[rname
]
838 # write-request comes from dest.ok
839 dest
= fu
.get_out(idx
)
840 fu_dest_latch
= fu
.get_fu_out(idx
) # latched output
841 name
= "%s_%s_%d" % (funame
, regname
, idx
)
842 fu_wrok
= Signal(name
="fu_wrok_"+name
, reset_less
=True)
843 comb
+= fu_wrok
.eq(dest
.ok
& fu
.busy_o
)
845 # connect request-write to picker input, and output to go-wr
846 fu_active
= fu_selected
[funame
]
847 pick
= fu
.wr
.rel_o
[idx
] & fu_active
848 comb
+= wrpick
.i
[pi
].eq(pick
)
849 # create a single-pulse go write from the picker output
850 wr_pick
= Signal(name
="wpick_%s_%s_%d" % (funame
, regname
, idx
))
851 comb
+= wr_pick
.eq(wrpick
.o
[pi
] & wrpick
.en_o
)
852 comb
+= fu
.go_wr_i
[idx
].eq(rising_edge(m
, wr_pick
))
854 # connect the regspec write "reg select" number to this port
855 # only if one FU actually requests (and is granted) the port
856 # will the write-enable be activated
857 wname
= "waddr_en_%s_%s_%d" % (funame
, regname
, idx
)
858 addr_en
= Signal
.like(write
, name
=wname
)
860 comb
+= wp
.eq(wr_pick
& wrpick
.en_o
)
861 comb
+= addr_en
.eq(Mux(wp
, write
, 0))
865 addrs
.append(addr_en
)
868 # connect regfile port to input
869 print("reg connect widths",
870 regfile
, regname
, pi
, funame
,
871 dest
.shape(), wport
.i_data
.shape())
872 wsigs
.append(fu_dest_latch
)
874 # now connect up the bitvector write hazard
875 if not self
.make_hazard_vecs
:
877 res
= self
.make_hazards(m
, regfile
, rfile
, wvclr
, wvset
,
878 funame
, regname
, idx
,
879 addr_en
, wp
, fu
, fu_active
,
880 wrflags
[i
], write
, fu_wrok
)
881 wvaddr_en
, wv_issue_en
= res
882 wvclren
.append(wvaddr_en
) # set only: no data => clear bit
883 wvseten
.append(wv_issue_en
) # set data same as enable
885 # read the write-hazard bitvector (wv) for any bit that is
886 fu_requested
= fu_bitdict
[funame
]
887 wvchk_en
= Signal(len(wvchk
), name
="waw_chk_addr_en_"+name
)
888 issue_active
= Signal(name
="waw_iactive_"+name
)
889 whazard
= Signal(name
="whaz_"+name
)
891 # XXX EEK! STATE regfile (branch) does not have an
892 # write-active indicator in regspec_decode_write()
893 print ("XXX FIXME waw_iactive", issue_active
,
896 # check bits from the incoming instruction. note (back
897 # in connect_instruction) that the decoder is held for
898 # us to be able to do this, here... *without* issue being
899 # held HI. we MUST NOT gate this with fu.issue_i or
900 # with fu_bitdict "enable": it would create a loop
901 comb
+= issue_active
.eq(wf
)
902 with m
.If(issue_active
):
904 comb
+= wvchk_en
.eq(write
)
906 comb
+= wvchk_en
.eq(1<<write
)
907 # if FU is busy (which doesn't get set at the same time as
908 # issue) and no hazard was detected, clear wvchk_en (i.e.
909 # stop checking for hazards). there is a loop here, but it's
910 # via a DFF, so is ok. some linters may complain, but hey.
911 with m
.If(fu
.busy_o
& ~whazard
):
912 comb
+= wvchk_en
.eq(0)
914 # write-hazard is ANDed with (filtered by) what is actually
915 # being requested. the wvchk data is on a one-clock delay,
916 # and wvchk_en comes directly from the main decoder
917 comb
+= whazard
.eq((wvchk_qint
& wvchk_en
).bool())
919 comb
+= fu
._waw
_hazard
.eq(1)
921 #wvens.append(wvchk_en)
923 # here is where we create the Write Broadcast Bus. simple, eh?
924 comb
+= wport
.i_data
.eq(ortreereduce_sig(wsigs
))
926 # for unary-addressed
927 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
929 # for binary-addressed
930 comb
+= wport
.addr
.eq(ortreereduce_sig(addrs
))
931 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
933 if not self
.make_hazard_vecs
:
936 # return these here rather than set wvclr/wvset directly,
937 # because there may be more than one write-port to a given
938 # regfile. example: XER has a write-port for SO, CA, and OV
939 # and the *last one added* of those would overwrite the other
940 # two. solution: have connect_wrports collate all the
941 # or-tree-reduced bitvector set/clear requests and drop them
942 # in as a single "thing". this can only be done because the
943 # set/get is an unary bitvector.
944 print ("make write-vecs", regfile
, regname
, wvset
, wvclr
)
945 return (ortreereduce_sig(wvclren
), # clear (regfile write)
946 ortreereduce_sig(wvseten
)) # set (issue time)
948 def connect_wrports(self
, m
, fu_bitdict
, fu_selected
):
949 """connect write ports
951 orders the write regspecs into a dict-of-dicts, by regfile,
952 by regport name, then connects all FUs that want that regport
953 by way of a PriorityPicker.
955 note that the write-port wen, write-port data, and go_wr_i all need to
956 be on the exact same clock cycle. as there is a combinatorial loop bug
957 at the moment, these all use sync.
959 comb
, sync
= m
.d
.comb
, m
.d
.sync
962 # dictionary of lists of regfile write ports
963 byregfiles_wr
, byregfiles_wrspec
= self
.get_byregfiles(False)
965 # same for write ports.
966 # BLECH! complex code-duplication! BLECH!
968 wvclrers
= defaultdict(list)
969 wvseters
= defaultdict(list)
970 for regfile
, spec
in byregfiles_wr
.items():
971 fuspecs
= byregfiles_wrspec
[regfile
]
972 wrpickers
[regfile
] = {}
974 if self
.regreduce_en
:
975 # argh, more port-merging
977 fuspecs
['o'] = [fuspecs
.pop('o')]
978 fuspecs
['o'].append(fuspecs
.pop('o1'))
979 if regfile
== 'FAST':
980 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
981 if 'fast2' in fuspecs
:
982 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
983 if 'fast3' in fuspecs
:
984 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
986 # collate these and record them by regfile because there
987 # are sometimes more write-ports per regfile
988 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
989 wvclren
, wvseten
= self
.connect_wrport(m
,
990 fu_bitdict
, fu_selected
,
992 regfile
, regname
, fspec
)
993 wvclrers
[regfile
.lower()].append(wvclren
)
994 wvseters
[regfile
.lower()].append(wvseten
)
996 if not self
.make_hazard_vecs
:
999 # for write-vectors: reduce the clr-ers and set-ers down to
1000 # a single set of bits. otherwise if there are two write
1001 # ports (on some regfiles), the last one doing comb += on
1002 # the reg.wv[regfile] instance "wins" (and all others are ignored,
1003 # whoops). if there was only one write-port per wv regfile this would
1005 for regfile
in wvclrers
.keys():
1006 wv
= regs
.wv
[regfile
]
1007 wvset
= wv
.s
# write-vec bit-level hazard ctrl
1008 wvclr
= wv
.r
# write-vec bit-level hazard ctrl
1009 wvclren
= wvclrers
[regfile
]
1010 wvseten
= wvseters
[regfile
]
1011 comb
+= wvclr
.eq(ortreereduce_sig(wvclren
)) # clear (regfile write)
1012 comb
+= wvset
.eq(ortreereduce_sig(wvseten
)) # set (issue time)
1014 def get_byregfiles(self
, readmode
):
1016 mode
= "read" if readmode
else "write"
1019 e
= self
.ireg
.e
# decoded instruction to execute
1021 # dictionary of dictionaries of lists/tuples of regfile ports.
1022 # first key: regfile. second key: regfile port name
1023 byregfiles
= defaultdict(lambda: defaultdict(list))
1024 byregfiles_spec
= defaultdict(dict)
1026 for (funame
, fu
) in fus
.items():
1027 # create in each FU a receptacle for the read/write register
1028 # hazard numbers. to be latched in connect_rd/write_ports
1029 # XXX better that this is moved into the actual FUs, but
1030 # the issue there is that this function is actually better
1031 # suited at the moment
1033 fu
.rd_latches
= {} # read reg number latches
1034 fu
.rf_latches
= {} # read flag latches
1038 print("%s ports for %s" % (mode
, funame
))
1039 for idx
in range(fu
.n_src
if readmode
else fu
.n_dst
):
1040 # construct regfile specs: read uses inspec, write outspec
1042 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
1044 (regfile
, regname
, wid
) = fu
.get_out_spec(idx
)
1045 print(" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
1047 # the PowerDecoder2 (main one, not the satellites) contains
1048 # the decoded regfile numbers. obtain these now
1050 okflag
, regport
= regspec_decode_read(e
, regfile
, regname
)
1052 okflag
, regport
= regspec_decode_write(e
, regfile
, regname
)
1054 # construct the dictionary of regspec information by regfile
1055 if regname
not in byregfiles_spec
[regfile
]:
1056 byregfiles_spec
[regfile
][regname
] = \
1057 ByRegSpec(okflag
, regport
, wid
, [])
1058 # here we start to create "lanes"
1059 fuspec
= FUSpec(funame
, fu
, idx
)
1060 byregfiles
[regfile
][idx
].append(fuspec
)
1061 byregfiles_spec
[regfile
][regname
].specs
.append(fuspec
)
1063 # ok just print that all out, for convenience
1064 for regfile
, spec
in byregfiles
.items():
1065 print("regfile %s ports:" % mode
, regfile
)
1066 fuspecs
= byregfiles_spec
[regfile
]
1067 for regname
, fspec
in fuspecs
.items():
1068 [okflag
, regport
, wid
, fuspecs
] = fspec
1069 print(" rf %s port %s lane: %s" % (mode
, regfile
, regname
))
1070 print(" %s" % regname
, wid
, okflag
, regport
)
1071 for (funame
, fu
, idx
) in fuspecs
:
1072 fusig
= fu
.src_i
[idx
] if readmode
else fu
.dest
[idx
]
1073 print(" ", funame
, fu
.__class
__.__name
__, idx
, fusig
)
1076 return byregfiles
, byregfiles_spec
1079 yield from self
.fus
.ports()
1080 yield from self
.i
.e
.ports()
1081 yield from self
.l0
.ports()
1088 if __name__
== '__main__':
1089 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
1095 dut
= NonProductionCore(pspec
)
1096 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
1097 with
open("test_core.il", "w") as f
: