src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal, ResetSignal, Cat, Mux
  23 from nmigen.cli import rtlil
  24
  25 from openpower.decoder.power_decoder2 import PowerDecodeSubset
  26 from openpower.decoder.power_regspec_map import regspec_decode_read
  27 from openpower.decoder.power_regspec_map import regspec_decode_write
  28 from openpower.sv.svp64 import SVP64Rec
  29
  30 from nmutil.picker import PriorityPicker
  31 from nmutil.util import treereduce
  32 from nmutil.singlepipe import ControlBase
  33
  34 from soc.fu.compunits.compunits import AllFunctionUnits
  35 from soc.regfile.regfiles import RegFiles
  36 from openpower.decoder.decode2execute1 import Decode2ToExecute1Type
  37 from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
  38 from openpower.decoder.power_decoder2 import get_rdflags
  39 from openpower.decoder.decode2execute1 import Data
  40 from soc.experiment.l0_cache import TstL0CacheBuffer  # test only
  41 from soc.config.test.test_loadstore import TestMemPspec
  42 from openpower.decoder.power_enums import MicrOp
  43 from soc.config.state import CoreState
  44
  45 import operator
  46
  47 from nmutil.util import rising_edge
  48
  49
  50 # helper function for reducing a list of signals down to a parallel
  51 # ORed single signal.
  52 def ortreereduce(tree, attr="o_data"):
  53     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  54
  55
  56 def ortreereduce_sig(tree):
  57     return treereduce(tree, operator.or_, lambda x: x)
  58
  59
  60 # helper function to place full regs declarations first
  61 def sort_fuspecs(fuspecs):
  62     res = []
  63     for (regname, fspec) in fuspecs.items():
  64         if regname.startswith("full"):
  65             res.append((regname, fspec))
  66     for (regname, fspec) in fuspecs.items():
  67         if not regname.startswith("full"):
  68             res.append((regname, fspec))
  69     return res  # enumerate(res)
  70
  71
  72 class CoreInput:
  73     """CoreInput: this is the input specification for Signals coming into core.
  74
  75     * state.  this contains PC, MSR, and SVSTATE. this is crucial information.
  76       (TODO: bigendian_i should really be read from the relevant MSR bit)
  77
  78     * the previously-decoded instruction goes into the Decode2Execute1Type
  79       data structure. no need for Core to re-decode that.  however note
  80       that *satellite* decoders *are* part of Core.
  81
  82     * the raw instruction. this is used by satellite decoders internal to
  83       Core, to provide Function-Unit-specific information.  really, they
  84       should be part of the actual ALU itself (in order to reduce wires),
  85       but hey.
  86
  87     * other stuff is related to SVP64.  the 24-bit SV REMAP field containing
  88       Vector context, etc.
  89     """
  90     def __init__(self, pspec, svp64_en, regreduce_en):
  91         self.pspec = pspec
  92         self.svp64_en = svp64_en
  93         self.e = Decode2ToExecute1Type("core", opkls=IssuerDecode2ToOperand,
  94                                 regreduce_en=regreduce_en)
  95
  96         # SVP64 RA_OR_ZERO needs to know if the relevant EXTRA2/3 field is zero
  97         self.sv_a_nz = Signal()
  98
  99         # state and raw instruction (and SVP64 ReMap fields)
 100         self.state = CoreState("core")
 101         self.raw_insn_i = Signal(32) # raw instruction
 102         self.bigendian_i = Signal() # bigendian - TODO, set by MSR.BE
 103         if svp64_en:
 104             self.sv_rm = SVP64Rec(name="core_svp64_rm") # SVP64 RM field
 105             self.is_svp64_mode = Signal() # set if SVP64 mode is enabled
 106             self.use_svp64_ldst_dec = Signal() # use alternative LDST decoder
 107             self.sv_pred_sm = Signal() # TODO: SIMD width
 108             self.sv_pred_dm = Signal() # TODO: SIMD width
 109
 110     def eq(self, i):
 111         self.e.eq(i.e)
 112         self.sv_a_nz.eq(i.sv_a_nz)
 113         self.state.eq(i.state)
 114         self.raw_insn_i.eq(i.raw_insn_i)
 115         self.bigendian_i.eq(i.bigendian_i)
 116         if not self.svp64_en:
 117             return
 118         self.sv_rm.eq(i.sv_rm)
 119         self.is_svp64_mode.eq(i.is_svp64_mode)
 120         self.use_svp64_ldst_dec.eq(i.use_svp64_ldst_dec)
 121         self.sv_pred_sm.eq(i.sv_pred_sm)
 122         self.sv_pred_dm.eq(i.sv_pred_dm)
 123
 124
 125 class CoreOutput:
 126     def __init__(self):
 127         # start/stop and terminated signalling
 128         self.core_terminate_o = Signal(reset=0)  # indicates stopped
 129         self.exc_happened = Signal()             # exception happened
 130
 131     def eq(self, i):
 132         self.core_terminate_o.eq(i.core_terminate_o)
 133         self.exc_happened.eq(i.exc_happened)
 134
 135
 136 # derive from ControlBase rather than have a separate Stage instance,
 137 # this is simpler to do
 138 class NonProductionCore(ControlBase):
 139     def __init__(self, pspec):
 140         self.pspec = pspec
 141
 142         # test is SVP64 is to be enabled
 143         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
 144
 145         # test to see if regfile ports should be reduced
 146         self.regreduce_en = (hasattr(pspec, "regreduce") and
 147                              (pspec.regreduce == True))
 148
 149         super().__init__(stage=self)
 150
 151         # single LD/ST funnel for memory access
 152         self.l0 = l0 = TstL0CacheBuffer(pspec, n_units=1)
 153         pi = l0.l0.dports[0]
 154
 155         # function units (only one each)
 156         # only include mmu if enabled in pspec
 157         self.fus = AllFunctionUnits(pspec, pilist=[pi])
 158
 159         # link LoadStore1 into MMU
 160         mmu = self.fus.get_fu('mmu0')
 161         print ("core pspec", pspec.ldst_ifacetype)
 162         print ("core mmu", mmu)
 163         print ("core lsmem.lsi", l0.cmpi.lsmem.lsi)
 164         if mmu is not None:
 165             mmu.alu.set_ldst_interface(l0.cmpi.lsmem.lsi)
 166
 167         # register files (yes plural)
 168         self.regs = RegFiles(pspec)
 169
 170         # set up input and output: unusual requirement to set data directly
 171         # (due to the way that the core is set up in a different domain,
 172         # see TestIssuer.setup_peripherals
 173         self.i, self.o = self.new_specs(None)
 174         self.i, self.o = self.p.i_data, self.n.o_data
 175
 176         # create per-FU instruction decoders (subsetted)
 177         self.decoders = {}
 178         self.des = {}
 179
 180         for funame, fu in self.fus.fus.items():
 181             f_name = fu.fnunit.name
 182             fnunit = fu.fnunit.value
 183             opkls = fu.opsubsetkls
 184             if f_name == 'TRAP':
 185                 # TRAP decoder is the *main* decoder
 186                 self.trapunit = funame
 187                 continue
 188             self.decoders[funame] = PowerDecodeSubset(None, opkls, f_name,
 189                                                       final=True,
 190                                                       state=self.i.state,
 191                                             svp64_en=self.svp64_en,
 192                                             regreduce_en=self.regreduce_en)
 193             self.des[funame] = self.decoders[funame].do
 194
 195         if "mmu0" in self.decoders:
 196             self.decoders["mmu0"].mmu0_spr_dec = self.decoders["spr0"]
 197
 198     def setup(self, m, i):
 199         pass
 200
 201     def ispec(self):
 202         return CoreInput(self.pspec, self.svp64_en, self.regreduce_en)
 203
 204     def ospec(self):
 205         return CoreOutput()
 206
 207     def elaborate(self, platform):
 208         m = super().elaborate(platform)
 209
 210         # for testing purposes, to cut down on build time in coriolis2
 211         if hasattr(self.pspec, "nocore") and self.pspec.nocore == True:
 212             x = Signal() # dummy signal
 213             m.d.sync += x.eq(~x)
 214             return m
 215         comb = m.d.comb
 216
 217         m.submodules.fus = self.fus
 218         m.submodules.l0 = l0 = self.l0
 219         self.regs.elaborate_into(m, platform)
 220         regs = self.regs
 221         fus = self.fus.fus
 222
 223         # connect decoders
 224         for k, v in self.decoders.items():
 225             # connect each satellite decoder and give it the instruction.
 226             # as subset decoders this massively reduces wire fanout given
 227             # the large number of ALUs
 228             setattr(m.submodules, "dec_%s" % v.fn_name, v)
 229             comb += v.dec.raw_opcode_in.eq(self.i.raw_insn_i)
 230             comb += v.dec.bigendian.eq(self.i.bigendian_i)
 231             # sigh due to SVP64 RA_OR_ZERO detection connect these too
 232             comb += v.sv_a_nz.eq(self.i.sv_a_nz)
 233             if self.svp64_en:
 234                 comb += v.pred_sm.eq(self.i.sv_pred_sm)
 235                 comb += v.pred_dm.eq(self.i.sv_pred_dm)
 236                 if k != self.trapunit:
 237                     comb += v.sv_rm.eq(self.i.sv_rm) # pass through SVP64 ReMap
 238                     comb += v.is_svp64_mode.eq(self.i.is_svp64_mode)
 239                     # only the LDST PowerDecodeSubset *actually* needs to
 240                     # know to use the alternative decoder.  this is all
 241                     # a terrible hack
 242                     if k.lower().startswith("ldst"):
 243                         comb += v.use_svp64_ldst_dec.eq(
 244                                         self.i.use_svp64_ldst_dec)
 245
 246         # ssh, cheat: trap uses the main decoder because of the rewriting
 247         self.des[self.trapunit] = self.i.e.do
 248
 249         # connect up Function Units, then read/write ports
 250         fu_bitdict = self.connect_instruction(m)
 251         self.connect_rdports(m, fu_bitdict)
 252         self.connect_wrports(m, fu_bitdict)
 253
 254         # note if an exception happened.  in a pipelined or OoO design
 255         # this needs to be accompanied by "shadowing" (or stalling)
 256         el = []
 257         for exc in self.fus.excs.values():
 258             el.append(exc.happened)
 259         if len(el) > 0: # at least one exception
 260             comb += self.o.exc_happened.eq(Cat(*el).bool())
 261
 262         return m
 263
 264     def connect_instruction(self, m):
 265         """connect_instruction
 266
 267         uses decoded (from PowerOp) function unit information from CSV files
 268         to ascertain which Function Unit should deal with the current
 269         instruction.
 270
 271         some (such as OP_ATTN, OP_NOP) are dealt with here, including
 272         ignoring it and halting the processor.  OP_NOP is a bit annoying
 273         because the issuer expects busy flag still to be raised then lowered.
 274         (this requires a fake counter to be set).
 275         """
 276         comb, sync = m.d.comb, m.d.sync
 277         fus = self.fus.fus
 278
 279         # indicate if core is busy
 280         busy_o = Signal(name="corebusy_o", reset_less=True)
 281
 282         # enable-signals for each FU, get one bit for each FU (by name)
 283         fu_enable = Signal(len(fus), reset_less=True)
 284         fu_bitdict = {}
 285         for i, funame in enumerate(fus.keys()):
 286             fu_bitdict[funame] = fu_enable[i]
 287
 288         # enable the required Function Unit based on the opcode decode
 289         # note: this *only* works correctly for simple core when one and
 290         # *only* one FU is allocated per instruction.  what is actually
 291         # required is one PriorityPicker per group of matching fnunits,
 292         # and for only one actual FU to be "picked".  this basically means
 293         # when ReservationStations are enabled it will be possible to
 294         # monitor multiple outstanding processing properly.
 295         for funame, fu in fus.items():
 296             fnunit = fu.fnunit.value
 297             enable = Signal(name="en_%s" % funame, reset_less=True)
 298             comb += enable.eq((self.i.e.do.fn_unit & fnunit).bool())
 299             comb += fu_bitdict[funame].eq(enable)
 300
 301         # sigh - need a NOP counter
 302         counter = Signal(2)
 303         with m.If(counter != 0):
 304             sync += counter.eq(counter - 1)
 305             comb += busy_o.eq(1)
 306
 307         with m.If(self.p.i_valid): # run only when valid
 308             with m.Switch(self.i.e.do.insn_type):
 309                 # check for ATTN: halt if true
 310                 with m.Case(MicrOp.OP_ATTN):
 311                     m.d.sync += self.o.core_terminate_o.eq(1)
 312
 313                 # fake NOP - this isn't really used (Issuer detects NOP)
 314                 with m.Case(MicrOp.OP_NOP):
 315                     sync += counter.eq(2)
 316                     comb += busy_o.eq(1)
 317
 318                 with m.Default():
 319                     # connect up instructions.  only one enabled at a time
 320                     for funame, fu in fus.items():
 321                         do = self.des[funame]
 322                         enable = fu_bitdict[funame]
 323
 324                         # run this FunctionUnit if enabled
 325                         # route op, issue, busy, read flags and mask to FU
 326                         with m.If(enable):
 327                             # operand comes from the *local*  decoder
 328                             comb += fu.oper_i.eq_from(do)
 329                             comb += fu.issue_i.eq(1) # issue when input valid
 330                             comb += busy_o.eq(fu.busy_o)
 331                             # rdmask, which is for registers, needs to come
 332                             # from the *main* decoder
 333                             rdmask = get_rdflags(self.i.e, fu)
 334                             comb += fu.rdmaskn.eq(~rdmask)
 335
 336         # if instruction is busy, set busy output for core. also
 337         # continue to hold each fu rdmask
 338         for funame, fu in fus.items():
 339             with m.If(fu.busy_o):
 340                 comb += busy_o.eq(fu.busy_o)
 341                 # rdmask, which is for registers, needs to come
 342                 # from the *main* decoder
 343                 rdmask = get_rdflags(self.i.e, fu)
 344                 comb += fu.rdmaskn.eq(~rdmask)
 345
 346         # set ready/valid signalling.  if busy, means refuse incoming issue
 347         # XXX note: for an in-order core this is far too simple.  busy must
 348         # be gated with the *availability* of the incoming (requested)
 349         # instruction, where Core must be prepared to store-and-hold
 350         # an instruction if no FU is available.
 351         comb += self.p.o_ready.eq(~busy_o)
 352
 353         return fu_bitdict
 354
 355     def connect_rdport(self, m, fu_bitdict, rdpickers, regfile, regname, fspec):
 356         comb, sync = m.d.comb, m.d.sync
 357         fus = self.fus.fus
 358         regs = self.regs
 359
 360         rpidx = regname
 361
 362         # select the required read port.  these are pre-defined sizes
 363         rfile = regs.rf[regfile.lower()]
 364         rport = rfile.r_ports[rpidx]
 365         print("read regfile", rpidx, regfile, regs.rf.keys(),
 366                               rfile, rfile.unary)
 367
 368         fspecs = fspec
 369         if not isinstance(fspecs, list):
 370             fspecs = [fspecs]
 371
 372         rdflags = []
 373         pplen = 0
 374         reads = []
 375         ppoffs = []
 376         for i, fspec in enumerate(fspecs):
 377             # get the regfile specs for this regfile port
 378             (rf, read, write, wid, fuspec) = fspec
 379             print ("fpsec", i, fspec, len(fuspec))
 380             ppoffs.append(pplen) # record offset for picker
 381             pplen += len(fuspec)
 382             name = "rdflag_%s_%s_%d" % (regfile, regname, i)
 383             rdflag = Signal(name=name, reset_less=True)
 384             comb += rdflag.eq(rf)
 385             rdflags.append(rdflag)
 386             reads.append(read)
 387
 388         print ("pplen", pplen)
 389
 390         # create a priority picker to manage this port
 391         rdpickers[regfile][rpidx] = rdpick = PriorityPicker(pplen)
 392         setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
 393
 394         rens = []
 395         addrs = []
 396         for i, fspec in enumerate(fspecs):
 397             (rf, read, write, wid, fuspec) = fspec
 398             # connect up the FU req/go signals, and the reg-read to the FU
 399             # and create a Read Broadcast Bus
 400             for pi, (funame, fu, idx) in enumerate(fuspec):
 401                 pi += ppoffs[i]
 402
 403                 # connect request-read to picker input, and output to go-rd
 404                 fu_active = fu_bitdict[funame]
 405                 name = "%s_%s_%s_%i" % (regfile, rpidx, funame, pi)
 406                 addr_en = Signal.like(reads[i], name="addr_en_"+name)
 407                 pick = Signal(name="pick_"+name)     # picker input
 408                 rp = Signal(name="rp_"+name)         # picker output
 409                 delay_pick = Signal(name="dp_"+name) # read-enable "underway"
 410
 411                 # exclude any currently-enabled read-request (mask out active)
 412                 comb += pick.eq(fu.rd_rel_o[idx] & fu_active & rdflags[i] &
 413                                 ~delay_pick)
 414                 comb += rdpick.i[pi].eq(pick)
 415                 comb += fu.go_rd_i[idx].eq(delay_pick) # pass in *delayed* pick
 416
 417                 # if picked, select read-port "reg select" number to port
 418                 comb += rp.eq(rdpick.o[pi] & rdpick.en_o)
 419                 sync += delay_pick.eq(rp) # delayed "pick"
 420                 comb += addr_en.eq(Mux(rp, reads[i], 0))
 421
 422                 # the read-enable happens combinatorially (see mux-bus below)
 423                 # but it results in the data coming out on a one-cycle delay.
 424                 if rfile.unary:
 425                     rens.append(addr_en)
 426                 else:
 427                     addrs.append(addr_en)
 428                     rens.append(rp)
 429
 430                 # use the *delayed* pick signal to put requested data onto bus
 431                 with m.If(delay_pick):
 432                     # connect regfile port to input, creating fan-out Bus
 433                     src = fu.src_i[idx]
 434                     print("reg connect widths",
 435                           regfile, regname, pi, funame,
 436                           src.shape(), rport.o_data.shape())
 437                     # all FUs connect to same port
 438                     comb += src.eq(rport.o_data)
 439
 440         # or-reduce the muxed read signals
 441         if rfile.unary:
 442             # for unary-addressed
 443             comb += rport.ren.eq(ortreereduce_sig(rens))
 444         else:
 445             # for binary-addressed
 446             comb += rport.addr.eq(ortreereduce_sig(addrs))
 447             comb += rport.ren.eq(Cat(*rens).bool())
 448             print ("binary", regfile, rpidx, rport, rport.ren, rens, addrs)
 449
 450     def connect_rdports(self, m, fu_bitdict):
 451         """connect read ports
 452
 453         orders the read regspecs into a dict-of-dicts, by regfile, by
 454         regport name, then connects all FUs that want that regport by
 455         way of a PriorityPicker.
 456         """
 457         comb, sync = m.d.comb, m.d.sync
 458         fus = self.fus.fus
 459         regs = self.regs
 460
 461         # dictionary of lists of regfile read ports
 462         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 463
 464         # okaay, now we need a PriorityPicker per regfile per regfile port
 465         # loootta pickers... peter piper picked a pack of pickled peppers...
 466         rdpickers = {}
 467         for regfile, spec in byregfiles_rd.items():
 468             fuspecs = byregfiles_rdspec[regfile]
 469             rdpickers[regfile] = {}
 470
 471             # argh.  an experiment to merge RA and RB in the INT regfile
 472             # (we have too many read/write ports)
 473             if self.regreduce_en:
 474                 if regfile == 'INT':
 475                     fuspecs['rabc'] = [fuspecs.pop('rb')]
 476                     fuspecs['rabc'].append(fuspecs.pop('rc'))
 477                     fuspecs['rabc'].append(fuspecs.pop('ra'))
 478                 if regfile == 'FAST':
 479                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
 480                     if 'fast2' in fuspecs:
 481                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
 482                     if 'fast3' in fuspecs:
 483                         fuspecs['fast1'].append(fuspecs.pop('fast3'))
 484
 485             # for each named regfile port, connect up all FUs to that port
 486             for (regname, fspec) in sort_fuspecs(fuspecs):
 487                 print("connect rd", regname, fspec)
 488                 self.connect_rdport(m, fu_bitdict, rdpickers, regfile,
 489                                        regname, fspec)
 490
 491     def connect_wrport(self, m, fu_bitdict, wrpickers, regfile, regname, fspec):
 492         comb, sync = m.d.comb, m.d.sync
 493         fus = self.fus.fus
 494         regs = self.regs
 495
 496         print("connect wr", regname, fspec)
 497         rpidx = regname
 498
 499         # select the required write port.  these are pre-defined sizes
 500         print(regfile, regs.rf.keys())
 501         rfile = regs.rf[regfile.lower()]
 502         wport = rfile.w_ports[rpidx]
 503
 504         fspecs = fspec
 505         if not isinstance(fspecs, list):
 506             fspecs = [fspecs]
 507
 508         pplen = 0
 509         writes = []
 510         ppoffs = []
 511         for i, fspec in enumerate(fspecs):
 512             # get the regfile specs for this regfile port
 513             (rf, read, write, wid, fuspec) = fspec
 514             print ("fpsec", i, fspec, len(fuspec))
 515             ppoffs.append(pplen) # record offset for picker
 516             pplen += len(fuspec)
 517
 518         # create a priority picker to manage this port
 519         wrpickers[regfile][rpidx] = wrpick = PriorityPicker(pplen)
 520         setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
 521
 522         wsigs = []
 523         wens = []
 524         addrs = []
 525         for i, fspec in enumerate(fspecs):
 526             # connect up the FU req/go signals and the reg-read to the FU
 527             # these are arbitrated by Data.ok signals
 528             (rf, read, write, wid, fuspec) = fspec
 529             for pi, (funame, fu, idx) in enumerate(fuspec):
 530                 pi += ppoffs[i]
 531
 532                 # write-request comes from dest.ok
 533                 dest = fu.get_out(idx)
 534                 fu_dest_latch = fu.get_fu_out(idx)  # latched output
 535                 name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 536                 wrflag = Signal(name=name, reset_less=True)
 537                 comb += wrflag.eq(dest.ok & fu.busy_o)
 538
 539                 # connect request-write to picker input, and output to go-wr
 540                 fu_active = fu_bitdict[funame]
 541                 pick = fu.wr.rel_o[idx] & fu_active  # & wrflag
 542                 comb += wrpick.i[pi].eq(pick)
 543                 # create a single-pulse go write from the picker output
 544                 wr_pick = Signal(name="wpick_%s_%s_%d" % (funame, regname, idx))
 545                 comb += wr_pick.eq(wrpick.o[pi] & wrpick.en_o)
 546                 comb += fu.go_wr_i[idx].eq(rising_edge(m, wr_pick))
 547
 548                 # connect the regspec write "reg select" number to this port
 549                 # only if one FU actually requests (and is granted) the port
 550                 # will the write-enable be activated
 551                 addr_en = Signal.like(write)
 552                 wp = Signal()
 553                 comb += wp.eq(wr_pick & wrpick.en_o)
 554                 comb += addr_en.eq(Mux(wp, write, 0))
 555                 if rfile.unary:
 556                     wens.append(addr_en)
 557                 else:
 558                     addrs.append(addr_en)
 559                     wens.append(wp)
 560
 561                 # connect regfile port to input
 562                 print("reg connect widths",
 563                       regfile, regname, pi, funame,
 564                       dest.shape(), wport.i_data.shape())
 565                 wsigs.append(fu_dest_latch)
 566
 567         # here is where we create the Write Broadcast Bus. simple, eh?
 568         comb += wport.i_data.eq(ortreereduce_sig(wsigs))
 569         if rfile.unary:
 570             # for unary-addressed
 571             comb += wport.wen.eq(ortreereduce_sig(wens))
 572         else:
 573             # for binary-addressed
 574             comb += wport.addr.eq(ortreereduce_sig(addrs))
 575             comb += wport.wen.eq(ortreereduce_sig(wens))
 576
 577     def connect_wrports(self, m, fu_bitdict):
 578         """connect write ports
 579
 580         orders the write regspecs into a dict-of-dicts, by regfile,
 581         by regport name, then connects all FUs that want that regport
 582         by way of a PriorityPicker.
 583
 584         note that the write-port wen, write-port data, and go_wr_i all need to
 585         be on the exact same clock cycle.  as there is a combinatorial loop bug
 586         at the moment, these all use sync.
 587         """
 588         comb, sync = m.d.comb, m.d.sync
 589         fus = self.fus.fus
 590         regs = self.regs
 591         # dictionary of lists of regfile write ports
 592         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 593
 594         # same for write ports.
 595         # BLECH!  complex code-duplication! BLECH!
 596         wrpickers = {}
 597         for regfile, spec in byregfiles_wr.items():
 598             fuspecs = byregfiles_wrspec[regfile]
 599             wrpickers[regfile] = {}
 600
 601             if self.regreduce_en:
 602                 # argh, more port-merging
 603                 if regfile == 'INT':
 604                     fuspecs['o'] = [fuspecs.pop('o')]
 605                     fuspecs['o'].append(fuspecs.pop('o1'))
 606                 if regfile == 'FAST':
 607                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
 608                     if 'fast2' in fuspecs:
 609                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
 610                     if 'fast3' in fuspecs:
 611                         fuspecs['fast1'].append(fuspecs.pop('fast3'))
 612
 613             for (regname, fspec) in sort_fuspecs(fuspecs):
 614                 self.connect_wrport(m, fu_bitdict, wrpickers,
 615                                         regfile, regname, fspec)
 616
 617     def get_byregfiles(self, readmode):
 618
 619         mode = "read" if readmode else "write"
 620         regs = self.regs
 621         fus = self.fus.fus
 622         e = self.i.e # decoded instruction to execute
 623
 624         # dictionary of lists of regfile ports
 625         byregfiles = {}
 626         byregfiles_spec = {}
 627         for (funame, fu) in fus.items():
 628             print("%s ports for %s" % (mode, funame))
 629             for idx in range(fu.n_src if readmode else fu.n_dst):
 630                 if readmode:
 631                     (regfile, regname, wid) = fu.get_in_spec(idx)
 632                 else:
 633                     (regfile, regname, wid) = fu.get_out_spec(idx)
 634                 print("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 635                 if readmode:
 636                     rdflag, read = regspec_decode_read(e, regfile, regname)
 637                     write = None
 638                 else:
 639                     rdflag, read = None, None
 640                     wrport, write = regspec_decode_write(e, regfile, regname)
 641                 if regfile not in byregfiles:
 642                     byregfiles[regfile] = {}
 643                     byregfiles_spec[regfile] = {}
 644                 if regname not in byregfiles_spec[regfile]:
 645                     byregfiles_spec[regfile][regname] = \
 646                         (rdflag, read, write, wid, [])
 647                 # here we start to create "lanes"
 648                 if idx not in byregfiles[regfile]:
 649                     byregfiles[regfile][idx] = []
 650                 fuspec = (funame, fu, idx)
 651                 byregfiles[regfile][idx].append(fuspec)
 652                 byregfiles_spec[regfile][regname][4].append(fuspec)
 653
 654         # ok just print that out, for convenience
 655         for regfile, spec in byregfiles.items():
 656             print("regfile %s ports:" % mode, regfile)
 657             fuspecs = byregfiles_spec[regfile]
 658             for regname, fspec in fuspecs.items():
 659                 [rdflag, read, write, wid, fuspec] = fspec
 660                 print("  rf %s port %s lane: %s" % (mode, regfile, regname))
 661                 print("  %s" % regname, wid, read, write, rdflag)
 662                 for (funame, fu, idx) in fuspec:
 663                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 664                     print("    ", funame, fu, idx, fusig)
 665                     print()
 666
 667         return byregfiles, byregfiles_spec
 668
 669     def __iter__(self):
 670         yield from self.fus.ports()
 671         yield from self.i.e.ports()
 672         yield from self.l0.ports()
 673         # TODO: regs
 674
 675     def ports(self):
 676         return list(self)
 677
 678
 679 if __name__ == '__main__':
 680     pspec = TestMemPspec(ldst_ifacetype='testpi',
 681                          imem_ifacetype='',
 682                          addr_wid=48,
 683                          mask_wid=8,
 684                          reg_wid=64)
 685     dut = NonProductionCore(pspec)
 686     vl = rtlil.convert(dut, ports=dut.ports())
 687     with open("test_core.il", "w") as f:
 688         f.write(vl)