3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from FastRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import Elaboratable
, Module
, Signal
19 from nmigen
.cli
import rtlil
21 from soc
.decoder
.decode2execute1
import Data
22 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
23 from soc
.regfile
.regfiles
import FastRegs
24 from soc
.simple
.core
import NonProductionCore
25 from soc
.config
.test
.test_loadstore
import TestMemPspec
26 from soc
.config
.ifetch
import ConfigFetchUnit
27 from soc
.decoder
.power_enums
import MicrOp
30 class TestIssuer(Elaboratable
):
31 """TestIssuer - reads instructions from TestMemory and issues them
33 efficiency and speed is not the main goal here: functional correctness is.
35 def __init__(self
, pspec
):
36 # main instruction core
37 self
.core
= core
= NonProductionCore(pspec
)
39 # Test Instruction memory
40 self
.imem
= ConfigFetchUnit(pspec
).fu
41 # one-row cache of instruction read
42 self
.iline
= Signal(64) # one instruction line
43 self
.iprev_adr
= Signal(64) # previous address: if different, do read
45 # instruction go/monitor
46 self
.go_insn_i
= Signal(reset_less
=True)
47 self
.pc_o
= Signal(64, reset_less
=True)
48 self
.pc_i
= Data(64, "pc") # set "ok" to indicate "please change me"
49 self
.busy_o
= core
.busy_o
50 self
.memerr_o
= Signal(reset_less
=True)
52 # FAST regfile read /write ports
53 self
.fast_rd1
= self
.core
.regs
.rf
['fast'].r_ports
['d_rd1']
54 self
.fast_wr1
= self
.core
.regs
.rf
['fast'].w_ports
['d_wr1']
55 # hack method of keeping an eye on whether branch/trap set the PC
56 self
.fast_nia
= self
.core
.regs
.rf
['fast'].w_ports
['nia']
57 self
.fast_nia
.wen
.name
= 'fast_nia_wen'
59 def elaborate(self
, platform
):
61 comb
, sync
= m
.d
.comb
, m
.d
.sync
63 m
.submodules
.core
= core
= self
.core
64 m
.submodules
.imem
= imem
= self
.imem
66 # temporary hack: says "go" immediately for both address gen and ST
68 ldst
= core
.fus
.fus
['ldst0']
69 m
.d
.comb
+= ldst
.ad
.go
.eq(ldst
.ad
.rel
) # link addr-go direct to rel
70 m
.d
.comb
+= ldst
.st
.go
.eq(ldst
.st
.rel
) # link store-go direct to rel
72 # PC and instruction from I-Memory
73 current_insn
= Signal(32) # current fetched instruction (note sync)
74 cur_pc
= Signal(64) # current PC (note it is reset/sync)
75 pc_changed
= Signal() # note write to PC
76 comb
+= self
.pc_o
.eq(cur_pc
)
79 # next instruction (+4 on current)
80 nia
= Signal(64, reset_less
=True)
81 comb
+= nia
.eq(cur_pc
+ 4)
84 core_busy_o
= core
.busy_o
# core is busy
85 core_ivalid_i
= core
.ivalid_i
# instruction is valid
86 core_issue_i
= core
.issue_i
# instruction is issued
87 core_be_i
= core
.bigendian_i
# bigendian mode
88 core_opcode_i
= core
.raw_opcode_i
# raw opcode
90 insn_type
= core
.pdecode2
.e
.do
.insn_type
92 # only run if not in halted state
93 with m
.If(~core
.core_terminated_o
):
95 # actually use a nmigen FSM for the first time (w00t)
96 # this FSM is perhaps unusual in that it detects conditions
97 # then "holds" information, combinatorially, for the core
98 # (as opposed to using sync - which would be on a clock's delay)
99 # this includes the actual opcode, valid flags and so on.
103 with m
.State("IDLE"):
104 sync
+= pc_changed
.eq(0)
105 with m
.If(self
.go_insn_i
):
106 # instruction allowed to go: start by reading the PC
107 pc
= Signal(64, reset_less
=True)
108 with m
.If(self
.pc_i
.ok
):
109 # incoming override (start from pc_i)
110 comb
+= pc
.eq(self
.pc_i
.data
)
112 # otherwise read FastRegs regfile for PC
113 comb
+= self
.fast_rd1
.ren
.eq(1<<FastRegs
.PC
)
114 comb
+= pc
.eq(self
.fast_rd1
.data_o
)
115 # capture the PC and also drop it into Insn Memory
116 # we have joined a pair of combinatorial memory
117 # lookups together. this is Generally Bad.
118 comb
+= self
.imem
.a_pc_i
.eq(pc
)
119 comb
+= self
.imem
.a_valid_i
.eq(1)
120 comb
+= self
.imem
.f_valid_i
.eq(1)
121 sync
+= cur_pc
.eq(pc
)
122 m
.next
= "INSN_READ" # move to "wait for bus" phase
124 # waiting for instruction bus (stays there until not busy)
125 with m
.State("INSN_READ"):
126 with m
.If(self
.imem
.f_busy_o
): # zzz...
127 # busy: stay in wait-read
128 comb
+= self
.imem
.a_valid_i
.eq(1)
129 comb
+= self
.imem
.f_valid_i
.eq(1)
131 # not busy: instruction fetched
132 insn
= self
.imem
.f_instr_o
.word_select(cur_pc
[2], 32)
133 comb
+= current_insn
.eq(insn
)
134 comb
+= core_ivalid_i
.eq(1) # instruction is valid
135 comb
+= core_issue_i
.eq(1) # and issued
136 comb
+= core_opcode_i
.eq(current_insn
) # actual opcode
137 sync
+= ilatch
.eq(current_insn
) # latch current insn
138 m
.next
= "INSN_ACTIVE" # move to "wait completion"
140 # instruction started: must wait till it finishes
141 with m
.State("INSN_ACTIVE"):
142 with m
.If(core
.core_terminated_o
):
143 m
.next
= "IDLE" # back to idle, immediately (OP_ATTN)
145 with m
.If(insn_type
!= MicrOp
.OP_NOP
):
146 comb
+= core_ivalid_i
.eq(1) # instruction is valid
147 comb
+= core_opcode_i
.eq(ilatch
) # actual opcode
148 with m
.If(self
.fast_nia
.wen
):
149 sync
+= pc_changed
.eq(1)
150 with m
.If(~core_busy_o
): # instruction done!
151 # ok here we are not reading the branch unit. TODO
152 # this just blithely overwrites whatever pipeline
154 with m
.If(~pc_changed
):
155 comb
+= self
.fast_wr1
.wen
.eq(1<<FastRegs
.PC
)
156 comb
+= self
.fast_wr1
.data_i
.eq(nia
)
157 m
.next
= "IDLE" # back to idle
162 yield from self
.pc_i
.ports()
166 yield from self
.core
.ports()
167 yield from self
.imem
.ports()
173 if __name__
== '__main__':
174 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
178 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
179 imem_ifacetype
='bare_wb',
184 dut
= TestIssuer(pspec
)
185 vl
= rtlil
.convert(dut
, ports
=dut
.ports(), name
="test_issuer")
186 with
open("test_issuer.il", "w") as f
: