src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # JTAG interface.  add this right at the start because if it's
  64         # added it *modifies* the pspec, by adding enable/disable signals
  65         # for parts of the rest of the core
  66         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  67         if self.jtag_en:
  68             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  69                       'pwm', 'sd0', 'sdr'}
  70             self.jtag = JTAG(get_pinspecs(subset=subset))
  71             # add signals to pspec to enable/disable icache and dcache
  72             # (or data and intstruction wishbone if icache/dcache not included)
  73             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  74             # TODO: do we actually care if these are not domain-synchronised?
  75             # honestly probably not.
  76             pspec.wb_icache_en = self.jtag.wb_icache_en
  77             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  78             self.wb_sram_en = self.jtag.wb_sram_en
  79         else:
  80             self.wb_sram_en = Const(1)
  81
  82         # add 4k sram blocks?
  83         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  84                          pspec.sram4x4kblock == True)
  85         if self.sram4x4k:
  86             self.sram4k = []
  87             for i in range(4):
  88                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
  89                                                     features={'err'}))
  90
  91         # add interrupt controller?
  92         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  93         if self.xics:
  94             self.xics_icp = XICS_ICP()
  95             self.xics_ics = XICS_ICS()
  96             self.int_level_i = self.xics_ics.int_level_i
  97
  98         # add GPIO peripheral?
  99         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
 100         if self.gpio:
 101             self.simple_gpio = SimpleGPIO()
 102             self.gpio_o = self.simple_gpio.gpio_o
 103
 104         # main instruction core25
 105         self.core = core = NonProductionCore(pspec)
 106
 107         # instruction decoder.  goes into Trap Record
 108         pdecode = create_pdecode()
 109         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 110         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 111                                      opkls=IssuerDecode2ToOperand)
 112         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 113
 114         # Test Instruction memory
 115         self.imem = ConfigFetchUnit(pspec).fu
 116         # one-row cache of instruction read
 117         self.iline = Signal(64) # one instruction line
 118         self.iprev_adr = Signal(64) # previous address: if different, do read
 119
 120         # DMI interface
 121         self.dbg = CoreDebug()
 122
 123         # instruction go/monitor
 124         self.pc_o = Signal(64, reset_less=True)
 125         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 126         self.svstate_i = Data(32, "svstate_i") # ditto
 127         self.core_bigendian_i = Signal()
 128         self.busy_o = Signal(reset_less=True)
 129         self.memerr_o = Signal(reset_less=True)
 130
 131         # STATE regfile read /write ports for PC, MSR, SVSTATE
 132         staterf = self.core.regs.rf['state']
 133         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 134         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 135         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 136         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 137         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 138
 139         # DMI interface access
 140         intrf = self.core.regs.rf['int']
 141         crrf = self.core.regs.rf['cr']
 142         xerrf = self.core.regs.rf['xer']
 143         self.int_r = intrf.r_ports['dmi'] # INT read
 144         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 145         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 146
 147         # hack method of keeping an eye on whether branch/trap set the PC
 148         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 149         self.state_nia.wen.name = 'state_nia_wen'
 150
 151     def fetch_fsm(self, m, core, pc, svstate, nia,
 152                         fetch_pc_ready_o, fetch_pc_valid_i,
 153                         fetch_insn_valid_o, fetch_insn_ready_i):
 154         """fetch FSM
 155         this FSM performs fetch of raw instruction data, partial-decodes
 156         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 157         read a 2nd 32-bit quantity if that occurs.
 158         """
 159         comb = m.d.comb
 160         sync = m.d.sync
 161         pdecode2 = self.pdecode2
 162         svp64 = self.svp64
 163         cur_state = self.cur_state
 164         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 165
 166         msr_read = Signal(reset=1)
 167
 168         with m.FSM(name='fetch_fsm'):
 169
 170             # waiting (zzz)
 171             with m.State("IDLE"):
 172                 comb += fetch_pc_ready_o.eq(1)
 173                 with m.If(fetch_pc_valid_i):
 174                     # instruction allowed to go: start by reading the PC
 175                     # capture the PC and also drop it into Insn Memory
 176                     # we have joined a pair of combinatorial memory
 177                     # lookups together.  this is Generally Bad.
 178                     comb += self.imem.a_pc_i.eq(pc)
 179                     comb += self.imem.a_valid_i.eq(1)
 180                     comb += self.imem.f_valid_i.eq(1)
 181                     sync += cur_state.pc.eq(pc)
 182                     sync += cur_state.svstate.eq(svstate) # and svstate
 183
 184                     # initiate read of MSR. arrives one clock later
 185                     comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 186                     sync += msr_read.eq(0)
 187
 188                     m.next = "INSN_READ"  # move to "wait for bus" phase
 189
 190             # dummy pause to find out why simulation is not keeping up
 191             with m.State("INSN_READ"):
 192                 # one cycle later, msr/sv read arrives.  valid only once.
 193                 with m.If(~msr_read):
 194                     sync += msr_read.eq(1) # yeah don't read it again
 195                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 196                 with m.If(self.imem.f_busy_o): # zzz...
 197                     # busy: stay in wait-read
 198                     comb += self.imem.a_valid_i.eq(1)
 199                     comb += self.imem.f_valid_i.eq(1)
 200                 with m.Else():
 201                     # not busy: instruction fetched
 202                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 203                     # decode the SVP64 prefix, if any
 204                     comb += svp64.raw_opcode_in.eq(insn)
 205                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 206                     # pass the decoded prefix (if any) to PowerDecoder2
 207                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 208                     # calculate the address of the following instruction
 209                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 210                     sync += nia.eq(cur_state.pc + insn_size)
 211                     with m.If(~svp64.is_svp64_mode):
 212                         # with no prefix, store the instruction
 213                         # and hand it directly to the next FSM
 214                         sync += dec_opcode_i.eq(insn)
 215                         m.next = "INSN_READY"
 216                     with m.Else():
 217                         # fetch the rest of the instruction from memory
 218                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 219                         comb += self.imem.a_valid_i.eq(1)
 220                         comb += self.imem.f_valid_i.eq(1)
 221                         m.next = "INSN_READ2"
 222
 223             with m.State("INSN_READ2"):
 224                 with m.If(self.imem.f_busy_o):  # zzz...
 225                     # busy: stay in wait-read
 226                     comb += self.imem.a_valid_i.eq(1)
 227                     comb += self.imem.f_valid_i.eq(1)
 228                 with m.Else():
 229                     # not busy: instruction fetched
 230                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 231                     sync += dec_opcode_i.eq(insn)
 232                     m.next = "INSN_READY"
 233
 234             with m.State("INSN_READY"):
 235                 # hand over the instruction, to be decoded
 236                 comb += fetch_insn_valid_o.eq(1)
 237                 with m.If(fetch_insn_ready_i):
 238                     m.next = "IDLE"
 239
 240     def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
 241                   dbg, core_rst,
 242                   fetch_pc_ready_o, fetch_pc_valid_i,
 243                   fetch_insn_valid_o, fetch_insn_ready_i,
 244                   exec_insn_valid_i, exec_insn_ready_o,
 245                   exec_pc_valid_o, exec_pc_ready_i):
 246         """issue FSM
 247
 248         decode / issue FSM.  this interacts with the "fetch" FSM
 249         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 250         (outgoing). also interacts with the "execute" FSM
 251         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 252         (incoming).
 253         SVP64 RM prefixes have already been set up by the
 254         "fetch" phase, so execute is fairly straightforward.
 255         """
 256
 257         comb = m.d.comb
 258         sync = m.d.sync
 259         pdecode2 = self.pdecode2
 260         cur_state = self.cur_state
 261
 262         # temporaries
 263         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 264
 265         # for updating svstate (things like srcstep etc.)
 266         update_svstate = Signal() # set this (below) if updating
 267         new_svstate = SVSTATERec("new_svstate")
 268         comb += new_svstate.eq(cur_state.svstate)
 269
 270         with m.FSM(name="issue_fsm"):
 271
 272             # go fetch the instruction at the current PC
 273             # at this point, there is no instruction running, that
 274             # could inadvertently update the PC.
 275             with m.State("INSN_FETCH"):
 276                 # wait on "core stop" release, before next fetch
 277                 # need to do this here, in case we are in a VL==0 loop
 278                 with m.If(~dbg.core_stop_o & ~core_rst):
 279                     comb += fetch_pc_valid_i.eq(1)
 280                     with m.If(fetch_pc_ready_o):
 281                         m.next = "INSN_WAIT"
 282                 with m.Else():
 283                     comb += core.core_stopped_i.eq(1)
 284                     comb += dbg.core_stopped_i.eq(1)
 285                     # while stopped, allow updating the PC and SVSTATE
 286                     with m.If(self.pc_i.ok):
 287                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 288                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 289                         sync += pc_changed.eq(1)
 290                     with m.If(self.svstate_i.ok):
 291                         comb += new_svstate.eq(self.svstate_i.data)
 292                         comb += update_svstate.eq(1)
 293                         sync += sv_changed.eq(1)
 294
 295             # decode the instruction when it arrives
 296             with m.State("INSN_WAIT"):
 297                 comb += fetch_insn_ready_i.eq(1)
 298                 with m.If(fetch_insn_valid_o):
 299                     # decode the instruction
 300                     sync += core.e.eq(pdecode2.e)
 301                     sync += core.state.eq(cur_state)
 302                     sync += core.raw_insn_i.eq(dec_opcode_i)
 303                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 304                     # loop into INSN_FETCH if it's a vector instruction
 305                     # and VL == 0.  this because VL==0 is a for-loop
 306                     # from 0 to 0 i.e. always, always a NOP.
 307                     cur_vl = cur_state.svstate.vl
 308                     with m.If(~pdecode2.no_out_vec & (cur_vl == 0)):
 309                         # update the PC before fetching the next instruction
 310                         # since we are in a VL==0 loop, no instruction was
 311                         # executed that we could be overwriting
 312                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 313                         comb += self.state_w_pc.data_i.eq(nia)
 314                         m.next = "INSN_FETCH"
 315                     with m.Else():
 316                         m.next = "INSN_EXECUTE"  # move to "execute"
 317
 318             with m.State("INSN_EXECUTE"):
 319                 comb += exec_insn_valid_i.eq(1)
 320                 with m.If(exec_insn_ready_o):
 321                     m.next = "EXECUTE_WAIT"
 322
 323             with m.State("EXECUTE_WAIT"):
 324                 # wait on "core stop" release, at instruction end
 325                 # need to do this here, in case we are in a VL>1 loop
 326                 with m.If(~dbg.core_stop_o & ~core_rst):
 327                     comb += exec_pc_ready_i.eq(1)
 328                     with m.If(exec_pc_valid_o):
 329                         # precalculate srcstep+1
 330                         next_srcstep = Signal.like(cur_state.svstate.srcstep)
 331                         comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
 332                         # was this the last loop iteration?
 333                         is_last = Signal()
 334                         cur_vl = cur_state.svstate.vl
 335                         comb += is_last.eq(next_srcstep == cur_vl)
 336
 337                         # if either PC or SVSTATE were changed by the previous
 338                         # instruction, go directly back to Fetch, without
 339                         # updating either PC or SVSTATE
 340                         with m.If(pc_changed | sv_changed):
 341                             m.next = "INSN_FETCH"
 342
 343                         # also return to Fetch, when no output was a vector
 344                         # (regardless of SRCSTEP and VL), or when the last
 345                         # instruction was really the last one of the VL loop
 346                         with m.Elif(pdecode2.no_out_vec | is_last):
 347                             # before going back to fetch, update the PC state
 348                             # register with the NIA.
 349                             # ok here we are not reading the branch unit.
 350                             # TODO: this just blithely overwrites whatever
 351                             #       pipeline updated the PC
 352                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 353                             comb += self.state_w_pc.data_i.eq(nia)
 354                             # reset SRCSTEP before returning to Fetch
 355                             with m.If(~pdecode2.no_out_vec):
 356                                 comb += new_svstate.srcstep.eq(0)
 357                                 comb += update_svstate.eq(1)
 358                             m.next = "INSN_FETCH"
 359
 360                         # returning to Execute? then, first update SRCSTEP
 361                         with m.Else():
 362                             comb += new_svstate.srcstep.eq(next_srcstep)
 363                             comb += update_svstate.eq(1)
 364                             m.next = "DECODE_SV"
 365
 366                 with m.Else():
 367                     comb += core.core_stopped_i.eq(1)
 368                     comb += dbg.core_stopped_i.eq(1)
 369                     # while stopped, allow updating the PC and SVSTATE
 370                     with m.If(self.pc_i.ok):
 371                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 372                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 373                         sync += pc_changed.eq(1)
 374                     with m.If(self.svstate_i.ok):
 375                         comb += new_svstate.eq(self.svstate_i.data)
 376                         comb += update_svstate.eq(1)
 377                         sync += sv_changed.eq(1)
 378
 379             # need to decode the instruction again, after updating SRCSTEP
 380             # in the previous state.
 381             # mostly a copy of INSN_WAIT, but without the actual wait
 382             with m.State("DECODE_SV"):
 383                 # decode the instruction
 384                 sync += core.e.eq(pdecode2.e)
 385                 sync += core.state.eq(cur_state)
 386                 sync += core.bigendian_i.eq(self.core_bigendian_i)
 387                 m.next = "INSN_EXECUTE"  # move to "execute"
 388
 389         # check if svstate needs updating: if so, write it to State Regfile
 390         with m.If(update_svstate):
 391             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 392             comb += self.state_w_sv.data_i.eq(new_svstate)
 393             sync += cur_state.svstate.eq(new_svstate) # for next clock
 394
 395     def execute_fsm(self, m, core, pc_changed, sv_changed,
 396                     exec_insn_valid_i, exec_insn_ready_o,
 397                     exec_pc_valid_o, exec_pc_ready_i):
 398         """execute FSM
 399
 400         execute FSM. this interacts with the "issue" FSM
 401         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 402         (outgoing). SVP64 RM prefixes have already been set up by the
 403         "issue" phase, so execute is fairly straightforward.
 404         """
 405
 406         comb = m.d.comb
 407         sync = m.d.sync
 408         pdecode2 = self.pdecode2
 409         svp64 = self.svp64
 410
 411         # temporaries
 412         core_busy_o = core.busy_o                 # core is busy
 413         core_ivalid_i = core.ivalid_i             # instruction is valid
 414         core_issue_i = core.issue_i               # instruction is issued
 415         insn_type = core.e.do.insn_type           # instruction MicroOp type
 416
 417         with m.FSM(name="exec_fsm"):
 418
 419             # waiting for instruction bus (stays there until not busy)
 420             with m.State("INSN_START"):
 421                 comb += exec_insn_ready_o.eq(1)
 422                 with m.If(exec_insn_valid_i):
 423                     comb += core_ivalid_i.eq(1)  # instruction is valid
 424                     comb += core_issue_i.eq(1)  # and issued
 425                     sync += sv_changed.eq(0)
 426                     sync += pc_changed.eq(0)
 427                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 428
 429             # instruction started: must wait till it finishes
 430             with m.State("INSN_ACTIVE"):
 431                 with m.If(insn_type != MicrOp.OP_NOP):
 432                     comb += core_ivalid_i.eq(1) # instruction is valid
 433                 # note changes to PC and SVSTATE
 434                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 435                     sync += sv_changed.eq(1)
 436                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 437                     sync += pc_changed.eq(1)
 438                 with m.If(~core_busy_o): # instruction done!
 439                     comb += exec_pc_valid_o.eq(1)
 440                     with m.If(exec_pc_ready_i):
 441                         m.next = "INSN_START"  # back to fetch
 442
 443     def elaborate(self, platform):
 444         m = Module()
 445         comb, sync = m.d.comb, m.d.sync
 446
 447         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 448         m.submodules.imem = imem = self.imem
 449         m.submodules.dbg = dbg = self.dbg
 450         if self.jtag_en:
 451             m.submodules.jtag = jtag = self.jtag
 452             # TODO: UART2GDB mux, here, from external pin
 453             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 454             sync += dbg.dmi.connect_to(jtag.dmi)
 455
 456         cur_state = self.cur_state
 457
 458         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 459         if self.sram4x4k:
 460             for i, sram in enumerate(self.sram4k):
 461                 m.submodules["sram4k_%d" % i] = sram
 462                 comb += sram.enable.eq(self.wb_sram_en)
 463
 464         # XICS interrupt handler
 465         if self.xics:
 466             m.submodules.xics_icp = icp = self.xics_icp
 467             m.submodules.xics_ics = ics = self.xics_ics
 468             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 469             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 470
 471         # GPIO test peripheral
 472         if self.gpio:
 473             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 474
 475         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 476         # XXX causes litex ECP5 test to get wrong idea about input and output
 477         # (but works with verilator sim *sigh*)
 478         #if self.gpio and self.xics:
 479         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 480
 481         # instruction decoder
 482         pdecode = create_pdecode()
 483         m.submodules.dec2 = pdecode2 = self.pdecode2
 484         m.submodules.svp64 = svp64 = self.svp64
 485
 486         # convenience
 487         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 488         intrf = self.core.regs.rf['int']
 489
 490         # clock delay power-on reset
 491         cd_por  = ClockDomain(reset_less=True)
 492         cd_sync = ClockDomain()
 493         core_sync = ClockDomain("coresync")
 494         m.domains += cd_por, cd_sync, core_sync
 495
 496         ti_rst = Signal(reset_less=True)
 497         delay = Signal(range(4), reset=3)
 498         with m.If(delay != 0):
 499             m.d.por += delay.eq(delay - 1)
 500         comb += cd_por.clk.eq(ClockSignal())
 501
 502         # power-on reset delay
 503         core_rst = ResetSignal("coresync")
 504         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 505         comb += core_rst.eq(ti_rst)
 506
 507         # busy/halted signals from core
 508         comb += self.busy_o.eq(core.busy_o)
 509         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 510
 511         # temporary hack: says "go" immediately for both address gen and ST
 512         l0 = core.l0
 513         ldst = core.fus.fus['ldst0']
 514         st_go_edge = rising_edge(m, ldst.st.rel_o)
 515         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 516         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 517
 518         # PC and instruction from I-Memory
 519         comb += self.pc_o.eq(cur_state.pc)
 520         pc_changed = Signal() # note write to PC
 521         sv_changed = Signal() # note write to SVSTATE
 522
 523         # read the PC
 524         pc = Signal(64, reset_less=True)
 525         pc_ok_delay = Signal()
 526         sync += pc_ok_delay.eq(~self.pc_i.ok)
 527         with m.If(self.pc_i.ok):
 528             # incoming override (start from pc_i)
 529             comb += pc.eq(self.pc_i.data)
 530         with m.Else():
 531             # otherwise read StateRegs regfile for PC...
 532             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 533         # ... but on a 1-clock delay
 534         with m.If(pc_ok_delay):
 535             comb += pc.eq(self.state_r_pc.data_o)
 536
 537         # read svstate
 538         svstate = Signal(64, reset_less=True)
 539         svstate_ok_delay = Signal()
 540         sync += svstate_ok_delay.eq(~self.svstate_i.ok)
 541         with m.If(self.svstate_i.ok):
 542             # incoming override (start from svstate__i)
 543             comb += svstate.eq(self.svstate_i.data)
 544         with m.Else():
 545             # otherwise read StateRegs regfile for SVSTATE...
 546             comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 547         # ... but on a 1-clock delay
 548         with m.If(svstate_ok_delay):
 549             comb += svstate.eq(self.state_r_sv.data_o)
 550
 551         # don't write pc every cycle
 552         comb += self.state_w_pc.wen.eq(0)
 553         comb += self.state_w_pc.data_i.eq(0)
 554
 555         # don't read msr every cycle
 556         comb += self.state_r_msr.ren.eq(0)
 557
 558         # address of the next instruction, in the absence of a branch
 559         # depends on the instruction size
 560         nia = Signal(64, reset_less=True)
 561
 562         # connect up debug signals
 563         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 564         comb += dbg.terminate_i.eq(core.core_terminate_o)
 565         comb += dbg.state.pc.eq(pc)
 566         comb += dbg.state.svstate.eq(svstate)
 567         comb += dbg.state.msr.eq(cur_state.msr)
 568
 569         # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
 570         # these are the handshake signals between fetch and decode/execute
 571
 572         # fetch FSM can run as soon as the PC is valid
 573         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 574         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 575
 576         # fetch FSM hands over the instruction to be decoded / issued
 577         fetch_insn_valid_o = Signal()
 578         fetch_insn_ready_i = Signal()
 579
 580         # issue FSM delivers the instruction to the be executed
 581         exec_insn_valid_i = Signal()
 582         exec_insn_ready_o = Signal()
 583
 584         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 585         exec_pc_valid_o = Signal()
 586         exec_pc_ready_i = Signal()
 587
 588         # the FSMs here are perhaps unusual in that they detect conditions
 589         # then "hold" information, combinatorially, for the core
 590         # (as opposed to using sync - which would be on a clock's delay)
 591         # this includes the actual opcode, valid flags and so on.
 592
 593         # Fetch, then Issue, then Execute. Issue is where the VL for-loop
 594         # lives.  the ready/valid signalling is used to communicate between
 595         # the three.
 596
 597         self.fetch_fsm(m, core, pc, svstate, nia,
 598                        fetch_pc_ready_o, fetch_pc_valid_i,
 599                        fetch_insn_valid_o, fetch_insn_ready_i)
 600
 601         self.issue_fsm(m, core, pc_changed, sv_changed, nia,
 602                        dbg, core_rst,
 603                        fetch_pc_ready_o, fetch_pc_valid_i,
 604                        fetch_insn_valid_o, fetch_insn_ready_i,
 605                        exec_insn_valid_i, exec_insn_ready_o,
 606                        exec_pc_valid_o, exec_pc_ready_i)
 607
 608         self.execute_fsm(m, core, pc_changed, sv_changed,
 609                          exec_insn_valid_i, exec_insn_ready_o,
 610                          exec_pc_valid_o, exec_pc_ready_i)
 611
 612         # this bit doesn't have to be in the FSM: connect up to read
 613         # regfiles on demand from DMI
 614         self.do_dmi(m, dbg)
 615
 616         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 617         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 618         self.tb_dec_fsm(m, cur_state.dec)
 619
 620         return m
 621
 622     def do_dmi(self, m, dbg):
 623         comb = m.d.comb
 624         sync = m.d.sync
 625         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 626         intrf = self.core.regs.rf['int']
 627
 628         with m.If(d_reg.req): # request for regfile access being made
 629             # TODO: error-check this
 630             # XXX should this be combinatorial?  sync better?
 631             if intrf.unary:
 632                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 633             else:
 634                 comb += self.int_r.addr.eq(d_reg.addr)
 635                 comb += self.int_r.ren.eq(1)
 636         d_reg_delay  = Signal()
 637         sync += d_reg_delay.eq(d_reg.req)
 638         with m.If(d_reg_delay):
 639             # data arrives one clock later
 640             comb += d_reg.data.eq(self.int_r.data_o)
 641             comb += d_reg.ack.eq(1)
 642
 643         # sigh same thing for CR debug
 644         with m.If(d_cr.req): # request for regfile access being made
 645             comb += self.cr_r.ren.eq(0b11111111) # enable all
 646         d_cr_delay  = Signal()
 647         sync += d_cr_delay.eq(d_cr.req)
 648         with m.If(d_cr_delay):
 649             # data arrives one clock later
 650             comb += d_cr.data.eq(self.cr_r.data_o)
 651             comb += d_cr.ack.eq(1)
 652
 653         # aaand XER...
 654         with m.If(d_xer.req): # request for regfile access being made
 655             comb += self.xer_r.ren.eq(0b111111) # enable all
 656         d_xer_delay  = Signal()
 657         sync += d_xer_delay.eq(d_xer.req)
 658         with m.If(d_xer_delay):
 659             # data arrives one clock later
 660             comb += d_xer.data.eq(self.xer_r.data_o)
 661             comb += d_xer.ack.eq(1)
 662
 663     def tb_dec_fsm(self, m, spr_dec):
 664         """tb_dec_fsm
 665
 666         this is a FSM for updating either dec or tb.  it runs alternately
 667         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 668         value to DEC, however the regfile has "passthrough" on it so this
 669         *should* be ok.
 670
 671         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 672         """
 673
 674         comb, sync = m.d.comb, m.d.sync
 675         fast_rf = self.core.regs.rf['fast']
 676         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 677         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 678
 679         with m.FSM() as fsm:
 680
 681             # initiates read of current DEC
 682             with m.State("DEC_READ"):
 683                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 684                 comb += fast_r_dectb.ren.eq(1)
 685                 m.next = "DEC_WRITE"
 686
 687             # waits for DEC read to arrive (1 cycle), updates with new value
 688             with m.State("DEC_WRITE"):
 689                 new_dec = Signal(64)
 690                 # TODO: MSR.LPCR 32-bit decrement mode
 691                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 692                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 693                 comb += fast_w_dectb.wen.eq(1)
 694                 comb += fast_w_dectb.data_i.eq(new_dec)
 695                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 696                 m.next = "TB_READ"
 697
 698             # initiates read of current TB
 699             with m.State("TB_READ"):
 700                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 701                 comb += fast_r_dectb.ren.eq(1)
 702                 m.next = "TB_WRITE"
 703
 704             # waits for read TB to arrive, initiates write of current TB
 705             with m.State("TB_WRITE"):
 706                 new_tb = Signal(64)
 707                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 708                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 709                 comb += fast_w_dectb.wen.eq(1)
 710                 comb += fast_w_dectb.data_i.eq(new_tb)
 711                 m.next = "DEC_READ"
 712
 713         return m
 714
 715     def __iter__(self):
 716         yield from self.pc_i.ports()
 717         yield self.pc_o
 718         yield self.memerr_o
 719         yield from self.core.ports()
 720         yield from self.imem.ports()
 721         yield self.core_bigendian_i
 722         yield self.busy_o
 723
 724     def ports(self):
 725         return list(self)
 726
 727     def external_ports(self):
 728         ports = self.pc_i.ports()
 729         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 730                 ]
 731
 732         if self.jtag_en:
 733             ports += list(self.jtag.external_ports())
 734         else:
 735             # don't add DMI if JTAG is enabled
 736             ports += list(self.dbg.dmi.ports())
 737
 738         ports += list(self.imem.ibus.fields.values())
 739         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 740
 741         if self.sram4x4k:
 742             for sram in self.sram4k:
 743                 ports += list(sram.bus.fields.values())
 744
 745         if self.xics:
 746             ports += list(self.xics_icp.bus.fields.values())
 747             ports += list(self.xics_ics.bus.fields.values())
 748             ports.append(self.int_level_i)
 749
 750         if self.gpio:
 751             ports += list(self.simple_gpio.bus.fields.values())
 752             ports.append(self.gpio_o)
 753
 754         return ports
 755
 756     def ports(self):
 757         return list(self)
 758
 759
 760 class TestIssuer(Elaboratable):
 761     def __init__(self, pspec):
 762         self.ti = TestIssuerInternal(pspec)
 763
 764         self.pll = DummyPLL()
 765
 766         # PLL direct clock or not
 767         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 768         if self.pll_en:
 769             self.pll_18_o = Signal(reset_less=True)
 770
 771     def elaborate(self, platform):
 772         m = Module()
 773         comb = m.d.comb
 774
 775         # TestIssuer runs at direct clock
 776         m.submodules.ti = ti = self.ti
 777         cd_int = ClockDomain("coresync")
 778
 779         if self.pll_en:
 780             # ClockSelect runs at PLL output internal clock rate
 781             m.submodules.pll = pll = self.pll
 782
 783             # add clock domains from PLL
 784             cd_pll = ClockDomain("pllclk")
 785             m.domains += cd_pll
 786
 787             # PLL clock established.  has the side-effect of running clklsel
 788             # at the PLL's speed (see DomainRenamer("pllclk") above)
 789             pllclk = ClockSignal("pllclk")
 790             comb += pllclk.eq(pll.clk_pll_o)
 791
 792             # wire up external 24mhz to PLL
 793             comb += pll.clk_24_i.eq(ClockSignal())
 794
 795             # output 18 mhz PLL test signal
 796             comb += self.pll_18_o.eq(pll.pll_18_o)
 797
 798             # now wire up ResetSignals.  don't mind them being in this domain
 799             pll_rst = ResetSignal("pllclk")
 800             comb += pll_rst.eq(ResetSignal())
 801
 802         # internal clock is set to selector clock-out.  has the side-effect of
 803         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 804         intclk = ClockSignal("coresync")
 805         if self.pll_en:
 806             comb += intclk.eq(pll.clk_pll_o)
 807         else:
 808             comb += intclk.eq(ClockSignal())
 809
 810         return m
 811
 812     def ports(self):
 813         return list(self.ti.ports()) + list(self.pll.ports()) + \
 814                [ClockSignal(), ResetSignal()]
 815
 816     def external_ports(self):
 817         ports = self.ti.external_ports()
 818         ports.append(ClockSignal())
 819         ports.append(ResetSignal())
 820         if self.pll_en:
 821             ports.append(self.pll.clk_sel_i)
 822             ports.append(self.pll_18_o)
 823             ports.append(self.pll.pll_lck_o)
 824         return ports
 825
 826
 827 if __name__ == '__main__':
 828     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 829              'spr': 1,
 830              'div': 1,
 831              'mul': 1,
 832              'shiftrot': 1
 833             }
 834     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 835                          imem_ifacetype='bare_wb',
 836                          addr_wid=48,
 837                          mask_wid=8,
 838                          reg_wid=64,
 839                          units=units)
 840     dut = TestIssuer(pspec)
 841     vl = main(dut, ports=dut.ports(), name="test_issuer")
 842
 843     if len(sys.argv) == 1:
 844         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 845         with open("test_issuer.il", "w") as f:
 846             f.write(vl)