src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const, Repl, Cat)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from nmutil.singlepipe import ControlBase
  25 from soc.simple.core_data import FetchOutput, FetchInput
  26
  27 from nmigen.lib.coding import PriorityEncoder
  28
  29 from openpower.decoder.power_decoder import create_pdecode
  30 from openpower.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  31 from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
  32 from openpower.decoder.decode2execute1 import Data
  33 from openpower.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
  34                                            SVP64PredMode)
  35 from openpower.state import CoreState
  36 from openpower.consts import (CR, SVP64CROffs, MSR)
  37 from soc.experiment.testmem import TestMemory  # test only for instructions
  38 from soc.regfile.regfiles import StateRegs, FastRegs
  39 from soc.simple.core import NonProductionCore
  40 from soc.config.test.test_loadstore import TestMemPspec
  41 from soc.config.ifetch import ConfigFetchUnit
  42 from soc.debug.dmi import CoreDebug, DMIInterface
  43 from soc.debug.jtag import JTAG
  44 from soc.config.pinouts import get_pinspecs
  45 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  46 from soc.bus.simple_gpio import SimpleGPIO
  47 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  48 from soc.clock.select import ClockSelect
  49 from soc.clock.dummypll import DummyPLL
  50 from openpower.sv.svstate import SVSTATERec
  51 from soc.experiment.icache import ICache
  52
  53 from nmutil.util import rising_edge
  54
  55
  56 def get_insn(f_instr_o, pc):
  57     if f_instr_o.width == 32:
  58         return f_instr_o
  59     else:
  60         # 64-bit: bit 2 of pc decides which word to select
  61         return f_instr_o.word_select(pc[2], 32)
  62
  63 # gets state input or reads from state regfile
  64
  65
  66 def state_get(m, res, core_rst, state_i, name, regfile, regnum):
  67     comb = m.d.comb
  68     sync = m.d.sync
  69     # read the {insert state variable here}
  70     res_ok_delay = Signal(name="%s_ok_delay" % name)
  71     with m.If(~core_rst):
  72         sync += res_ok_delay.eq(~state_i.ok)
  73         with m.If(state_i.ok):
  74             # incoming override (start from pc_i)
  75             comb += res.eq(state_i.data)
  76         with m.Else():
  77             # otherwise read StateRegs regfile for {insert state here}...
  78             comb += regfile.ren.eq(1 << regnum)
  79         # ... but on a 1-clock delay
  80         with m.If(res_ok_delay):
  81             comb += res.eq(regfile.o_data)
  82
  83
  84 def get_predint(m, mask, name):
  85     """decode SVP64 predicate integer mask field to reg number and invert
  86     this is identical to the equivalent function in ISACaller except that
  87     it doesn't read the INT directly, it just decodes "what needs to be done"
  88     i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
  89
  90     * all1s is set to indicate that no mask is to be applied.
  91     * regread indicates the GPR register number to be read
  92     * invert is set to indicate that the register value is to be inverted
  93     * unary indicates that the contents of the register is to be shifted 1<<r3
  94     """
  95     comb = m.d.comb
  96     regread = Signal(5, name=name+"regread")
  97     invert = Signal(name=name+"invert")
  98     unary = Signal(name=name+"unary")
  99     all1s = Signal(name=name+"all1s")
 100     with m.Switch(mask):
 101         with m.Case(SVP64PredInt.ALWAYS.value):
 102             comb += all1s.eq(1)      # use 0b1111 (all ones)
 103         with m.Case(SVP64PredInt.R3_UNARY.value):
 104             comb += regread.eq(3)
 105             comb += unary.eq(1)        # 1<<r3 - shift r3 (single bit)
 106         with m.Case(SVP64PredInt.R3.value):
 107             comb += regread.eq(3)
 108         with m.Case(SVP64PredInt.R3_N.value):
 109             comb += regread.eq(3)
 110             comb += invert.eq(1)
 111         with m.Case(SVP64PredInt.R10.value):
 112             comb += regread.eq(10)
 113         with m.Case(SVP64PredInt.R10_N.value):
 114             comb += regread.eq(10)
 115             comb += invert.eq(1)
 116         with m.Case(SVP64PredInt.R30.value):
 117             comb += regread.eq(30)
 118         with m.Case(SVP64PredInt.R30_N.value):
 119             comb += regread.eq(30)
 120             comb += invert.eq(1)
 121     return regread, invert, unary, all1s
 122
 123
 124 def get_predcr(m, mask, name):
 125     """decode SVP64 predicate CR to reg number field and invert status
 126     this is identical to _get_predcr in ISACaller
 127     """
 128     comb = m.d.comb
 129     idx = Signal(2, name=name+"idx")
 130     invert = Signal(name=name+"crinvert")
 131     with m.Switch(mask):
 132         with m.Case(SVP64PredCR.LT.value):
 133             comb += idx.eq(CR.LT)
 134             comb += invert.eq(0)
 135         with m.Case(SVP64PredCR.GE.value):
 136             comb += idx.eq(CR.LT)
 137             comb += invert.eq(1)
 138         with m.Case(SVP64PredCR.GT.value):
 139             comb += idx.eq(CR.GT)
 140             comb += invert.eq(0)
 141         with m.Case(SVP64PredCR.LE.value):
 142             comb += idx.eq(CR.GT)
 143             comb += invert.eq(1)
 144         with m.Case(SVP64PredCR.EQ.value):
 145             comb += idx.eq(CR.EQ)
 146             comb += invert.eq(0)
 147         with m.Case(SVP64PredCR.NE.value):
 148             comb += idx.eq(CR.EQ)
 149             comb += invert.eq(1)
 150         with m.Case(SVP64PredCR.SO.value):
 151             comb += idx.eq(CR.SO)
 152             comb += invert.eq(0)
 153         with m.Case(SVP64PredCR.NS.value):
 154             comb += idx.eq(CR.SO)
 155             comb += invert.eq(1)
 156     return idx, invert
 157
 158
 159 class TestIssuerBase(Elaboratable):
 160     """TestIssuerBase - common base class for Issuers
 161
 162     takes care of power-on reset, peripherals, debug, DEC/TB,
 163     and gets PC/MSR/SVSTATE from the State Regfile etc.
 164     """
 165
 166     def __init__(self, pspec):
 167
 168         # test if microwatt compatibility is to be enabled
 169         self.microwatt_compat = (hasattr(pspec, "microwatt_compat") and
 170                                  (pspec.microwatt_compat == True))
 171         self.alt_reset = Signal(reset_less=True) # not connected yet (microwatt)
 172
 173         # test is SVP64 is to be enabled
 174         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
 175
 176         # and if regfiles are reduced
 177         self.regreduce_en = (hasattr(pspec, "regreduce") and
 178                              (pspec.regreduce == True))
 179
 180         # and if overlap requested
 181         self.allow_overlap = (hasattr(pspec, "allow_overlap") and
 182                               (pspec.allow_overlap == True))
 183
 184         # and get the core domain
 185         self.core_domain = "coresync"
 186         if (hasattr(pspec, "core_domain") and
 187             isinstance(pspec.core_domain, str)):
 188             self.core_domain = pspec.core_domain
 189
 190         # JTAG interface.  add this right at the start because if it's
 191         # added it *modifies* the pspec, by adding enable/disable signals
 192         # for parts of the rest of the core
 193         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
 194         #self.dbg_domain = "sync"  # sigh "dbgsunc" too problematic
 195         self.dbg_domain = "dbgsync" # domain for DMI/JTAG clock
 196         if self.jtag_en:
 197             # XXX MUST keep this up-to-date with litex, and
 198             # soc-cocotb-sim, and err.. all needs sorting out, argh
 199             subset = ['uart',
 200                       'mtwi',
 201                       'eint', 'gpio', 'mspi0',
 202                       # 'mspi1', - disabled for now
 203                       # 'pwm', 'sd0', - disabled for now
 204                       'sdr']
 205             self.jtag = JTAG(get_pinspecs(subset=subset),
 206                              domain=self.dbg_domain)
 207             # add signals to pspec to enable/disable icache and dcache
 208             # (or data and intstruction wishbone if icache/dcache not included)
 209             # https://bugs.libre-soc.org/show_bug.cgi?id=520
 210             # TODO: do we actually care if these are not domain-synchronised?
 211             # honestly probably not.
 212             pspec.wb_icache_en = self.jtag.wb_icache_en
 213             pspec.wb_dcache_en = self.jtag.wb_dcache_en
 214             self.wb_sram_en = self.jtag.wb_sram_en
 215         else:
 216             self.wb_sram_en = Const(1)
 217
 218         # add 4k sram blocks?
 219         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
 220                          pspec.sram4x4kblock == True)
 221         if self.sram4x4k:
 222             self.sram4k = []
 223             for i in range(4):
 224                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
 225                                                     # features={'err'}
 226                                                     ))
 227
 228         # add interrupt controller?
 229         self.xics = hasattr(pspec, "xics") and pspec.xics == True
 230         if self.xics:
 231             self.xics_icp = XICS_ICP()
 232             self.xics_ics = XICS_ICS()
 233             self.int_level_i = self.xics_ics.int_level_i
 234         else:
 235             self.ext_irq = Signal()
 236
 237         # add GPIO peripheral?
 238         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
 239         if self.gpio:
 240             self.simple_gpio = SimpleGPIO()
 241             self.gpio_o = self.simple_gpio.gpio_o
 242
 243         # main instruction core.  suitable for prototyping / demo only
 244         self.core = core = NonProductionCore(pspec)
 245         self.core_rst = ResetSignal(self.core_domain)
 246
 247         # instruction decoder.  goes into Trap Record
 248         #pdecode = create_pdecode()
 249         self.cur_state = CoreState("cur")  # current state (MSR/PC/SVSTATE)
 250         self.pdecode2 = PowerDecode2(None, state=self.cur_state,
 251                                      opkls=IssuerDecode2ToOperand,
 252                                      svp64_en=self.svp64_en,
 253                                      regreduce_en=self.regreduce_en)
 254         pdecode = self.pdecode2.dec
 255
 256         if self.svp64_en:
 257             self.svp64 = SVP64PrefixDecoder()  # for decoding SVP64 prefix
 258
 259         self.update_svstate = Signal()  # set this if updating svstate
 260         self.new_svstate = new_svstate = SVSTATERec("new_svstate")
 261
 262         # Test Instruction memory
 263         if hasattr(core, "icache"):
 264             # XXX BLECH! use pspec to transfer the I-Cache to ConfigFetchUnit
 265             # truly dreadful.  needs a huge reorg.
 266             pspec.icache = core.icache
 267         self.imem = ConfigFetchUnit(pspec).fu
 268
 269         # DMI interface
 270         self.dbg = CoreDebug()
 271         self.dbg_rst_i = Signal(reset_less=True)
 272
 273         # instruction go/monitor
 274         self.pc_o = Signal(64, reset_less=True)
 275         self.pc_i = Data(64, "pc_i")  # set "ok" to indicate "please change me"
 276         self.msr_i = Data(64, "msr_i") # set "ok" to indicate "please change me"
 277         self.svstate_i = Data(64, "svstate_i")  # ditto
 278         self.core_bigendian_i = Signal()  # TODO: set based on MSR.LE
 279         self.busy_o = Signal(reset_less=True)
 280         self.memerr_o = Signal(reset_less=True)
 281
 282         # STATE regfile read /write ports for PC, MSR, SVSTATE
 283         staterf = self.core.regs.rf['state']
 284         self.state_r_msr = staterf.r_ports['msr']  # MSR rd
 285         self.state_r_pc = staterf.r_ports['cia']  # PC rd
 286         self.state_r_sv = staterf.r_ports['sv']  # SVSTATE rd
 287
 288         self.state_w_msr = staterf.w_ports['d_wr2']  # MSR wr
 289         self.state_w_pc = staterf.w_ports['d_wr1']  # PC wr
 290         self.state_w_sv = staterf.w_ports['sv']  # SVSTATE wr
 291
 292         # DMI interface access
 293         intrf = self.core.regs.rf['int']
 294         crrf = self.core.regs.rf['cr']
 295         xerrf = self.core.regs.rf['xer']
 296         self.int_r = intrf.r_ports['dmi']  # INT read
 297         self.cr_r = crrf.r_ports['full_cr_dbg']  # CR read
 298         self.xer_r = xerrf.r_ports['full_xer']  # XER read
 299
 300         if self.svp64_en:
 301             # for predication
 302             self.int_pred = intrf.r_ports['pred']  # INT predicate read
 303             self.cr_pred = crrf.r_ports['cr_pred']  # CR predicate read
 304
 305         # hack method of keeping an eye on whether branch/trap set the PC
 306         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 307         self.state_nia.wen.name = 'state_nia_wen'
 308
 309         # pulse to synchronize the simulator at instruction end
 310         self.insn_done = Signal()
 311
 312         # indicate any instruction still outstanding, in execution
 313         self.any_busy = Signal()
 314
 315         if self.svp64_en:
 316             # store copies of predicate masks
 317             self.srcmask = Signal(64)
 318             self.dstmask = Signal(64)
 319
 320         # sigh, the wishbone addresses are not wishbone-compliant in microwatt
 321         if self.microwatt_compat:
 322             self.ibus_adr = Signal(32, name='wishbone_insn_out.adr')
 323             self.dbus_adr = Signal(32, name='wishbone_data_out.adr')
 324
 325         # add an output of the PC and instruction, and whether it was requested
 326         # this is for verilator debug purposes
 327         if self.microwatt_compat:
 328             self.nia = Signal(64)
 329             self.msr_o = Signal(64)
 330             self.nia_req = Signal(1)
 331             self.insn = Signal(32)
 332             self.ldst_req = Signal(1)
 333             self.ldst_addr = Signal(1)
 334
 335         # for pausing dec/tb during an SPR pipeline event, this
 336         # ensures that an SPR write (mtspr) to TB or DEC does not
 337         # get overwritten by the DEC/TB FSM
 338         self.pause_dec_tb = Signal()
 339
 340     def setup_peripherals(self, m):
 341         comb, sync = m.d.comb, m.d.sync
 342
 343         # okaaaay so the debug module must be in coresync clock domain
 344         # but NOT its reset signal. to cope with this, set every single
 345         # submodule explicitly in coresync domain, debug and JTAG
 346         # in their own one but using *external* reset.
 347         csd = DomainRenamer(self.core_domain)
 348         dbd = DomainRenamer(self.dbg_domain)
 349
 350         if self.microwatt_compat:
 351             m.submodules.core = core = self.core
 352         else:
 353             m.submodules.core = core = csd(self.core)
 354
 355         # this _so_ needs sorting out.  ICache is added down inside
 356         # LoadStore1 and is already a submodule of LoadStore1
 357         if not isinstance(self.imem, ICache):
 358             m.submodules.imem = imem = csd(self.imem)
 359
 360         # set up JTAG Debug Module (in correct domain)
 361         m.submodules.dbg = dbg = dbd(self.dbg)
 362         if self.jtag_en:
 363             m.submodules.jtag = jtag = dbd(self.jtag)
 364             # TODO: UART2GDB mux, here, from external pin
 365             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 366             sync += dbg.dmi.connect_to(jtag.dmi)
 367
 368         # fixup the clocks in microwatt-compat mode (but leave resets alone
 369         # so that microwatt soc.vhdl can pull a reset on the core or DMI
 370         # can do it, just like in TestIssuer)
 371         if self.microwatt_compat:
 372             intclk = ClockSignal(self.core_domain)
 373             dbgclk = ClockSignal(self.dbg_domain)
 374             if self.core_domain != 'sync':
 375                 comb += intclk.eq(ClockSignal())
 376             if self.dbg_domain != 'sync':
 377                 comb += dbgclk.eq(ClockSignal())
 378
 379         # drop the first 3 bits of the incoming wishbone addresses
 380         # this can go if using later versions of microwatt (not now)
 381         if self.microwatt_compat:
 382             ibus = self.imem.ibus
 383             dbus = self.core.l0.cmpi.wb_bus()
 384             comb += self.ibus_adr.eq(Cat(Const(0, 3), ibus.adr))
 385             comb += self.dbus_adr.eq(Cat(Const(0, 3), dbus.adr))
 386             # microwatt verilator debug purposes
 387             pi = self.core.l0.cmpi.pi.pi
 388             comb += self.ldst_req.eq(pi.addr_ok_o)
 389             comb += self.ldst_addr.eq(pi.addr)
 390
 391         cur_state = self.cur_state
 392
 393         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 394         if self.sram4x4k:
 395             for i, sram in enumerate(self.sram4k):
 396                 m.submodules["sram4k_%d" % i] = csd(sram)
 397                 comb += sram.enable.eq(self.wb_sram_en)
 398
 399         # terrible hack to stop a potential race condition.  if core
 400         # is doing any operation (at all) pause the DEC/TB FSM
 401         comb += self.pause_dec_tb.eq(core.pause_dec_tb)
 402
 403         # XICS interrupt handler
 404         if self.xics:
 405             m.submodules.xics_icp = icp = csd(self.xics_icp)
 406             m.submodules.xics_ics = ics = csd(self.xics_ics)
 407             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 408             sync += cur_state.eint.eq(icp.core_irq_o)  # connect ICP to core
 409         else:
 410             sync += cur_state.eint.eq(self.ext_irq)  # connect externally
 411
 412         # GPIO test peripheral
 413         if self.gpio:
 414             m.submodules.simple_gpio = simple_gpio = csd(self.simple_gpio)
 415
 416         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 417         # XXX causes litex ECP5 test to get wrong idea about input and output
 418         # (but works with verilator sim *sigh*)
 419         # if self.gpio and self.xics:
 420         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 421
 422         # instruction decoder
 423         pdecode = create_pdecode()
 424         m.submodules.dec2 = pdecode2 = csd(self.pdecode2)
 425         if self.svp64_en:
 426             m.submodules.svp64 = svp64 = csd(self.svp64)
 427
 428         # convenience
 429         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 430         intrf = self.core.regs.rf['int']
 431
 432         # clock delay power-on reset
 433         cd_por = ClockDomain(reset_less=True)
 434         cd_sync = ClockDomain()
 435         m.domains += cd_por, cd_sync
 436         core_sync = ClockDomain(self.core_domain)
 437         if self.core_domain != "sync":
 438             m.domains += core_sync
 439         if self.dbg_domain != "sync":
 440             dbg_sync = ClockDomain(self.dbg_domain)
 441             m.domains += dbg_sync
 442
 443         ti_rst = Signal(reset_less=True)
 444         delay = Signal(range(4), reset=3)
 445         with m.If(delay != 0):
 446             m.d.por += delay.eq(delay - 1)
 447         comb += cd_por.clk.eq(ClockSignal())
 448
 449         # power-on reset delay
 450         core_rst = ResetSignal(self.core_domain)
 451         if self.core_domain != "sync":
 452             comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 453             comb += core_rst.eq(ti_rst)
 454         else:
 455             with m.If(delay != 0 | dbg.core_rst_o):
 456                 comb += core_rst.eq(1)
 457
 458         # connect external reset signal to DMI Reset
 459         if self.dbg_domain != "sync":
 460             dbg_rst = ResetSignal(self.dbg_domain)
 461             comb += dbg_rst.eq(self.dbg_rst_i)
 462
 463         # busy/halted signals from core
 464         core_busy_o = ~core.p.o_ready | core.n.o_data.busy_o  # core is busy
 465         comb += self.busy_o.eq(core_busy_o)
 466         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 467
 468         # temporary hack: says "go" immediately for both address gen and ST
 469         l0 = core.l0
 470         ldst = core.fus.fus['ldst0']
 471         st_go_edge = rising_edge(m, ldst.st.rel_o)
 472         # link addr-go direct to rel
 473         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o)
 474         m.d.comb += ldst.st.go_i.eq(st_go_edge)  # link store-go to rising rel
 475
 476     def do_dmi(self, m, dbg):
 477         """deals with DMI debug requests
 478
 479         currently only provides read requests for the INT regfile, CR and XER
 480         it will later also deal with *writing* to these regfiles.
 481         """
 482         comb = m.d.comb
 483         sync = m.d.sync
 484         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 485         intrf = self.core.regs.rf['int']
 486
 487         with m.If(d_reg.req):  # request for regfile access being made
 488             # TODO: error-check this
 489             # XXX should this be combinatorial?  sync better?
 490             if intrf.unary:
 491                 comb += self.int_r.ren.eq(1 << d_reg.addr)
 492             else:
 493                 comb += self.int_r.addr.eq(d_reg.addr)
 494                 comb += self.int_r.ren.eq(1)
 495         d_reg_delay = Signal()
 496         sync += d_reg_delay.eq(d_reg.req)
 497         with m.If(d_reg_delay):
 498             # data arrives one clock later
 499             comb += d_reg.data.eq(self.int_r.o_data)
 500             comb += d_reg.ack.eq(1)
 501
 502         # sigh same thing for CR debug
 503         with m.If(d_cr.req):  # request for regfile access being made
 504             comb += self.cr_r.ren.eq(0b11111111)  # enable all
 505         d_cr_delay = Signal()
 506         sync += d_cr_delay.eq(d_cr.req)
 507         with m.If(d_cr_delay):
 508             # data arrives one clock later
 509             comb += d_cr.data.eq(self.cr_r.o_data)
 510             comb += d_cr.ack.eq(1)
 511
 512         # aaand XER...
 513         with m.If(d_xer.req):  # request for regfile access being made
 514             comb += self.xer_r.ren.eq(0b111111)  # enable all
 515         d_xer_delay = Signal()
 516         sync += d_xer_delay.eq(d_xer.req)
 517         with m.If(d_xer_delay):
 518             # data arrives one clock later
 519             comb += d_xer.data.eq(self.xer_r.o_data)
 520             comb += d_xer.ack.eq(1)
 521
 522     def tb_dec_fsm(self, m, spr_dec):
 523         """tb_dec_fsm
 524
 525         this is a FSM for updating either dec or tb.  it runs alternately
 526         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 527         value to DEC, however the regfile has "passthrough" on it so this
 528         *should* be ok.
 529
 530         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 531         """
 532
 533         comb, sync = m.d.comb, m.d.sync
 534         fast_rf = self.core.regs.rf['fast']
 535         fast_r_dectb = fast_rf.r_ports['issue']  # DEC/TB
 536         fast_w_dectb = fast_rf.w_ports['issue']  # DEC/TB
 537
 538         with m.FSM() as fsm:
 539
 540             # initiates read of current DEC
 541             with m.State("DEC_READ"):
 542                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 543                 comb += fast_r_dectb.ren.eq(1)
 544                 with m.If(~self.pause_dec_tb):
 545                     m.next = "DEC_WRITE"
 546
 547             # waits for DEC read to arrive (1 cycle), updates with new value
 548             # respects if dec/tb writing has been paused
 549             with m.State("DEC_WRITE"):
 550                 with m.If(self.pause_dec_tb):
 551                     # if paused, return to reading
 552                     m.next = "DEC_READ"
 553                 with m.Else():
 554                     new_dec = Signal(64)
 555                     # TODO: MSR.LPCR 32-bit decrement mode
 556                     comb += new_dec.eq(fast_r_dectb.o_data - 1)
 557                     comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 558                     comb += fast_w_dectb.wen.eq(1)
 559                     comb += fast_w_dectb.i_data.eq(new_dec)
 560                     # copy to cur_state for decoder, for an interrupt
 561                     sync += spr_dec.eq(new_dec)
 562                     m.next = "TB_READ"
 563
 564             # initiates read of current TB
 565             with m.State("TB_READ"):
 566                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 567                 comb += fast_r_dectb.ren.eq(1)
 568                 with m.If(~self.pause_dec_tb):
 569                     m.next = "TB_WRITE"
 570
 571             # waits for read TB to arrive, initiates write of current TB
 572             # respects if dec/tb writing has been paused
 573             with m.State("TB_WRITE"):
 574                 with m.If(self.pause_dec_tb):
 575                     # if paused, return to reading
 576                     m.next = "TB_READ"
 577                 with m.Else():
 578                     new_tb = Signal(64)
 579                     comb += new_tb.eq(fast_r_dectb.o_data + 1)
 580                     comb += fast_w_dectb.addr.eq(FastRegs.TB)
 581                     comb += fast_w_dectb.wen.eq(1)
 582                     comb += fast_w_dectb.i_data.eq(new_tb)
 583                     m.next = "DEC_READ"
 584
 585         return m
 586
 587     def elaborate(self, platform):
 588         m = Module()
 589         # convenience
 590         comb, sync = m.d.comb, m.d.sync
 591         cur_state = self.cur_state
 592         pdecode2 = self.pdecode2
 593         dbg = self.dbg
 594
 595         # set up peripherals and core
 596         core_rst = self.core_rst
 597         self.setup_peripherals(m)
 598
 599         # reset current state if core reset requested
 600         with m.If(core_rst):
 601             m.d.sync += self.cur_state.eq(0)
 602
 603         # check halted condition: requested PC to execute matches DMI stop addr
 604         # and immediately stop. address of 0xffff_ffff_ffff_ffff can never
 605         # match
 606         halted = Signal()
 607         comb += halted.eq(dbg.stop_addr_o == dbg.state.pc)
 608         with m.If(halted):
 609             comb += dbg.core_stopped_i.eq(1)
 610             comb += dbg.terminate_i.eq(1)
 611
 612         # PC and instruction from I-Memory
 613         comb += self.pc_o.eq(cur_state.pc)
 614         self.pc_changed = Signal()  # note write to PC
 615         self.msr_changed = Signal()  # note write to MSR
 616         self.sv_changed = Signal()  # note write to SVSTATE
 617
 618         # read state either from incoming override or from regfile
 619         state = CoreState("get")  # current state (MSR/PC/SVSTATE)
 620         state_get(m, state.msr, core_rst, self.msr_i,
 621                        "msr",                  # read MSR
 622                        self.state_r_msr, StateRegs.MSR)
 623         state_get(m, state.pc, core_rst, self.pc_i,
 624                        "pc",                  # read PC
 625                        self.state_r_pc, StateRegs.PC)
 626         state_get(m, state.svstate, core_rst, self.svstate_i,
 627                             "svstate",   # read SVSTATE
 628                             self.state_r_sv, StateRegs.SVSTATE)
 629
 630         # don't write pc every cycle
 631         comb += self.state_w_pc.wen.eq(0)
 632         comb += self.state_w_pc.i_data.eq(0)
 633
 634         # connect up debug state.  note "combinatorially same" below,
 635         # this is a bit naff, passing state over in the dbg class, but
 636         # because it is combinatorial it achieves the desired goal
 637         comb += dbg.state.eq(state)
 638
 639         # this bit doesn't have to be in the FSM: connect up to read
 640         # regfiles on demand from DMI
 641         self.do_dmi(m, dbg)
 642
 643         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 644         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 645         self.tb_dec_fsm(m, cur_state.dec)
 646
 647         # while stopped, allow updating the MSR, PC and SVSTATE.
 648         # these are mainly for debugging purposes (including DMI/JTAG)
 649         with m.If(dbg.core_stopped_i):
 650             with m.If(self.pc_i.ok):
 651                 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 652                 comb += self.state_w_pc.i_data.eq(self.pc_i.data)
 653                 sync += self.pc_changed.eq(1)
 654             with m.If(self.msr_i.ok):
 655                 comb += self.state_w_msr.wen.eq(1 << StateRegs.MSR)
 656                 comb += self.state_w_msr.i_data.eq(self.msr_i.data)
 657                 sync += self.msr_changed.eq(1)
 658             with m.If(self.svstate_i.ok | self.update_svstate):
 659                 with m.If(self.svstate_i.ok): # over-ride from external source
 660                     comb += self.new_svstate.eq(self.svstate_i.data)
 661                 comb += self.state_w_sv.wen.eq(1 << StateRegs.SVSTATE)
 662                 comb += self.state_w_sv.i_data.eq(self.new_svstate)
 663                 sync += self.sv_changed.eq(1)
 664
 665         # start renaming some of the ports to match microwatt
 666         if self.microwatt_compat:
 667             self.core.o.core_terminate_o.name = "terminated_out"
 668             # names of DMI interface
 669             self.dbg.dmi.addr_i.name = 'dmi_addr'
 670             self.dbg.dmi.din.name    = 'dmi_din'
 671             self.dbg.dmi.dout.name   = 'dmi_dout'
 672             self.dbg.dmi.req_i.name  = 'dmi_req'
 673             self.dbg.dmi.we_i.name   = 'dmi_wr'
 674             self.dbg.dmi.ack_o.name  = 'dmi_ack'
 675             # wishbone instruction bus
 676             ibus = self.imem.ibus
 677             ibus.adr.name = 'wishbone_insn_out.adr'
 678             ibus.dat_w.name = 'wishbone_insn_out.dat'
 679             ibus.sel.name = 'wishbone_insn_out.sel'
 680             ibus.cyc.name = 'wishbone_insn_out.cyc'
 681             ibus.stb.name = 'wishbone_insn_out.stb'
 682             ibus.we.name = 'wishbone_insn_out.we'
 683             ibus.dat_r.name = 'wishbone_insn_in.dat'
 684             ibus.ack.name = 'wishbone_insn_in.ack'
 685             ibus.stall.name = 'wishbone_insn_in.stall'
 686             # wishbone data bus
 687             dbus = self.core.l0.cmpi.wb_bus()
 688             dbus.adr.name = 'wishbone_data_out.adr'
 689             dbus.dat_w.name = 'wishbone_data_out.dat'
 690             dbus.sel.name = 'wishbone_data_out.sel'
 691             dbus.cyc.name = 'wishbone_data_out.cyc'
 692             dbus.stb.name = 'wishbone_data_out.stb'
 693             dbus.we.name = 'wishbone_data_out.we'
 694             dbus.dat_r.name = 'wishbone_data_in.dat'
 695             dbus.ack.name = 'wishbone_data_in.ack'
 696             dbus.stall.name = 'wishbone_data_in.stall'
 697
 698         return m
 699
 700     def __iter__(self):
 701         yield from self.pc_i.ports()
 702         yield from self.msr_i.ports()
 703         yield self.pc_o
 704         yield self.memerr_o
 705         yield from self.core.ports()
 706         yield from self.imem.ports()
 707         yield self.core_bigendian_i
 708         yield self.busy_o
 709
 710     def ports(self):
 711         return list(self)
 712
 713     def external_ports(self):
 714         if self.microwatt_compat:
 715             ports = [self.core.o.core_terminate_o,
 716                      self.ext_irq,
 717                      self.alt_reset, # not connected yet
 718                      self.nia, self.insn, self.nia_req, self.msr_o,
 719                      self.ldst_req, self.ldst_addr,
 720                      ClockSignal(),
 721                      ResetSignal(),
 722                     ]
 723             ports += list(self.dbg.dmi.ports())
 724             # for dbus/ibus microwatt, exclude err btw and cti
 725             for name, sig in self.imem.ibus.fields.items():
 726                 if name not in ['err', 'bte', 'cti', 'adr']:
 727                     ports.append(sig)
 728             for name, sig in self.core.l0.cmpi.wb_bus().fields.items():
 729                 if name not in ['err', 'bte', 'cti', 'adr']:
 730                     ports.append(sig)
 731             # microwatt non-compliant with wishbone
 732             ports.append(self.ibus_adr)
 733             ports.append(self.dbus_adr)
 734             return ports
 735
 736         ports = self.pc_i.ports()
 737         ports = self.msr_i.ports()
 738         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 739                   ]
 740
 741         if self.jtag_en:
 742             ports += list(self.jtag.external_ports())
 743         else:
 744             # don't add DMI if JTAG is enabled
 745             ports += list(self.dbg.dmi.ports())
 746
 747         ports += list(self.imem.ibus.fields.values())
 748         ports += list(self.core.l0.cmpi.wb_bus().fields.values())
 749
 750         if self.sram4x4k:
 751             for sram in self.sram4k:
 752                 ports += list(sram.bus.fields.values())
 753
 754         if self.xics:
 755             ports += list(self.xics_icp.bus.fields.values())
 756             ports += list(self.xics_ics.bus.fields.values())
 757             ports.append(self.int_level_i)
 758         else:
 759             ports.append(self.ext_irq)
 760
 761         if self.gpio:
 762             ports += list(self.simple_gpio.bus.fields.values())
 763             ports.append(self.gpio_o)
 764
 765         return ports
 766
 767     def ports(self):
 768         return list(self)
 769
 770
 771 class TestIssuerInternal(TestIssuerBase):
 772     """TestIssuer - reads instructions from TestMemory and issues them
 773
 774     efficiency and speed is not the main goal here: functional correctness
 775     and code clarity is.  optimisations (which almost 100% interfere with
 776     easy understanding) come later.
 777     """
 778
 779     def fetch_fsm(self, m, dbg, core, pc, msr, svstate, nia, is_svp64_mode,
 780                         fetch_pc_o_ready, fetch_pc_i_valid,
 781                         fetch_insn_o_valid, fetch_insn_i_ready):
 782         """fetch FSM
 783
 784         this FSM performs fetch of raw instruction data, partial-decodes
 785         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 786         read a 2nd 32-bit quantity if that occurs.
 787         """
 788         comb = m.d.comb
 789         sync = m.d.sync
 790         pdecode2 = self.pdecode2
 791         cur_state = self.cur_state
 792         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 793
 794         # also note instruction fetch failed
 795         if hasattr(core, "icache"):
 796             fetch_failed = core.icache.i_out.fetch_failed
 797             flush_needed = True
 798         else:
 799             fetch_failed = Const(0, 1)
 800             flush_needed = False
 801
 802         # set priv / virt mode on I-Cache, sigh
 803         if isinstance(self.imem, ICache):
 804             comb += self.imem.i_in.priv_mode.eq(~msr[MSR.PR])
 805             comb += self.imem.i_in.virt_mode.eq(msr[MSR.IR]) # Instr. Redir (VM)
 806
 807         with m.FSM(name='fetch_fsm'):
 808
 809             # waiting (zzz)
 810             with m.State("IDLE"):
 811                 # fetch allowed if not failed and stopped but not stepping
 812                 # (see dmi.py for how core_stop_o is generated)
 813                 with m.If(~fetch_failed & ~dbg.core_stop_o):
 814                     comb += fetch_pc_o_ready.eq(1)
 815                 with m.If(fetch_pc_i_valid & ~pdecode2.instr_fault
 816                           & ~dbg.core_stop_o):
 817                     # instruction allowed to go: start by reading the PC
 818                     # capture the PC and also drop it into Insn Memory
 819                     # we have joined a pair of combinatorial memory
 820                     # lookups together.  this is Generally Bad.
 821                     comb += self.imem.a_pc_i.eq(pc)
 822                     comb += self.imem.a_i_valid.eq(1)
 823                     comb += self.imem.f_i_valid.eq(1)
 824                     # transfer state to output
 825                     sync += cur_state.pc.eq(pc)
 826                     sync += cur_state.svstate.eq(svstate)  # and svstate
 827                     sync += cur_state.msr.eq(msr)  # and msr
 828
 829                     m.next = "INSN_READ"  # move to "wait for bus" phase
 830
 831             # dummy pause to find out why simulation is not keeping up
 832             with m.State("INSN_READ"):
 833                 # when using "single-step" mode, checking dbg.stopping_o
 834                 # prevents progress.  allow fetch to proceed once started
 835                 stopping = Const(0)
 836                 #if self.allow_overlap:
 837                 #    stopping = dbg.stopping_o
 838                 with m.If(stopping):
 839                     # stopping: jump back to idle
 840                     m.next = "IDLE"
 841                 with m.Else():
 842                     with m.If(self.imem.f_busy_o &
 843                               ~pdecode2.instr_fault):  # zzz...
 844                         # busy but not fetch failed: stay in wait-read
 845                         comb += self.imem.a_pc_i.eq(pc)
 846                         comb += self.imem.a_i_valid.eq(1)
 847                         comb += self.imem.f_i_valid.eq(1)
 848                     with m.Else():
 849                         # not busy (or fetch failed!): instruction fetched
 850                         # when fetch failed, the instruction gets ignored
 851                         # by the decoder
 852                         if hasattr(core, "icache"):
 853                             # blech, icache returns actual instruction
 854                             insn = self.imem.f_instr_o
 855                         else:
 856                             # but these return raw memory
 857                             insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 858                         if self.svp64_en:
 859                             svp64 = self.svp64
 860                             # decode the SVP64 prefix, if any
 861                             comb += svp64.raw_opcode_in.eq(insn)
 862                             comb += svp64.bigendian.eq(self.core_bigendian_i)
 863                             # pass the decoded prefix (if any) to PowerDecoder2
 864                             sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 865                             sync += pdecode2.is_svp64_mode.eq(is_svp64_mode)
 866                             # remember whether this is a prefixed instruction,
 867                             # so the FSM can readily loop when VL==0
 868                             sync += is_svp64_mode.eq(svp64.is_svp64_mode)
 869                             # calculate the address of the following instruction
 870                             insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 871                             sync += nia.eq(cur_state.pc + insn_size)
 872                             with m.If(~svp64.is_svp64_mode):
 873                                 # with no prefix, store the instruction
 874                                 # and hand it directly to the next FSM
 875                                 sync += dec_opcode_i.eq(insn)
 876                                 m.next = "INSN_READY"
 877                             with m.Else():
 878                                 # fetch the rest of the instruction from memory
 879                                 comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 880                                 comb += self.imem.a_i_valid.eq(1)
 881                                 comb += self.imem.f_i_valid.eq(1)
 882                                 m.next = "INSN_READ2"
 883                         else:
 884                             # not SVP64 - 32-bit only
 885                             sync += nia.eq(cur_state.pc + 4)
 886                             sync += dec_opcode_i.eq(insn)
 887                             if self.microwatt_compat:
 888                                 # for verilator debug purposes
 889                                 comb += self.insn.eq(insn)
 890                                 comb += self.nia.eq(cur_state.pc)
 891                                 comb += self.msr_o.eq(cur_state.msr)
 892                                 comb += self.nia_req.eq(1)
 893                             m.next = "INSN_READY"
 894
 895             with m.State("INSN_READ2"):
 896                 with m.If(self.imem.f_busy_o):  # zzz...
 897                     # busy: stay in wait-read
 898                     comb += self.imem.a_i_valid.eq(1)
 899                     comb += self.imem.f_i_valid.eq(1)
 900                 with m.Else():
 901                     # not busy: instruction fetched
 902                     if hasattr(core, "icache"):
 903                         # blech, icache returns actual instruction
 904                         insn = self.imem.f_instr_o
 905                     else:
 906                         insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 907                     sync += dec_opcode_i.eq(insn)
 908                     m.next = "INSN_READY"
 909                     # TODO: probably can start looking at pdecode2.rm_dec
 910                     # here or maybe even in INSN_READ state, if svp64_mode
 911                     # detected, in order to trigger - and wait for - the
 912                     # predicate reading.
 913                     if self.svp64_en:
 914                         pmode = pdecode2.rm_dec.predmode
 915                     """
 916                     if pmode != SVP64PredMode.ALWAYS.value:
 917                         fire predicate loading FSM and wait before
 918                         moving to INSN_READY
 919                     else:
 920                         sync += self.srcmask.eq(-1) # set to all 1s
 921                         sync += self.dstmask.eq(-1) # set to all 1s
 922                         m.next = "INSN_READY"
 923                     """
 924
 925             with m.State("INSN_READY"):
 926                 # hand over the instruction, to be decoded
 927                 comb += fetch_insn_o_valid.eq(1)
 928                 with m.If(fetch_insn_i_ready):
 929                     m.next = "IDLE"
 930
 931
 932     def fetch_predicate_fsm(self, m,
 933                             pred_insn_i_valid, pred_insn_o_ready,
 934                             pred_mask_o_valid, pred_mask_i_ready):
 935         """fetch_predicate_fsm - obtains (constructs in the case of CR)
 936            src/dest predicate masks
 937
 938         https://bugs.libre-soc.org/show_bug.cgi?id=617
 939         the predicates can be read here, by using IntRegs r_ports['pred']
 940         or CRRegs r_ports['pred'].  in the case of CRs it will have to
 941         be done through multiple reads, extracting one relevant at a time.
 942         later, a faster way would be to use the 32-bit-wide CR port but
 943         this is more complex decoding, here.  equivalent code used in
 944         ISACaller is "from openpower.decoder.isa.caller import get_predcr"
 945
 946         note: this ENTIRE FSM is not to be called when svp64 is disabled
 947         """
 948         comb = m.d.comb
 949         sync = m.d.sync
 950         pdecode2 = self.pdecode2
 951         rm_dec = pdecode2.rm_dec  # SVP64RMModeDecode
 952         predmode = rm_dec.predmode
 953         srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
 954         cr_pred, int_pred = self.cr_pred, self.int_pred   # read regfiles
 955         # get src/dst step, so we can skip already used mask bits
 956         cur_state = self.cur_state
 957         srcstep = cur_state.svstate.srcstep
 958         dststep = cur_state.svstate.dststep
 959         cur_vl = cur_state.svstate.vl
 960
 961         # decode predicates
 962         sregread, sinvert, sunary, sall1s = get_predint(m, srcpred, 's')
 963         dregread, dinvert, dunary, dall1s = get_predint(m, dstpred, 'd')
 964         sidx, scrinvert = get_predcr(m, srcpred, 's')
 965         didx, dcrinvert = get_predcr(m, dstpred, 'd')
 966
 967         # store fetched masks, for either intpred or crpred
 968         # when src/dst step is not zero, the skipped mask bits need to be
 969         # shifted-out, before actually storing them in src/dest mask
 970         new_srcmask = Signal(64, reset_less=True)
 971         new_dstmask = Signal(64, reset_less=True)
 972
 973         with m.FSM(name="fetch_predicate"):
 974
 975             with m.State("FETCH_PRED_IDLE"):
 976                 comb += pred_insn_o_ready.eq(1)
 977                 with m.If(pred_insn_i_valid):
 978                     with m.If(predmode == SVP64PredMode.INT):
 979                         # skip fetching destination mask register, when zero
 980                         with m.If(dall1s):
 981                             sync += new_dstmask.eq(-1)
 982                             # directly go to fetch source mask register
 983                             # guaranteed not to be zero (otherwise predmode
 984                             # would be SVP64PredMode.ALWAYS, not INT)
 985                             comb += int_pred.addr.eq(sregread)
 986                             comb += int_pred.ren.eq(1)
 987                             m.next = "INT_SRC_READ"
 988                         # fetch destination predicate register
 989                         with m.Else():
 990                             comb += int_pred.addr.eq(dregread)
 991                             comb += int_pred.ren.eq(1)
 992                             m.next = "INT_DST_READ"
 993                     with m.Elif(predmode == SVP64PredMode.CR):
 994                         # go fetch masks from the CR register file
 995                         sync += new_srcmask.eq(0)
 996                         sync += new_dstmask.eq(0)
 997                         m.next = "CR_READ"
 998                     with m.Else():
 999                         sync += self.srcmask.eq(-1)
1000                         sync += self.dstmask.eq(-1)
1001                         m.next = "FETCH_PRED_DONE"
1002
1003             with m.State("INT_DST_READ"):
1004                 # store destination mask
1005                 inv = Repl(dinvert, 64)
1006                 with m.If(dunary):
1007                     # set selected mask bit for 1<<r3 mode
1008                     dst_shift = Signal(range(64))
1009                     comb += dst_shift.eq(self.int_pred.o_data & 0b111111)
1010                     sync += new_dstmask.eq(1 << dst_shift)
1011                 with m.Else():
1012                     # invert mask if requested
1013                     sync += new_dstmask.eq(self.int_pred.o_data ^ inv)
1014                 # skip fetching source mask register, when zero
1015                 with m.If(sall1s):
1016                     sync += new_srcmask.eq(-1)
1017                     m.next = "FETCH_PRED_SHIFT_MASK"
1018                 # fetch source predicate register
1019                 with m.Else():
1020                     comb += int_pred.addr.eq(sregread)
1021                     comb += int_pred.ren.eq(1)
1022                     m.next = "INT_SRC_READ"
1023
1024             with m.State("INT_SRC_READ"):
1025                 # store source mask
1026                 inv = Repl(sinvert, 64)
1027                 with m.If(sunary):
1028                     # set selected mask bit for 1<<r3 mode
1029                     src_shift = Signal(range(64))
1030                     comb += src_shift.eq(self.int_pred.o_data & 0b111111)
1031                     sync += new_srcmask.eq(1 << src_shift)
1032                 with m.Else():
1033                     # invert mask if requested
1034                     sync += new_srcmask.eq(self.int_pred.o_data ^ inv)
1035                 m.next = "FETCH_PRED_SHIFT_MASK"
1036
1037             # fetch masks from the CR register file
1038             # implements the following loop:
1039             # idx, inv = get_predcr(mask)
1040             # mask = 0
1041             # for cr_idx in range(vl):
1042             #     cr = crl[cr_idx + SVP64CROffs.CRPred]  # takes one cycle
1043             #     if cr[idx] ^ inv:
1044             #         mask |= 1 << cr_idx
1045             # return mask
1046             with m.State("CR_READ"):
1047                 # CR index to be read, which will be ready by the next cycle
1048                 cr_idx = Signal.like(cur_vl, reset_less=True)
1049                 # submit the read operation to the regfile
1050                 with m.If(cr_idx != cur_vl):
1051                     # the CR read port is unary ...
1052                     # ren = 1 << cr_idx
1053                     # ... in MSB0 convention ...
1054                     # ren = 1 << (7 - cr_idx)
1055                     # ... and with an offset:
1056                     # ren = 1 << (7 - off - cr_idx)
1057                     idx = SVP64CROffs.CRPred + cr_idx
1058                     comb += cr_pred.ren.eq(1 << (7 - idx))
1059                     # signal data valid in the next cycle
1060                     cr_read = Signal(reset_less=True)
1061                     sync += cr_read.eq(1)
1062                     # load the next index
1063                     sync += cr_idx.eq(cr_idx + 1)
1064                 with m.Else():
1065                     # exit on loop end
1066                     sync += cr_read.eq(0)
1067                     sync += cr_idx.eq(0)
1068                     m.next = "FETCH_PRED_SHIFT_MASK"
1069                 with m.If(cr_read):
1070                     # compensate for the one cycle delay on the regfile
1071                     cur_cr_idx = Signal.like(cur_vl)
1072                     comb += cur_cr_idx.eq(cr_idx - 1)
1073                     # read the CR field, select the appropriate bit
1074                     cr_field = Signal(4)
1075                     scr_bit = Signal()
1076                     dcr_bit = Signal()
1077                     comb += cr_field.eq(cr_pred.o_data)
1078                     comb += scr_bit.eq(cr_field.bit_select(sidx, 1)
1079                                        ^ scrinvert)
1080                     comb += dcr_bit.eq(cr_field.bit_select(didx, 1)
1081                                        ^ dcrinvert)
1082                     # set the corresponding mask bit
1083                     bit_to_set = Signal.like(self.srcmask)
1084                     comb += bit_to_set.eq(1 << cur_cr_idx)
1085                     with m.If(scr_bit):
1086                         sync += new_srcmask.eq(new_srcmask | bit_to_set)
1087                     with m.If(dcr_bit):
1088                         sync += new_dstmask.eq(new_dstmask | bit_to_set)
1089
1090             with m.State("FETCH_PRED_SHIFT_MASK"):
1091                 # shift-out skipped mask bits
1092                 sync += self.srcmask.eq(new_srcmask >> srcstep)
1093                 sync += self.dstmask.eq(new_dstmask >> dststep)
1094                 m.next = "FETCH_PRED_DONE"
1095
1096             with m.State("FETCH_PRED_DONE"):
1097                 comb += pred_mask_o_valid.eq(1)
1098                 with m.If(pred_mask_i_ready):
1099                     m.next = "FETCH_PRED_IDLE"
1100
1101     def issue_fsm(self, m, core, nia,
1102                   dbg, core_rst, is_svp64_mode,
1103                   fetch_pc_o_ready, fetch_pc_i_valid,
1104                   fetch_insn_o_valid, fetch_insn_i_ready,
1105                   pred_insn_i_valid, pred_insn_o_ready,
1106                   pred_mask_o_valid, pred_mask_i_ready,
1107                   exec_insn_i_valid, exec_insn_o_ready,
1108                   exec_pc_o_valid, exec_pc_i_ready):
1109         """issue FSM
1110
1111         decode / issue FSM.  this interacts with the "fetch" FSM
1112         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
1113         (outgoing). also interacts with the "execute" FSM
1114         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
1115         (incoming).
1116         SVP64 RM prefixes have already been set up by the
1117         "fetch" phase, so execute is fairly straightforward.
1118         """
1119
1120         comb = m.d.comb
1121         sync = m.d.sync
1122         pdecode2 = self.pdecode2
1123         cur_state = self.cur_state
1124         new_svstate = self.new_svstate
1125
1126         # temporaries
1127         dec_opcode_i = pdecode2.dec.raw_opcode_in  # raw opcode
1128
1129         # for updating svstate (things like srcstep etc.)
1130         comb += new_svstate.eq(cur_state.svstate)
1131
1132         # precalculate srcstep+1 and dststep+1
1133         cur_srcstep = cur_state.svstate.srcstep
1134         cur_dststep = cur_state.svstate.dststep
1135         next_srcstep = Signal.like(cur_srcstep)
1136         next_dststep = Signal.like(cur_dststep)
1137         comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
1138         comb += next_dststep.eq(cur_state.svstate.dststep+1)
1139
1140         # note if an exception happened.  in a pipelined or OoO design
1141         # this needs to be accompanied by "shadowing" (or stalling)
1142         exc_happened = self.core.o.exc_happened
1143         # also note instruction fetch failed
1144         if hasattr(core, "icache"):
1145             fetch_failed = core.icache.i_out.fetch_failed
1146             flush_needed = True
1147             # set to fault in decoder
1148             # update (highest priority) instruction fault
1149             rising_fetch_failed = rising_edge(m, fetch_failed)
1150             with m.If(rising_fetch_failed):
1151                 sync += pdecode2.instr_fault.eq(1)
1152         else:
1153             fetch_failed = Const(0, 1)
1154             flush_needed = False
1155
1156         with m.FSM(name="issue_fsm"):
1157
1158             # sync with the "fetch" phase which is reading the instruction
1159             # at this point, there is no instruction running, that
1160             # could inadvertently update the PC.
1161             with m.State("ISSUE_START"):
1162                 # reset instruction fault
1163                 sync += pdecode2.instr_fault.eq(0)
1164                 # wait on "core stop" release, before next fetch
1165                 # need to do this here, in case we are in a VL==0 loop
1166                 with m.If(~dbg.core_stop_o & ~core_rst):
1167                     comb += fetch_pc_i_valid.eq(1)  # tell fetch to start
1168                     with m.If(fetch_pc_o_ready):   # fetch acknowledged us
1169                         m.next = "INSN_WAIT"
1170                 with m.Else():
1171                     # tell core it's stopped, and acknowledge debug handshake
1172                     comb += dbg.core_stopped_i.eq(1)
1173                     # while stopped, allow updating SVSTATE
1174                     with m.If(self.svstate_i.ok):
1175                         comb += new_svstate.eq(self.svstate_i.data)
1176                         comb += self.update_svstate.eq(1)
1177                         sync += self.sv_changed.eq(1)
1178
1179             # wait for an instruction to arrive from Fetch
1180             with m.State("INSN_WAIT"):
1181                 # when using "single-step" mode, checking dbg.stopping_o
1182                 # prevents progress.  allow issue to proceed once started
1183                 stopping = Const(0)
1184                 #if self.allow_overlap:
1185                 #    stopping = dbg.stopping_o
1186                 with m.If(stopping):
1187                     # stopping: jump back to idle
1188                     m.next = "ISSUE_START"
1189                     if flush_needed:
1190                         # request the icache to stop asserting "failed"
1191                         comb += core.icache.flush_in.eq(1)
1192                     # stop instruction fault
1193                     sync += pdecode2.instr_fault.eq(0)
1194                 with m.Else():
1195                     comb += fetch_insn_i_ready.eq(1)
1196                     with m.If(fetch_insn_o_valid):
1197                         # loop into ISSUE_START if it's a SVP64 instruction
1198                         # and VL == 0.  this because VL==0 is a for-loop
1199                         # from 0 to 0 i.e. always, always a NOP.
1200                         cur_vl = cur_state.svstate.vl
1201                         with m.If(is_svp64_mode & (cur_vl == 0)):
1202                             # update the PC before fetching the next instruction
1203                             # since we are in a VL==0 loop, no instruction was
1204                             # executed that we could be overwriting
1205                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
1206                             comb += self.state_w_pc.i_data.eq(nia)
1207                             comb += self.insn_done.eq(1)
1208                             m.next = "ISSUE_START"
1209                         with m.Else():
1210                             if self.svp64_en:
1211                                 m.next = "PRED_START"  # fetching predicate
1212                             else:
1213                                 m.next = "DECODE_SV"  # skip predication
1214
1215             with m.State("PRED_START"):
1216                 comb += pred_insn_i_valid.eq(1)  # tell fetch_pred to start
1217                 with m.If(pred_insn_o_ready):  # fetch_pred acknowledged us
1218                     m.next = "MASK_WAIT"
1219
1220             with m.State("MASK_WAIT"):
1221                 comb += pred_mask_i_ready.eq(1)  # ready to receive the masks
1222                 with m.If(pred_mask_o_valid):  # predication masks are ready
1223                     m.next = "PRED_SKIP"
1224
1225             # skip zeros in predicate
1226             with m.State("PRED_SKIP"):
1227                 with m.If(~is_svp64_mode):
1228                     m.next = "DECODE_SV"  # nothing to do
1229                 with m.Else():
1230                     if self.svp64_en:
1231                         pred_src_zero = pdecode2.rm_dec.pred_sz
1232                         pred_dst_zero = pdecode2.rm_dec.pred_dz
1233
1234                         # new srcstep, after skipping zeros
1235                         skip_srcstep = Signal.like(cur_srcstep)
1236                         # value to be added to the current srcstep
1237                         src_delta = Signal.like(cur_srcstep)
1238                         # add leading zeros to srcstep, if not in zero mode
1239                         with m.If(~pred_src_zero):
1240                             # priority encoder (count leading zeros)
1241                             # append guard bit, in case the mask is all zeros
1242                             pri_enc_src = PriorityEncoder(65)
1243                             m.submodules.pri_enc_src = pri_enc_src
1244                             comb += pri_enc_src.i.eq(Cat(self.srcmask,
1245                                                          Const(1, 1)))
1246                             comb += src_delta.eq(pri_enc_src.o)
1247                         # apply delta to srcstep
1248                         comb += skip_srcstep.eq(cur_srcstep + src_delta)
1249                         # shift-out all leading zeros from the mask
1250                         # plus the leading "one" bit
1251                         # TODO count leading zeros and shift-out the zero
1252                         #      bits, in the same step, in hardware
1253                         sync += self.srcmask.eq(self.srcmask >> (src_delta+1))
1254
1255                         # same as above, but for dststep
1256                         skip_dststep = Signal.like(cur_dststep)
1257                         dst_delta = Signal.like(cur_dststep)
1258                         with m.If(~pred_dst_zero):
1259                             pri_enc_dst = PriorityEncoder(65)
1260                             m.submodules.pri_enc_dst = pri_enc_dst
1261                             comb += pri_enc_dst.i.eq(Cat(self.dstmask,
1262                                                          Const(1, 1)))
1263                             comb += dst_delta.eq(pri_enc_dst.o)
1264                         comb += skip_dststep.eq(cur_dststep + dst_delta)
1265                         sync += self.dstmask.eq(self.dstmask >> (dst_delta+1))
1266
1267                         # TODO: initialize mask[VL]=1 to avoid passing past VL
1268                         with m.If((skip_srcstep >= cur_vl) |
1269                                   (skip_dststep >= cur_vl)):
1270                             # end of VL loop. Update PC and reset src/dst step
1271                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
1272                             comb += self.state_w_pc.i_data.eq(nia)
1273                             comb += new_svstate.srcstep.eq(0)
1274                             comb += new_svstate.dststep.eq(0)
1275                             comb += self.update_svstate.eq(1)
1276                             # synchronize with the simulator
1277                             comb += self.insn_done.eq(1)
1278                             # go back to Issue
1279                             m.next = "ISSUE_START"
1280                         with m.Else():
1281                             # update new src/dst step
1282                             comb += new_svstate.srcstep.eq(skip_srcstep)
1283                             comb += new_svstate.dststep.eq(skip_dststep)
1284                             comb += self.update_svstate.eq(1)
1285                             # proceed to Decode
1286                             m.next = "DECODE_SV"
1287
1288                         # pass predicate mask bits through to satellite decoders
1289                         # TODO: for SIMD this will be *multiple* bits
1290                         sync += core.i.sv_pred_sm.eq(self.srcmask[0])
1291                         sync += core.i.sv_pred_dm.eq(self.dstmask[0])
1292
1293             # after src/dst step have been updated, we are ready
1294             # to decode the instruction
1295             with m.State("DECODE_SV"):
1296                 # decode the instruction
1297                 with m.If(~fetch_failed):
1298                     sync += pdecode2.instr_fault.eq(0)
1299                 sync += core.i.e.eq(pdecode2.e)
1300                 sync += core.i.state.eq(cur_state)
1301                 sync += core.i.raw_insn_i.eq(dec_opcode_i)
1302                 sync += core.i.bigendian_i.eq(self.core_bigendian_i)
1303                 if self.svp64_en:
1304                     sync += core.i.sv_rm.eq(pdecode2.sv_rm)
1305                     # set RA_OR_ZERO detection in satellite decoders
1306                     sync += core.i.sv_a_nz.eq(pdecode2.sv_a_nz)
1307                     # and svp64 detection
1308                     sync += core.i.is_svp64_mode.eq(is_svp64_mode)
1309                     # and svp64 bit-rev'd ldst mode
1310                     ldst_dec = pdecode2.use_svp64_ldst_dec
1311                     sync += core.i.use_svp64_ldst_dec.eq(ldst_dec)
1312                 # after decoding, reset any previous exception condition,
1313                 # allowing it to be set again during the next execution
1314                 sync += pdecode2.ldst_exc.eq(0)
1315
1316                 m.next = "INSN_EXECUTE"  # move to "execute"
1317
1318             # handshake with execution FSM, move to "wait" once acknowledged
1319             with m.State("INSN_EXECUTE"):
1320                 # when using "single-step" mode, checking dbg.stopping_o
1321                 # prevents progress.  allow execute to proceed once started
1322                 stopping = Const(0)
1323                 #if self.allow_overlap:
1324                 #    stopping = dbg.stopping_o
1325                 with m.If(stopping):
1326                     # stopping: jump back to idle
1327                     m.next = "ISSUE_START"
1328                     if flush_needed:
1329                         # request the icache to stop asserting "failed"
1330                         comb += core.icache.flush_in.eq(1)
1331                     # stop instruction fault
1332                     sync += pdecode2.instr_fault.eq(0)
1333                 with m.Else():
1334                     comb += exec_insn_i_valid.eq(1)  # trigger execute
1335                     with m.If(exec_insn_o_ready):   # execute acknowledged us
1336                         m.next = "EXECUTE_WAIT"
1337
1338             with m.State("EXECUTE_WAIT"):
1339                 comb += exec_pc_i_ready.eq(1)
1340                 # see https://bugs.libre-soc.org/show_bug.cgi?id=636
1341                 # the exception info needs to be blatted into
1342                 # pdecode.ldst_exc, and the instruction "re-run".
1343                 # when ldst_exc.happened is set, the PowerDecoder2
1344                 # reacts very differently: it re-writes the instruction
1345                 # with a "trap" (calls PowerDecoder2.trap()) which
1346                 # will *overwrite* whatever was requested and jump the
1347                 # PC to the exception address, as well as alter MSR.
1348                 # nothing else needs to be done other than to note
1349                 # the change of PC and MSR (and, later, SVSTATE)
1350                 with m.If(exc_happened):
1351                     mmu = core.fus.get_exc("mmu0")
1352                     ldst = core.fus.get_exc("ldst0")
1353                     if mmu is not None:
1354                         with m.If(fetch_failed):
1355                             # instruction fetch: exception is from MMU
1356                             # reset instr_fault (highest priority)
1357                             sync += pdecode2.ldst_exc.eq(mmu)
1358                             sync += pdecode2.instr_fault.eq(0)
1359                             if flush_needed:
1360                                 # request icache to stop asserting "failed"
1361                                 comb += core.icache.flush_in.eq(1)
1362                     with m.If(~fetch_failed):
1363                         # otherwise assume it was a LDST exception
1364                         sync += pdecode2.ldst_exc.eq(ldst)
1365
1366                 with m.If(exec_pc_o_valid):
1367
1368                     # was this the last loop iteration?
1369                     is_last = Signal()
1370                     cur_vl = cur_state.svstate.vl
1371                     comb += is_last.eq(next_srcstep == cur_vl)
1372
1373                     with m.If(pdecode2.instr_fault):
1374                         # reset instruction fault, try again
1375                         sync += pdecode2.instr_fault.eq(0)
1376                         m.next = "ISSUE_START"
1377
1378                     # return directly to Decode if Execute generated an
1379                     # exception.
1380                     with m.Elif(pdecode2.ldst_exc.happened):
1381                         m.next = "DECODE_SV"
1382
1383                     # if MSR, PC or SVSTATE were changed by the previous
1384                     # instruction, go directly back to Fetch, without
1385                     # updating either MSR PC or SVSTATE
1386                     with m.Elif(self.msr_changed | self.pc_changed |
1387                                 self.sv_changed):
1388                         m.next = "ISSUE_START"
1389
1390                     # also return to Fetch, when no output was a vector
1391                     # (regardless of SRCSTEP and VL), or when the last
1392                     # instruction was really the last one of the VL loop
1393                     with m.Elif((~pdecode2.loop_continue) | is_last):
1394                         # before going back to fetch, update the PC state
1395                         # register with the NIA.
1396                         # ok here we are not reading the branch unit.
1397                         # TODO: this just blithely overwrites whatever
1398                         #       pipeline updated the PC
1399                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
1400                         comb += self.state_w_pc.i_data.eq(nia)
1401                         # reset SRCSTEP before returning to Fetch
1402                         if self.svp64_en:
1403                             with m.If(pdecode2.loop_continue):
1404                                 comb += new_svstate.srcstep.eq(0)
1405                                 comb += new_svstate.dststep.eq(0)
1406                                 comb += self.update_svstate.eq(1)
1407                         else:
1408                             comb += new_svstate.srcstep.eq(0)
1409                             comb += new_svstate.dststep.eq(0)
1410                             comb += self.update_svstate.eq(1)
1411                         m.next = "ISSUE_START"
1412
1413                     # returning to Execute? then, first update SRCSTEP
1414                     with m.Else():
1415                         comb += new_svstate.srcstep.eq(next_srcstep)
1416                         comb += new_svstate.dststep.eq(next_dststep)
1417                         comb += self.update_svstate.eq(1)
1418                         # return to mask skip loop
1419                         m.next = "PRED_SKIP"
1420
1421
1422         # check if svstate needs updating: if so, write it to State Regfile
1423         with m.If(self.update_svstate):
1424             sync += cur_state.svstate.eq(self.new_svstate)  # for next clock
1425
1426     def execute_fsm(self, m, core,
1427                     exec_insn_i_valid, exec_insn_o_ready,
1428                     exec_pc_o_valid, exec_pc_i_ready):
1429         """execute FSM
1430
1431         execute FSM. this interacts with the "issue" FSM
1432         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
1433         (outgoing). SVP64 RM prefixes have already been set up by the
1434         "issue" phase, so execute is fairly straightforward.
1435         """
1436
1437         comb = m.d.comb
1438         sync = m.d.sync
1439         dbg = self.dbg
1440         pdecode2 = self.pdecode2
1441
1442         # temporaries
1443         core_busy_o = core.n.o_data.busy_o  # core is busy
1444         core_ivalid_i = core.p.i_valid              # instruction is valid
1445
1446         if hasattr(core, "icache"):
1447             fetch_failed = core.icache.i_out.fetch_failed
1448         else:
1449             fetch_failed = Const(0, 1)
1450
1451         with m.FSM(name="exec_fsm"):
1452
1453             # waiting for instruction bus (stays there until not busy)
1454             with m.State("INSN_START"):
1455                 comb += exec_insn_o_ready.eq(1)
1456                 with m.If(exec_insn_i_valid):
1457                     comb += core_ivalid_i.eq(1)  # instruction is valid/issued
1458                     sync += self.sv_changed.eq(0)
1459                     sync += self.pc_changed.eq(0)
1460                     sync += self.msr_changed.eq(0)
1461                     with m.If(core.p.o_ready):  # only move if accepted
1462                         m.next = "INSN_ACTIVE"  # move to "wait completion"
1463
1464             # instruction started: must wait till it finishes
1465             with m.State("INSN_ACTIVE"):
1466                 # note changes to MSR, PC and SVSTATE
1467                 # XXX oops, really must monitor *all* State Regfile write
1468                 # ports looking for changes!
1469                 with m.If(self.state_nia.wen & (1 << StateRegs.SVSTATE)):
1470                     sync += self.sv_changed.eq(1)
1471                 with m.If(self.state_nia.wen & (1 << StateRegs.MSR)):
1472                     sync += self.msr_changed.eq(1)
1473                 with m.If(self.state_nia.wen & (1 << StateRegs.PC)):
1474                     sync += self.pc_changed.eq(1)
1475                 with m.If(~core_busy_o):  # instruction done!
1476                     comb += exec_pc_o_valid.eq(1)
1477                     with m.If(exec_pc_i_ready):
1478                         # when finished, indicate "done".
1479                         # however, if there was an exception, the instruction
1480                         # is *not* yet done.  this is an implementation
1481                         # detail: we choose to implement exceptions by
1482                         # taking the exception information from the LDST
1483                         # unit, putting that *back* into the PowerDecoder2,
1484                         # and *re-running the entire instruction*.
1485                         # if we erroneously indicate "done" here, it is as if
1486                         # there were *TWO* instructions:
1487                         # 1) the failed LDST 2) a TRAP.
1488                         with m.If(~pdecode2.ldst_exc.happened &
1489                                    ~pdecode2.instr_fault):
1490                             comb += self.insn_done.eq(1)
1491                         m.next = "INSN_START"  # back to fetch
1492                 # terminate returns directly to INSN_START
1493                 with m.If(dbg.terminate_i):
1494                     # comb += self.insn_done.eq(1) - no because it's not
1495                     m.next = "INSN_START"  # back to fetch
1496
1497     def elaborate(self, platform):
1498         m = super().elaborate(platform)
1499         # convenience
1500         comb, sync = m.d.comb, m.d.sync
1501         cur_state = self.cur_state
1502         pdecode2 = self.pdecode2
1503         dbg = self.dbg
1504         core = self.core
1505
1506         # set up peripherals and core
1507         core_rst = self.core_rst
1508
1509         # indicate to outside world if any FU is still executing
1510         comb += self.any_busy.eq(core.n.o_data.any_busy_o)  # any FU executing
1511
1512         # address of the next instruction, in the absence of a branch
1513         # depends on the instruction size
1514         nia = Signal(64)
1515
1516         # connect up debug signals
1517         with m.If(core.o.core_terminate_o):
1518             comb += dbg.terminate_i.eq(1)
1519
1520         # pass the prefix mode from Fetch to Issue, so the latter can loop
1521         # on VL==0
1522         is_svp64_mode = Signal()
1523
1524         # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
1525         # issue, decode/execute, now joined by "Predicate fetch/calculate".
1526         # these are the handshake signals between each
1527
1528         # fetch FSM can run as soon as the PC is valid
1529         fetch_pc_i_valid = Signal()  # Execute tells Fetch "start next read"
1530         fetch_pc_o_ready = Signal()  # Fetch Tells SVSTATE "proceed"
1531
1532         # fetch FSM hands over the instruction to be decoded / issued
1533         fetch_insn_o_valid = Signal()
1534         fetch_insn_i_ready = Signal()
1535
1536         # predicate fetch FSM decodes and fetches the predicate
1537         pred_insn_i_valid = Signal()
1538         pred_insn_o_ready = Signal()
1539
1540         # predicate fetch FSM delivers the masks
1541         pred_mask_o_valid = Signal()
1542         pred_mask_i_ready = Signal()
1543
1544         # issue FSM delivers the instruction to the be executed
1545         exec_insn_i_valid = Signal()
1546         exec_insn_o_ready = Signal()
1547
1548         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
1549         exec_pc_o_valid = Signal()
1550         exec_pc_i_ready = Signal()
1551
1552         # the FSMs here are perhaps unusual in that they detect conditions
1553         # then "hold" information, combinatorially, for the core
1554         # (as opposed to using sync - which would be on a clock's delay)
1555         # this includes the actual opcode, valid flags and so on.
1556
1557         # Fetch, then predicate fetch, then Issue, then Execute.
1558         # Issue is where the VL for-loop # lives.  the ready/valid
1559         # signalling is used to communicate between the four.
1560
1561         self.fetch_fsm(m, dbg, core, dbg.state.pc, dbg.state.msr,
1562                        dbg.state.svstate, nia, is_svp64_mode,
1563                        fetch_pc_o_ready, fetch_pc_i_valid,
1564                        fetch_insn_o_valid, fetch_insn_i_ready)
1565
1566         self.issue_fsm(m, core, nia,
1567                        dbg, core_rst, is_svp64_mode,
1568                        fetch_pc_o_ready, fetch_pc_i_valid,
1569                        fetch_insn_o_valid, fetch_insn_i_ready,
1570                        pred_insn_i_valid, pred_insn_o_ready,
1571                        pred_mask_o_valid, pred_mask_i_ready,
1572                        exec_insn_i_valid, exec_insn_o_ready,
1573                        exec_pc_o_valid, exec_pc_i_ready)
1574
1575         if self.svp64_en:
1576             self.fetch_predicate_fsm(m,
1577                                      pred_insn_i_valid, pred_insn_o_ready,
1578                                      pred_mask_o_valid, pred_mask_i_ready)
1579
1580         self.execute_fsm(m, core,
1581                          exec_insn_i_valid, exec_insn_o_ready,
1582                          exec_pc_o_valid, exec_pc_i_ready)
1583
1584         # whatever was done above, over-ride it if core reset is held
1585         with m.If(core_rst):
1586             sync += nia.eq(0)
1587
1588         return m
1589
1590
1591 class TestIssuer(Elaboratable):
1592     def __init__(self, pspec):
1593         self.ti = TestIssuerInternal(pspec)
1594         self.pll = DummyPLL(instance=True)
1595
1596         self.dbg_rst_i = Signal(reset_less=True)
1597
1598         # PLL direct clock or not
1599         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
1600         if self.pll_en:
1601             self.pll_test_o = Signal(reset_less=True)
1602             self.pll_vco_o = Signal(reset_less=True)
1603             self.clk_sel_i = Signal(2, reset_less=True)
1604             self.ref_clk = ClockSignal()  # can't rename it but that's ok
1605             self.pllclk_clk = ClockSignal("pllclk")
1606
1607     def elaborate(self, platform):
1608         m = Module()
1609         comb = m.d.comb
1610
1611         # TestIssuer nominally runs at main clock, actually it is
1612         # all combinatorial internally except for coresync'd components
1613         m.submodules.ti = ti = self.ti
1614
1615         if self.pll_en:
1616             # ClockSelect runs at PLL output internal clock rate
1617             m.submodules.wrappll = pll = self.pll
1618
1619             # add clock domains from PLL
1620             cd_pll = ClockDomain("pllclk")
1621             m.domains += cd_pll
1622
1623             # PLL clock established.  has the side-effect of running clklsel
1624             # at the PLL's speed (see DomainRenamer("pllclk") above)
1625             pllclk = self.pllclk_clk
1626             comb += pllclk.eq(pll.clk_pll_o)
1627
1628             # wire up external 24mhz to PLL
1629             #comb += pll.clk_24_i.eq(self.ref_clk)
1630             # output 18 mhz PLL test signal, and analog oscillator out
1631             comb += self.pll_test_o.eq(pll.pll_test_o)
1632             comb += self.pll_vco_o.eq(pll.pll_vco_o)
1633
1634             # input to pll clock selection
1635             comb += pll.clk_sel_i.eq(self.clk_sel_i)
1636
1637             # now wire up ResetSignals.  don't mind them being in this domain
1638             pll_rst = ResetSignal("pllclk")
1639             comb += pll_rst.eq(ResetSignal())
1640
1641         # internal clock is set to selector clock-out.  has the side-effect of
1642         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1643         # debug clock runs at coresync internal clock
1644         if self.ti.dbg_domain != 'sync':
1645             cd_dbgsync = ClockDomain("dbgsync")
1646         intclk = ClockSignal(self.ti.core_domain)
1647         dbgclk = ClockSignal(self.ti.dbg_domain)
1648         # XXX BYPASS PLL XXX
1649         # XXX BYPASS PLL XXX
1650         # XXX BYPASS PLL XXX
1651         if self.pll_en:
1652             comb += intclk.eq(self.ref_clk)
1653             assert self.ti.core_domain != 'sync', \
1654                 "cannot set core_domain to sync and use pll at the same time"
1655         else:
1656             if self.ti.core_domain != 'sync':
1657                 comb += intclk.eq(ClockSignal())
1658         if self.ti.dbg_domain != 'sync':
1659             dbgclk = ClockSignal(self.ti.dbg_domain)
1660             comb += dbgclk.eq(intclk)
1661         comb += self.ti.dbg_rst_i.eq(self.dbg_rst_i)
1662
1663         return m
1664
1665     def ports(self):
1666         return list(self.ti.ports()) + list(self.pll.ports()) + \
1667             [ClockSignal(), ResetSignal()]
1668
1669     def external_ports(self):
1670         ports = self.ti.external_ports()
1671         ports.append(ClockSignal())
1672         ports.append(ResetSignal())
1673         if self.pll_en:
1674             ports.append(self.clk_sel_i)
1675             ports.append(self.pll.clk_24_i)
1676             ports.append(self.pll_test_o)
1677             ports.append(self.pll_vco_o)
1678             ports.append(self.pllclk_clk)
1679             ports.append(self.ref_clk)
1680         return ports
1681
1682
1683 if __name__ == '__main__':
1684     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1685              'spr': 1,
1686              'div': 1,
1687              'mul': 1,
1688              'shiftrot': 1
1689              }
1690     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
1691                          imem_ifacetype='bare_wb',
1692                          addr_wid=64,
1693                          mask_wid=8,
1694                          reg_wid=64,
1695                          units=units)
1696     dut = TestIssuer(pspec)
1697     vl = main(dut, ports=dut.ports(), name="test_issuer")
1698
1699     if len(sys.argv) == 1:
1700         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
1701         with open("test_issuer.il", "w") as f:
1702             f.write(vl)