src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # JTAG interface.  add this right at the start because if it's
  64         # added it *modifies* the pspec, by adding enable/disable signals
  65         # for parts of the rest of the core
  66         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  67         if self.jtag_en:
  68             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  69                       'pwm', 'sd0', 'sdr'}
  70             self.jtag = JTAG(get_pinspecs(subset=subset))
  71             # add signals to pspec to enable/disable icache and dcache
  72             # (or data and intstruction wishbone if icache/dcache not included)
  73             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  74             # TODO: do we actually care if these are not domain-synchronised?
  75             # honestly probably not.
  76             pspec.wb_icache_en = self.jtag.wb_icache_en
  77             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  78
  79         # add 4k sram blocks?
  80         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  81                          pspec.sram4x4kblock == True)
  82         if self.sram4x4k:
  83             self.sram4k = []
  84             for i in range(4):
  85                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i))
  86
  87         # add interrupt controller?
  88         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  89         if self.xics:
  90             self.xics_icp = XICS_ICP()
  91             self.xics_ics = XICS_ICS()
  92             self.int_level_i = self.xics_ics.int_level_i
  93
  94         # add GPIO peripheral?
  95         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
  96         if self.gpio:
  97             self.simple_gpio = SimpleGPIO()
  98             self.gpio_o = self.simple_gpio.gpio_o
  99
 100         # main instruction core25
 101         self.core = core = NonProductionCore(pspec)
 102
 103         # instruction decoder.  goes into Trap Record
 104         pdecode = create_pdecode()
 105         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 106         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 107                                      opkls=IssuerDecode2ToOperand)
 108         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 109
 110         # Test Instruction memory
 111         self.imem = ConfigFetchUnit(pspec).fu
 112         # one-row cache of instruction read
 113         self.iline = Signal(64) # one instruction line
 114         self.iprev_adr = Signal(64) # previous address: if different, do read
 115
 116         # DMI interface
 117         self.dbg = CoreDebug()
 118
 119         # instruction go/monitor
 120         self.pc_o = Signal(64, reset_less=True)
 121         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 122         self.core_bigendian_i = Signal()
 123         self.busy_o = Signal(reset_less=True)
 124         self.memerr_o = Signal(reset_less=True)
 125
 126         # STATE regfile read /write ports for PC, MSR, SVSTATE
 127         staterf = self.core.regs.rf['state']
 128         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 129         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 130         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 131         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 132         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 133
 134         # DMI interface access
 135         intrf = self.core.regs.rf['int']
 136         crrf = self.core.regs.rf['cr']
 137         xerrf = self.core.regs.rf['xer']
 138         self.int_r = intrf.r_ports['dmi'] # INT read
 139         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 140         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 141
 142         # hack method of keeping an eye on whether branch/trap set the PC
 143         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 144         self.state_nia.wen.name = 'state_nia_wen'
 145
 146     def elaborate(self, platform):
 147         m = Module()
 148         comb, sync = m.d.comb, m.d.sync
 149
 150         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 151         m.submodules.imem = imem = self.imem
 152         m.submodules.dbg = dbg = self.dbg
 153         if self.jtag_en:
 154             m.submodules.jtag = jtag = self.jtag
 155             # TODO: UART2GDB mux, here, from external pin
 156             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 157             sync += dbg.dmi.connect_to(jtag.dmi)
 158
 159         cur_state = self.cur_state
 160
 161         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 162         if self.sram4x4k:
 163             for i, sram in enumerate(self.sram4k):
 164                 m.submodules["sram4k_%d" % i] = sram
 165
 166         # XICS interrupt handler
 167         if self.xics:
 168             m.submodules.xics_icp = icp = self.xics_icp
 169             m.submodules.xics_ics = ics = self.xics_ics
 170             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 171             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 172
 173         # GPIO test peripheral
 174         if self.gpio:
 175             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 176
 177         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 178         # XXX causes litex ECP5 test to get wrong idea about input and output
 179         # (but works with verilator sim *sigh*)
 180         #if self.gpio and self.xics:
 181         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 182
 183         # instruction decoder
 184         pdecode = create_pdecode()
 185         m.submodules.dec2 = pdecode2 = self.pdecode2
 186         m.submodules.svp64 = svp64 = self.svp64
 187
 188         # convenience
 189         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 190         intrf = self.core.regs.rf['int']
 191
 192         # clock delay power-on reset
 193         cd_por  = ClockDomain(reset_less=True)
 194         cd_sync = ClockDomain()
 195         core_sync = ClockDomain("coresync")
 196         m.domains += cd_por, cd_sync, core_sync
 197
 198         ti_rst = Signal(reset_less=True)
 199         delay = Signal(range(4), reset=3)
 200         with m.If(delay != 0):
 201             m.d.por += delay.eq(delay - 1)
 202         comb += cd_por.clk.eq(ClockSignal())
 203
 204         # power-on reset delay
 205         core_rst = ResetSignal("coresync")
 206         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 207         comb += core_rst.eq(ti_rst)
 208
 209         # busy/halted signals from core
 210         comb += self.busy_o.eq(core.busy_o)
 211         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 212
 213         # temporary hack: says "go" immediately for both address gen and ST
 214         l0 = core.l0
 215         ldst = core.fus.fus['ldst0']
 216         st_go_edge = rising_edge(m, ldst.st.rel_o)
 217         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 218         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 219
 220         # PC and instruction from I-Memory
 221         pc_changed = Signal() # note write to PC
 222         comb += self.pc_o.eq(cur_state.pc)
 223         ilatch = Signal(32)
 224
 225         # address of the next instruction, in the absence of a branch
 226         # depends on the instruction size
 227         nia = Signal(64, reset_less=True)
 228
 229         # read the PC
 230         pc = Signal(64, reset_less=True)
 231         pc_ok_delay = Signal()
 232         sync += pc_ok_delay.eq(~self.pc_i.ok)
 233         with m.If(self.pc_i.ok):
 234             # incoming override (start from pc_i)
 235             comb += pc.eq(self.pc_i.data)
 236         with m.Else():
 237             # otherwise read StateRegs regfile for PC...
 238             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 239         # ... but on a 1-clock delay
 240         with m.If(pc_ok_delay):
 241             comb += pc.eq(self.state_r_pc.data_o)
 242
 243         # don't write pc every cycle
 244         comb += self.state_w_pc.wen.eq(0)
 245         comb += self.state_w_pc.data_i.eq(0)
 246
 247         # don't read msr or svstate every cycle
 248         comb += self.state_r_sv.ren.eq(0)
 249         comb += self.state_r_msr.ren.eq(0)
 250         msr_read = Signal(reset=1)
 251         sv_read = Signal(reset=1)
 252
 253         # connect up debug signals
 254         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 255         comb += dbg.terminate_i.eq(core.core_terminate_o)
 256         comb += dbg.state.pc.eq(pc)
 257         #comb += dbg.state.pc.eq(cur_state.pc)
 258         comb += dbg.state.msr.eq(cur_state.msr)
 259
 260         # temporaries
 261         core_busy_o = core.busy_o                 # core is busy
 262         core_ivalid_i = core.ivalid_i             # instruction is valid
 263         core_issue_i = core.issue_i               # instruction is issued
 264         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 265         insn_type = core.e.do.insn_type           # instruction MicroOp type
 266
 267         # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
 268         # these are the handshake signals between fetch and decode/execute
 269
 270         # fetch FSM can run as soon as the PC is valid
 271         fetch_pc_valid_i = Signal()
 272         fetch_pc_ready_o = Signal()
 273         # when done, deliver the instruction to the next FSM
 274         fetch_insn_valid_o = Signal()
 275         fetch_insn_ready_i = Signal()
 276
 277         # latches copy of raw fetched instruction
 278         fetch_insn_o = Signal(32, reset_less=True)
 279
 280         # actually use a nmigen FSM for the first time (w00t)
 281         # this FSM is perhaps unusual in that it detects conditions
 282         # then "holds" information, combinatorially, for the core
 283         # (as opposed to using sync - which would be on a clock's delay)
 284         # this includes the actual opcode, valid flags and so on.
 285
 286         # this FSM performs fetch of raw instruction data, partial-decodes
 287         # it 32-bit at a time to detect SVP64 prefixes, and will optionally
 288         # read a 2nd 32-bit quantity if that occurs.
 289
 290         with m.FSM(name='fetch_fsm'):
 291
 292             # waiting (zzz)
 293             with m.State("IDLE"):
 294                 with m.If(~dbg.core_stop_o & ~core_rst):
 295                     comb += fetch_pc_ready_o.eq(1)
 296                     with m.If(fetch_pc_valid_i):
 297                         # instruction allowed to go: start by reading the PC
 298                         # capture the PC and also drop it into Insn Memory
 299                         # we have joined a pair of combinatorial memory
 300                         # lookups together.  this is Generally Bad.
 301                         comb += self.imem.a_pc_i.eq(pc)
 302                         comb += self.imem.a_valid_i.eq(1)
 303                         comb += self.imem.f_valid_i.eq(1)
 304                         sync += cur_state.pc.eq(pc)
 305
 306                         # initiate read of MSR/SVSTATE. arrives one clock later
 307                         comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 308                         comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 309                         sync += msr_read.eq(0)
 310                         sync += sv_read.eq(0)
 311
 312                         m.next = "INSN_READ"  # move to "wait for bus" phase
 313                 with m.Else():
 314                     comb += core.core_stopped_i.eq(1)
 315                     comb += dbg.core_stopped_i.eq(1)
 316
 317             # dummy pause to find out why simulation is not keeping up
 318             with m.State("INSN_READ"):
 319                 # one cycle later, msr/sv read arrives.  valid only once.
 320                 with m.If(~msr_read):
 321                     sync += msr_read.eq(1) # yeah don't read it again
 322                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 323                 with m.If(~sv_read):
 324                     sync += sv_read.eq(1) # yeah don't read it again
 325                     sync += cur_state.svstate.eq(self.state_r_sv.data_o)
 326                 with m.If(self.imem.f_busy_o): # zzz...
 327                     # busy: stay in wait-read
 328                     comb += self.imem.a_valid_i.eq(1)
 329                     comb += self.imem.f_valid_i.eq(1)
 330                 with m.Else():
 331                     # not busy: instruction fetched
 332                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 333                     # decode the SVP64 prefix, if any
 334                     comb += svp64.raw_opcode_in.eq(insn)
 335                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 336                     # pass the decoded prefix (if any) to PowerDecoder2
 337                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 338                     # calculate the address of the following instruction
 339                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 340                     sync += nia.eq(cur_state.pc + insn_size)
 341                     with m.If(~svp64.is_svp64_mode):
 342                         # with no prefix, store the instruction
 343                         # and hand it directly to the next FSM
 344                         sync += fetch_insn_o.eq(insn)
 345                         m.next = "INSN_READY"
 346                     with m.Else():
 347                         # fetch the rest of the instruction from memory
 348                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 349                         comb += self.imem.a_valid_i.eq(1)
 350                         comb += self.imem.f_valid_i.eq(1)
 351                         m.next = "INSN_READ2"
 352
 353             with m.State("INSN_READ2"):
 354                 with m.If(self.imem.f_busy_o):  # zzz...
 355                     # busy: stay in wait-read
 356                     comb += self.imem.a_valid_i.eq(1)
 357                     comb += self.imem.f_valid_i.eq(1)
 358                 with m.Else():
 359                     # not busy: instruction fetched
 360                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 361                     sync += fetch_insn_o.eq(insn)
 362                     m.next = "INSN_READY"
 363
 364             with m.State("INSN_READY"):
 365                 # hand over the instruction, to be decoded
 366                 comb += fetch_insn_valid_o.eq(1)
 367                 with m.If(fetch_insn_ready_i):
 368                     m.next = "IDLE"
 369
 370         # decode / issue / execute FSM.  this interacts with the "fetch" FSM
 371         # through fetch_pc_ready/valid (incoming) and fetch_insn_ready/valid
 372         # (outgoing).  SVP64 RM prefixes have already been set up by the
 373         # "fetch" phase, so execute is fairly straightforward.
 374
 375         with m.FSM():
 376
 377             # go fetch the instruction at the current PC
 378             # at this point, there is no instruction running, that
 379             # could inadvertently update the PC.
 380             with m.State("INSN_FETCH"):
 381                 comb += fetch_pc_valid_i.eq(1)
 382                 with m.If(fetch_pc_ready_o):
 383                     m.next = "INSN_WAIT"
 384
 385             # decode the instruction when it arrives
 386             with m.State("INSN_WAIT"):
 387                 comb += fetch_insn_ready_i.eq(1)
 388                 with m.If(fetch_insn_valid_o):
 389                     # decode the instruction
 390                     comb += dec_opcode_i.eq(fetch_insn_o)  # actual opcode
 391                     sync += core.e.eq(pdecode2.e)
 392                     sync += core.state.eq(cur_state)
 393                     sync += core.raw_insn_i.eq(dec_opcode_i)
 394                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 395                     sync += ilatch.eq(insn) # latch current insn
 396                     # also drop PC and MSR into decode "state"
 397                     m.next = "INSN_START" # move to "start"
 398
 399             # waiting for instruction bus (stays there until not busy)
 400             with m.State("INSN_START"):
 401                 comb += core_ivalid_i.eq(1) # instruction is valid
 402                 comb += core_issue_i.eq(1)  # and issued
 403                 sync += pc_changed.eq(0)
 404
 405                 m.next = "INSN_ACTIVE" # move to "wait completion"
 406
 407             # instruction started: must wait till it finishes
 408             with m.State("INSN_ACTIVE"):
 409                 with m.If(insn_type != MicrOp.OP_NOP):
 410                     comb += core_ivalid_i.eq(1) # instruction is valid
 411                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 412                     sync += pc_changed.eq(1)
 413                 with m.If(~core_busy_o): # instruction done!
 414                     # ok here we are not reading the branch unit.  TODO
 415                     # this just blithely overwrites whatever pipeline
 416                     # updated the PC
 417                     with m.If(~pc_changed):
 418                         comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 419                         comb += self.state_w_pc.data_i.eq(nia)
 420                     sync += core.e.eq(0)
 421                     sync += core.raw_insn_i.eq(0)
 422                     sync += core.bigendian_i.eq(0)
 423                     m.next = "INSN_FETCH"  # back to fetch
 424
 425         # for updating svstate (things like srcstep etc.)
 426         update_svstate = Signal() # TODO: move this somewhere above
 427         new_svstate = SVSTATERec("new_svstate") # and move this as well
 428         # check if svstate needs updating: if so, write it to State Regfile
 429         with m.If(update_svstate):
 430             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 431             comb += self.state_w_sv.data_i.eq(new_svstate)
 432
 433         # this bit doesn't have to be in the FSM: connect up to read
 434         # regfiles on demand from DMI
 435         with m.If(d_reg.req): # request for regfile access being made
 436             # TODO: error-check this
 437             # XXX should this be combinatorial?  sync better?
 438             if intrf.unary:
 439                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 440             else:
 441                 comb += self.int_r.addr.eq(d_reg.addr)
 442                 comb += self.int_r.ren.eq(1)
 443         d_reg_delay  = Signal()
 444         sync += d_reg_delay.eq(d_reg.req)
 445         with m.If(d_reg_delay):
 446             # data arrives one clock later
 447             comb += d_reg.data.eq(self.int_r.data_o)
 448             comb += d_reg.ack.eq(1)
 449
 450         # sigh same thing for CR debug
 451         with m.If(d_cr.req): # request for regfile access being made
 452             comb += self.cr_r.ren.eq(0b11111111) # enable all
 453         d_cr_delay  = Signal()
 454         sync += d_cr_delay.eq(d_cr.req)
 455         with m.If(d_cr_delay):
 456             # data arrives one clock later
 457             comb += d_cr.data.eq(self.cr_r.data_o)
 458             comb += d_cr.ack.eq(1)
 459
 460         # aaand XER...
 461         with m.If(d_xer.req): # request for regfile access being made
 462             comb += self.xer_r.ren.eq(0b111111) # enable all
 463         d_xer_delay  = Signal()
 464         sync += d_xer_delay.eq(d_xer.req)
 465         with m.If(d_xer_delay):
 466             # data arrives one clock later
 467             comb += d_xer.data.eq(self.xer_r.data_o)
 468             comb += d_xer.ack.eq(1)
 469
 470         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 471         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 472         self.tb_dec_fsm(m, cur_state.dec)
 473
 474         return m
 475
 476     def tb_dec_fsm(self, m, spr_dec):
 477         """tb_dec_fsm
 478
 479         this is a FSM for updating either dec or tb.  it runs alternately
 480         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 481         value to DEC, however the regfile has "passthrough" on it so this
 482         *should* be ok.
 483
 484         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 485         """
 486
 487         comb, sync = m.d.comb, m.d.sync
 488         fast_rf = self.core.regs.rf['fast']
 489         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 490         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 491
 492         with m.FSM() as fsm:
 493
 494             # initiates read of current DEC
 495             with m.State("DEC_READ"):
 496                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 497                 comb += fast_r_dectb.ren.eq(1)
 498                 m.next = "DEC_WRITE"
 499
 500             # waits for DEC read to arrive (1 cycle), updates with new value
 501             with m.State("DEC_WRITE"):
 502                 new_dec = Signal(64)
 503                 # TODO: MSR.LPCR 32-bit decrement mode
 504                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 505                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 506                 comb += fast_w_dectb.wen.eq(1)
 507                 comb += fast_w_dectb.data_i.eq(new_dec)
 508                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 509                 m.next = "TB_READ"
 510
 511             # initiates read of current TB
 512             with m.State("TB_READ"):
 513                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 514                 comb += fast_r_dectb.ren.eq(1)
 515                 m.next = "TB_WRITE"
 516
 517             # waits for read TB to arrive, initiates write of current TB
 518             with m.State("TB_WRITE"):
 519                 new_tb = Signal(64)
 520                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 521                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 522                 comb += fast_w_dectb.wen.eq(1)
 523                 comb += fast_w_dectb.data_i.eq(new_tb)
 524                 m.next = "DEC_READ"
 525
 526         return m
 527
 528     def __iter__(self):
 529         yield from self.pc_i.ports()
 530         yield self.pc_o
 531         yield self.memerr_o
 532         yield from self.core.ports()
 533         yield from self.imem.ports()
 534         yield self.core_bigendian_i
 535         yield self.busy_o
 536
 537     def ports(self):
 538         return list(self)
 539
 540     def external_ports(self):
 541         ports = self.pc_i.ports()
 542         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 543                 ]
 544
 545         if self.jtag_en:
 546             ports += list(self.jtag.external_ports())
 547         else:
 548             # don't add DMI if JTAG is enabled
 549             ports += list(self.dbg.dmi.ports())
 550
 551         ports += list(self.imem.ibus.fields.values())
 552         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 553
 554         if self.sram4x4k:
 555             for sram in self.sram4k:
 556                 ports += list(sram.bus.fields.values())
 557
 558         if self.xics:
 559             ports += list(self.xics_icp.bus.fields.values())
 560             ports += list(self.xics_ics.bus.fields.values())
 561             ports.append(self.int_level_i)
 562
 563         if self.gpio:
 564             ports += list(self.simple_gpio.bus.fields.values())
 565             ports.append(self.gpio_o)
 566
 567         return ports
 568
 569     def ports(self):
 570         return list(self)
 571
 572
 573 class TestIssuer(Elaboratable):
 574     def __init__(self, pspec):
 575         self.ti = TestIssuerInternal(pspec)
 576
 577         self.pll = DummyPLL()
 578
 579         # PLL direct clock or not
 580         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 581         if self.pll_en:
 582             self.pll_18_o = Signal(reset_less=True)
 583
 584     def elaborate(self, platform):
 585         m = Module()
 586         comb = m.d.comb
 587
 588         # TestIssuer runs at direct clock
 589         m.submodules.ti = ti = self.ti
 590         cd_int = ClockDomain("coresync")
 591
 592         if self.pll_en:
 593             # ClockSelect runs at PLL output internal clock rate
 594             m.submodules.pll = pll = self.pll
 595
 596             # add clock domains from PLL
 597             cd_pll = ClockDomain("pllclk")
 598             m.domains += cd_pll
 599
 600             # PLL clock established.  has the side-effect of running clklsel
 601             # at the PLL's speed (see DomainRenamer("pllclk") above)
 602             pllclk = ClockSignal("pllclk")
 603             comb += pllclk.eq(pll.clk_pll_o)
 604
 605             # wire up external 24mhz to PLL
 606             comb += pll.clk_24_i.eq(ClockSignal())
 607
 608             # output 18 mhz PLL test signal
 609             comb += self.pll_18_o.eq(pll.pll_18_o)
 610
 611             # now wire up ResetSignals.  don't mind them being in this domain
 612             pll_rst = ResetSignal("pllclk")
 613             comb += pll_rst.eq(ResetSignal())
 614
 615         # internal clock is set to selector clock-out.  has the side-effect of
 616         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 617         intclk = ClockSignal("coresync")
 618         if self.pll_en:
 619             comb += intclk.eq(pll.clk_pll_o)
 620         else:
 621             comb += intclk.eq(ClockSignal())
 622
 623         return m
 624
 625     def ports(self):
 626         return list(self.ti.ports()) + list(self.pll.ports()) + \
 627                [ClockSignal(), ResetSignal()]
 628
 629     def external_ports(self):
 630         ports = self.ti.external_ports()
 631         ports.append(ClockSignal())
 632         ports.append(ResetSignal())
 633         if self.pll_en:
 634             ports.append(self.pll.clk_sel_i)
 635             ports.append(self.pll_18_o)
 636             ports.append(self.pll.pll_lck_o)
 637         return ports
 638
 639
 640 if __name__ == '__main__':
 641     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 642              'spr': 1,
 643              'div': 1,
 644              'mul': 1,
 645              'shiftrot': 1
 646             }
 647     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 648                          imem_ifacetype='bare_wb',
 649                          addr_wid=48,
 650                          mask_wid=8,
 651                          reg_wid=64,
 652                          units=units)
 653     dut = TestIssuer(pspec)
 654     vl = main(dut, ports=dut.ports(), name="test_issuer")
 655
 656     if len(sys.argv) == 1:
 657         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 658         with open("test_issuer.il", "w") as f:
 659             f.write(vl)