src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # JTAG interface.  add this right at the start because if it's
  64         # added it *modifies* the pspec, by adding enable/disable signals
  65         # for parts of the rest of the core
  66         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  67         if self.jtag_en:
  68             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  69                       'pwm', 'sd0', 'sdr'}
  70             self.jtag = JTAG(get_pinspecs(subset=subset))
  71             # add signals to pspec to enable/disable icache and dcache
  72             # (or data and intstruction wishbone if icache/dcache not included)
  73             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  74             # TODO: do we actually care if these are not domain-synchronised?
  75             # honestly probably not.
  76             pspec.wb_icache_en = self.jtag.wb_icache_en
  77             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  78             self.wb_sram_en = self.jtag.wb_sram_en
  79         else:
  80             self.wb_sram_en = Const(1)
  81
  82         # add 4k sram blocks?
  83         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  84                          pspec.sram4x4kblock == True)
  85         if self.sram4x4k:
  86             self.sram4k = []
  87             for i in range(4):
  88                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
  89                                                     features={'err'}))
  90
  91         # add interrupt controller?
  92         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  93         if self.xics:
  94             self.xics_icp = XICS_ICP()
  95             self.xics_ics = XICS_ICS()
  96             self.int_level_i = self.xics_ics.int_level_i
  97
  98         # add GPIO peripheral?
  99         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
 100         if self.gpio:
 101             self.simple_gpio = SimpleGPIO()
 102             self.gpio_o = self.simple_gpio.gpio_o
 103
 104         # main instruction core25
 105         self.core = core = NonProductionCore(pspec)
 106
 107         # instruction decoder.  goes into Trap Record
 108         pdecode = create_pdecode()
 109         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 110         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 111                                      opkls=IssuerDecode2ToOperand)
 112         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 113
 114         # Test Instruction memory
 115         self.imem = ConfigFetchUnit(pspec).fu
 116         # one-row cache of instruction read
 117         self.iline = Signal(64) # one instruction line
 118         self.iprev_adr = Signal(64) # previous address: if different, do read
 119
 120         # DMI interface
 121         self.dbg = CoreDebug()
 122
 123         # instruction go/monitor
 124         self.pc_o = Signal(64, reset_less=True)
 125         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 126         self.svstate_i = Data(32, "svstate_i") # ditto
 127         self.core_bigendian_i = Signal()
 128         self.busy_o = Signal(reset_less=True)
 129         self.memerr_o = Signal(reset_less=True)
 130
 131         # STATE regfile read /write ports for PC, MSR, SVSTATE
 132         staterf = self.core.regs.rf['state']
 133         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 134         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 135         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 136         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 137         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 138
 139         # DMI interface access
 140         intrf = self.core.regs.rf['int']
 141         crrf = self.core.regs.rf['cr']
 142         xerrf = self.core.regs.rf['xer']
 143         self.int_r = intrf.r_ports['dmi'] # INT read
 144         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 145         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 146
 147         # hack method of keeping an eye on whether branch/trap set the PC
 148         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 149         self.state_nia.wen.name = 'state_nia_wen'
 150
 151     def fetch_fsm(self, m, core, pc, svstate, nia,
 152                         fetch_pc_ready_o, fetch_pc_valid_i,
 153                         fetch_insn_valid_o, fetch_insn_ready_i):
 154         """fetch FSM
 155         this FSM performs fetch of raw instruction data, partial-decodes
 156         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 157         read a 2nd 32-bit quantity if that occurs.
 158         """
 159         comb = m.d.comb
 160         sync = m.d.sync
 161         pdecode2 = self.pdecode2
 162         svp64 = self.svp64
 163         cur_state = self.cur_state
 164         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 165
 166         msr_read = Signal(reset=1)
 167
 168         with m.FSM(name='fetch_fsm'):
 169
 170             # waiting (zzz)
 171             with m.State("IDLE"):
 172                 comb += fetch_pc_ready_o.eq(1)
 173                 with m.If(fetch_pc_valid_i):
 174                     # instruction allowed to go: start by reading the PC
 175                     # capture the PC and also drop it into Insn Memory
 176                     # we have joined a pair of combinatorial memory
 177                     # lookups together.  this is Generally Bad.
 178                     comb += self.imem.a_pc_i.eq(pc)
 179                     comb += self.imem.a_valid_i.eq(1)
 180                     comb += self.imem.f_valid_i.eq(1)
 181                     sync += cur_state.pc.eq(pc)
 182                     sync += cur_state.svstate.eq(svstate) # and svstate
 183
 184                     # initiate read of MSR. arrives one clock later
 185                     comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 186                     sync += msr_read.eq(0)
 187
 188                     m.next = "INSN_READ"  # move to "wait for bus" phase
 189
 190             # dummy pause to find out why simulation is not keeping up
 191             with m.State("INSN_READ"):
 192                 # one cycle later, msr/sv read arrives.  valid only once.
 193                 with m.If(~msr_read):
 194                     sync += msr_read.eq(1) # yeah don't read it again
 195                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 196                 with m.If(self.imem.f_busy_o): # zzz...
 197                     # busy: stay in wait-read
 198                     comb += self.imem.a_valid_i.eq(1)
 199                     comb += self.imem.f_valid_i.eq(1)
 200                 with m.Else():
 201                     # not busy: instruction fetched
 202                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 203                     # decode the SVP64 prefix, if any
 204                     comb += svp64.raw_opcode_in.eq(insn)
 205                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 206                     # pass the decoded prefix (if any) to PowerDecoder2
 207                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 208                     # calculate the address of the following instruction
 209                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 210                     sync += nia.eq(cur_state.pc + insn_size)
 211                     with m.If(~svp64.is_svp64_mode):
 212                         # with no prefix, store the instruction
 213                         # and hand it directly to the next FSM
 214                         sync += dec_opcode_i.eq(insn)
 215                         m.next = "INSN_READY"
 216                     with m.Else():
 217                         # fetch the rest of the instruction from memory
 218                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 219                         comb += self.imem.a_valid_i.eq(1)
 220                         comb += self.imem.f_valid_i.eq(1)
 221                         m.next = "INSN_READ2"
 222
 223             with m.State("INSN_READ2"):
 224                 with m.If(self.imem.f_busy_o):  # zzz...
 225                     # busy: stay in wait-read
 226                     comb += self.imem.a_valid_i.eq(1)
 227                     comb += self.imem.f_valid_i.eq(1)
 228                 with m.Else():
 229                     # not busy: instruction fetched
 230                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 231                     sync += dec_opcode_i.eq(insn)
 232                     m.next = "INSN_READY"
 233
 234             with m.State("INSN_READY"):
 235                 # hand over the instruction, to be decoded
 236                 comb += fetch_insn_valid_o.eq(1)
 237                 with m.If(fetch_insn_ready_i):
 238                     m.next = "IDLE"
 239
 240     def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
 241                   dbg, core_rst,
 242                   fetch_pc_ready_o, fetch_pc_valid_i,
 243                   fetch_insn_valid_o, fetch_insn_ready_i,
 244                   exec_insn_valid_i, exec_insn_ready_o,
 245                   exec_pc_valid_o, exec_pc_ready_i):
 246         """issue FSM
 247
 248         decode / issue FSM.  this interacts with the "fetch" FSM
 249         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 250         (outgoing). also interacts with the "execute" FSM
 251         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 252         (incoming).
 253         SVP64 RM prefixes have already been set up by the
 254         "fetch" phase, so execute is fairly straightforward.
 255         """
 256
 257         comb = m.d.comb
 258         sync = m.d.sync
 259         pdecode2 = self.pdecode2
 260         cur_state = self.cur_state
 261
 262         # temporaries
 263         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 264
 265         # for updating svstate (things like srcstep etc.)
 266         update_svstate = Signal() # set this (below) if updating
 267         new_svstate = SVSTATERec("new_svstate")
 268         comb += new_svstate.eq(cur_state.svstate)
 269
 270         with m.FSM(name="issue_fsm"):
 271
 272             # Wait on "core stop" release, at reset
 273             with m.State("WAIT_RESET"):
 274                 with m.If(~dbg.core_stop_o & ~core_rst):
 275                     m.next = "INSN_FETCH"
 276                 with m.Else():
 277                     comb += core.core_stopped_i.eq(1)
 278                     comb += dbg.core_stopped_i.eq(1)
 279                     # while stopped, allow updating the PC and SVSTATE
 280                     with m.If(self.pc_i.ok):
 281                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 282                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 283                         sync += pc_changed.eq(1)
 284                     with m.If(self.svstate_i.ok):
 285                         comb += new_svstate.eq(self.svstate_i.data)
 286                         comb += update_svstate.eq(1)
 287                         sync += sv_changed.eq(1)
 288
 289             # go fetch the instruction at the current PC
 290             # at this point, there is no instruction running, that
 291             # could inadvertently update the PC.
 292             with m.State("INSN_FETCH"):
 293                 # TODO: update PC here, before fetch
 294                 comb += fetch_pc_valid_i.eq(1)
 295                 with m.If(fetch_pc_ready_o):
 296                     m.next = "INSN_WAIT"
 297
 298             # decode the instruction when it arrives
 299             with m.State("INSN_WAIT"):
 300                 comb += fetch_insn_ready_i.eq(1)
 301                 with m.If(fetch_insn_valid_o):
 302                     # decode the instruction
 303                     sync += core.e.eq(pdecode2.e)
 304                     sync += core.state.eq(cur_state)
 305                     sync += core.raw_insn_i.eq(dec_opcode_i)
 306                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 307                     # TODO: loop into INSN_FETCH if it's a vector instruction
 308                     #       and VL == 0.  this because VL==0 is a for-loop
 309                     #       from 0 to 0 i.e. always, always a NOP.
 310                     m.next = "INSN_EXECUTE"  # move to "execute"
 311
 312             with m.State("INSN_EXECUTE"):
 313                 comb += exec_insn_valid_i.eq(1)
 314                 with m.If(exec_insn_ready_o):
 315                     m.next = "EXECUTE_WAIT"
 316
 317             with m.State("EXECUTE_WAIT"):
 318                 # wait on "core stop" release, at instruction end
 319                 with m.If(~dbg.core_stop_o & ~core_rst):
 320                     comb += exec_pc_ready_i.eq(1)
 321                     with m.If(exec_pc_valid_o):
 322                         # precalculate srcstep+1
 323                         next_srcstep = Signal.like(cur_state.svstate.srcstep)
 324                         comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
 325                         # was this the last loop iteration?
 326                         is_last = Signal()
 327                         cur_vl = cur_state.svstate.vl
 328                         comb += is_last.eq(next_srcstep == cur_vl)
 329
 330                         # if either PC or SVSTATE were changed by the previous
 331                         # instruction, go directly back to Fetch, without
 332                         # updating either PC or SVSTATE
 333                         with m.If(pc_changed | sv_changed):
 334                             m.next = "INSN_FETCH"
 335
 336                         # also return to Fetch, when no output was a vector
 337                         # (regardless of SRCSTEP and VL), or when the last
 338                         # instruction was really the last one of the VL loop
 339                         with m.Elif(pdecode2.no_out_vec | is_last):
 340                             # before going back to fetch, update the PC state
 341                             # register with the NIA.
 342                             # ok here we are not reading the branch unit.
 343                             # TODO: this just blithely overwrites whatever
 344                             #       pipeline updated the PC
 345                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 346                             comb += self.state_w_pc.data_i.eq(nia)
 347                             # reset SRCSTEP before returning to Fetch
 348                             with m.If(~pdecode2.no_out_vec):
 349                                 comb += new_svstate.srcstep.eq(0)
 350                                 comb += update_svstate.eq(1)
 351                             m.next = "INSN_FETCH"
 352
 353                         # returning to Execute? then, first update SRCSTEP
 354                         with m.Else():
 355                             comb += new_svstate.srcstep.eq(next_srcstep)
 356                             comb += update_svstate.eq(1)
 357                             m.next = "DECODE_SV"
 358
 359                 with m.Else():
 360                     comb += core.core_stopped_i.eq(1)
 361                     comb += dbg.core_stopped_i.eq(1)
 362                     # while stopped, allow updating the PC and SVSTATE
 363                     with m.If(self.pc_i.ok):
 364                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 365                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 366                         sync += pc_changed.eq(1)
 367                     with m.If(self.svstate_i.ok):
 368                         comb += new_svstate.eq(self.svstate_i.data)
 369                         comb += update_svstate.eq(1)
 370                         sync += sv_changed.eq(1)
 371
 372             # need to decode the instruction again, after updating SRCSTEP
 373             # in the previous state.
 374             # mostly a copy of INSN_WAIT, but without the actual wait
 375             with m.State("DECODE_SV"):
 376                 # decode the instruction
 377                 sync += core.e.eq(pdecode2.e)
 378                 sync += core.state.eq(cur_state)
 379                 sync += core.bigendian_i.eq(self.core_bigendian_i)
 380                 m.next = "INSN_EXECUTE"  # move to "execute"
 381
 382         # check if svstate needs updating: if so, write it to State Regfile
 383         with m.If(update_svstate):
 384             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 385             comb += self.state_w_sv.data_i.eq(new_svstate)
 386             sync += cur_state.svstate.eq(new_svstate) # for next clock
 387
 388     def execute_fsm(self, m, core, insn_done, pc_changed, sv_changed,
 389                     exec_insn_valid_i, exec_insn_ready_o,
 390                     exec_pc_valid_o, exec_pc_ready_i):
 391         """execute FSM
 392
 393         execute FSM. this interacts with the "issue" FSM
 394         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 395         (outgoing). SVP64 RM prefixes have already been set up by the
 396         "issue" phase, so execute is fairly straightforward.
 397         """
 398
 399         comb = m.d.comb
 400         sync = m.d.sync
 401         pdecode2 = self.pdecode2
 402         svp64 = self.svp64
 403
 404         # temporaries
 405         core_busy_o = core.busy_o                 # core is busy
 406         core_ivalid_i = core.ivalid_i             # instruction is valid
 407         core_issue_i = core.issue_i               # instruction is issued
 408         insn_type = core.e.do.insn_type           # instruction MicroOp type
 409
 410         with m.FSM(name="exec_fsm"):
 411
 412             # waiting for instruction bus (stays there until not busy)
 413             with m.State("INSN_START"):
 414                 comb += exec_insn_ready_o.eq(1)
 415                 with m.If(exec_insn_valid_i):
 416                     comb += core_ivalid_i.eq(1)  # instruction is valid
 417                     comb += core_issue_i.eq(1)  # and issued
 418                     sync += sv_changed.eq(0)
 419                     sync += pc_changed.eq(0)
 420                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 421
 422             # instruction started: must wait till it finishes
 423             with m.State("INSN_ACTIVE"):
 424                 with m.If(insn_type != MicrOp.OP_NOP):
 425                     comb += core_ivalid_i.eq(1) # instruction is valid
 426                 # note changes to PC and SVSTATE
 427                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 428                     sync += sv_changed.eq(1)
 429                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 430                     sync += pc_changed.eq(1)
 431                 with m.If(~core_busy_o): # instruction done!
 432                     comb += insn_done.eq(1)
 433                     comb += exec_pc_valid_o.eq(1)
 434                     with m.If(exec_pc_ready_i):
 435                         m.next = "INSN_START"  # back to fetch
 436
 437     def elaborate(self, platform):
 438         m = Module()
 439         comb, sync = m.d.comb, m.d.sync
 440
 441         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 442         m.submodules.imem = imem = self.imem
 443         m.submodules.dbg = dbg = self.dbg
 444         if self.jtag_en:
 445             m.submodules.jtag = jtag = self.jtag
 446             # TODO: UART2GDB mux, here, from external pin
 447             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 448             sync += dbg.dmi.connect_to(jtag.dmi)
 449
 450         cur_state = self.cur_state
 451
 452         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 453         if self.sram4x4k:
 454             for i, sram in enumerate(self.sram4k):
 455                 m.submodules["sram4k_%d" % i] = sram
 456                 comb += sram.enable.eq(self.wb_sram_en)
 457
 458         # XICS interrupt handler
 459         if self.xics:
 460             m.submodules.xics_icp = icp = self.xics_icp
 461             m.submodules.xics_ics = ics = self.xics_ics
 462             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 463             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 464
 465         # GPIO test peripheral
 466         if self.gpio:
 467             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 468
 469         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 470         # XXX causes litex ECP5 test to get wrong idea about input and output
 471         # (but works with verilator sim *sigh*)
 472         #if self.gpio and self.xics:
 473         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 474
 475         # instruction decoder
 476         pdecode = create_pdecode()
 477         m.submodules.dec2 = pdecode2 = self.pdecode2
 478         m.submodules.svp64 = svp64 = self.svp64
 479
 480         # convenience
 481         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 482         intrf = self.core.regs.rf['int']
 483
 484         # clock delay power-on reset
 485         cd_por  = ClockDomain(reset_less=True)
 486         cd_sync = ClockDomain()
 487         core_sync = ClockDomain("coresync")
 488         m.domains += cd_por, cd_sync, core_sync
 489
 490         ti_rst = Signal(reset_less=True)
 491         delay = Signal(range(4), reset=3)
 492         with m.If(delay != 0):
 493             m.d.por += delay.eq(delay - 1)
 494         comb += cd_por.clk.eq(ClockSignal())
 495
 496         # power-on reset delay
 497         core_rst = ResetSignal("coresync")
 498         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 499         comb += core_rst.eq(ti_rst)
 500
 501         # busy/halted signals from core
 502         comb += self.busy_o.eq(core.busy_o)
 503         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 504
 505         # temporary hack: says "go" immediately for both address gen and ST
 506         l0 = core.l0
 507         ldst = core.fus.fus['ldst0']
 508         st_go_edge = rising_edge(m, ldst.st.rel_o)
 509         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 510         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 511
 512         # PC and instruction from I-Memory
 513         comb += self.pc_o.eq(cur_state.pc)
 514         pc_changed = Signal() # note write to PC
 515         sv_changed = Signal() # note write to SVSTATE
 516         insn_done = Signal()  # fires just once
 517
 518         # read the PC
 519         pc = Signal(64, reset_less=True)
 520         pc_ok_delay = Signal()
 521         sync += pc_ok_delay.eq(~self.pc_i.ok)
 522         with m.If(self.pc_i.ok):
 523             # incoming override (start from pc_i)
 524             comb += pc.eq(self.pc_i.data)
 525         with m.Else():
 526             # otherwise read StateRegs regfile for PC...
 527             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 528         # ... but on a 1-clock delay
 529         with m.If(pc_ok_delay):
 530             comb += pc.eq(self.state_r_pc.data_o)
 531
 532         # read svstate
 533         svstate = Signal(64, reset_less=True)
 534         svstate_ok_delay = Signal()
 535         sync += svstate_ok_delay.eq(~self.svstate_i.ok)
 536         with m.If(self.svstate_i.ok):
 537             # incoming override (start from svstate__i)
 538             comb += svstate.eq(self.svstate_i.data)
 539         with m.Else():
 540             # otherwise read StateRegs regfile for SVSTATE...
 541             comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 542         # ... but on a 1-clock delay
 543         with m.If(svstate_ok_delay):
 544             comb += svstate.eq(self.state_r_sv.data_o)
 545
 546         # don't write pc every cycle
 547         comb += self.state_w_pc.wen.eq(0)
 548         comb += self.state_w_pc.data_i.eq(0)
 549
 550         # don't read msr every cycle
 551         comb += self.state_r_msr.ren.eq(0)
 552
 553         # address of the next instruction, in the absence of a branch
 554         # depends on the instruction size
 555         nia = Signal(64, reset_less=True)
 556
 557         # connect up debug signals
 558         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 559         comb += dbg.terminate_i.eq(core.core_terminate_o)
 560         comb += dbg.state.pc.eq(pc)
 561         comb += dbg.state.svstate.eq(svstate)
 562         comb += dbg.state.msr.eq(cur_state.msr)
 563
 564         # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
 565         # these are the handshake signals between fetch and decode/execute
 566
 567         # fetch FSM can run as soon as the PC is valid
 568         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 569         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 570
 571         # fetch FSM hands over the instruction to be decoded / issued
 572         fetch_insn_valid_o = Signal()
 573         fetch_insn_ready_i = Signal()
 574
 575         # issue FSM delivers the instruction to the be executed
 576         exec_insn_valid_i = Signal()
 577         exec_insn_ready_o = Signal()
 578
 579         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 580         exec_pc_valid_o = Signal()
 581         exec_pc_ready_i = Signal()
 582
 583         # actually use a nmigen FSM for the first time (w00t)
 584         # this FSM is perhaps unusual in that it detects conditions
 585         # then "holds" information, combinatorially, for the core
 586         # (as opposed to using sync - which would be on a clock's delay)
 587         # this includes the actual opcode, valid flags and so on.
 588
 589         self.fetch_fsm(m, core, pc, svstate, nia,
 590                        fetch_pc_ready_o, fetch_pc_valid_i,
 591                        fetch_insn_valid_o, fetch_insn_ready_i)
 592
 593         # TODO: an SVSTATE-based for-loop FSM that goes in between
 594         # fetch pc/insn ready/valid and advances SVSTATE.srcstep
 595         # until it reaches VL-1 or PowerDecoder2.no_out_vec is True.
 596         self.issue_fsm(m, core, pc_changed, sv_changed, nia,
 597                        dbg, core_rst,
 598                        fetch_pc_ready_o, fetch_pc_valid_i,
 599                        fetch_insn_valid_o, fetch_insn_ready_i,
 600                        exec_insn_valid_i, exec_insn_ready_o,
 601                        exec_pc_ready_i, exec_pc_valid_o)
 602
 603         self.execute_fsm(m, core, insn_done, pc_changed, sv_changed,
 604                          exec_insn_valid_i, exec_insn_ready_o,
 605                          exec_pc_ready_i, exec_pc_valid_o)
 606
 607         # this bit doesn't have to be in the FSM: connect up to read
 608         # regfiles on demand from DMI
 609         with m.If(d_reg.req): # request for regfile access being made
 610             # TODO: error-check this
 611             # XXX should this be combinatorial?  sync better?
 612             if intrf.unary:
 613                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 614             else:
 615                 comb += self.int_r.addr.eq(d_reg.addr)
 616                 comb += self.int_r.ren.eq(1)
 617         d_reg_delay  = Signal()
 618         sync += d_reg_delay.eq(d_reg.req)
 619         with m.If(d_reg_delay):
 620             # data arrives one clock later
 621             comb += d_reg.data.eq(self.int_r.data_o)
 622             comb += d_reg.ack.eq(1)
 623
 624         # sigh same thing for CR debug
 625         with m.If(d_cr.req): # request for regfile access being made
 626             comb += self.cr_r.ren.eq(0b11111111) # enable all
 627         d_cr_delay  = Signal()
 628         sync += d_cr_delay.eq(d_cr.req)
 629         with m.If(d_cr_delay):
 630             # data arrives one clock later
 631             comb += d_cr.data.eq(self.cr_r.data_o)
 632             comb += d_cr.ack.eq(1)
 633
 634         # aaand XER...
 635         with m.If(d_xer.req): # request for regfile access being made
 636             comb += self.xer_r.ren.eq(0b111111) # enable all
 637         d_xer_delay  = Signal()
 638         sync += d_xer_delay.eq(d_xer.req)
 639         with m.If(d_xer_delay):
 640             # data arrives one clock later
 641             comb += d_xer.data.eq(self.xer_r.data_o)
 642             comb += d_xer.ack.eq(1)
 643
 644         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 645         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 646         self.tb_dec_fsm(m, cur_state.dec)
 647
 648         return m
 649
 650     def tb_dec_fsm(self, m, spr_dec):
 651         """tb_dec_fsm
 652
 653         this is a FSM for updating either dec or tb.  it runs alternately
 654         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 655         value to DEC, however the regfile has "passthrough" on it so this
 656         *should* be ok.
 657
 658         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 659         """
 660
 661         comb, sync = m.d.comb, m.d.sync
 662         fast_rf = self.core.regs.rf['fast']
 663         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 664         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 665
 666         with m.FSM() as fsm:
 667
 668             # initiates read of current DEC
 669             with m.State("DEC_READ"):
 670                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 671                 comb += fast_r_dectb.ren.eq(1)
 672                 m.next = "DEC_WRITE"
 673
 674             # waits for DEC read to arrive (1 cycle), updates with new value
 675             with m.State("DEC_WRITE"):
 676                 new_dec = Signal(64)
 677                 # TODO: MSR.LPCR 32-bit decrement mode
 678                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 679                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 680                 comb += fast_w_dectb.wen.eq(1)
 681                 comb += fast_w_dectb.data_i.eq(new_dec)
 682                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 683                 m.next = "TB_READ"
 684
 685             # initiates read of current TB
 686             with m.State("TB_READ"):
 687                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 688                 comb += fast_r_dectb.ren.eq(1)
 689                 m.next = "TB_WRITE"
 690
 691             # waits for read TB to arrive, initiates write of current TB
 692             with m.State("TB_WRITE"):
 693                 new_tb = Signal(64)
 694                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 695                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 696                 comb += fast_w_dectb.wen.eq(1)
 697                 comb += fast_w_dectb.data_i.eq(new_tb)
 698                 m.next = "DEC_READ"
 699
 700         return m
 701
 702     def __iter__(self):
 703         yield from self.pc_i.ports()
 704         yield self.pc_o
 705         yield self.memerr_o
 706         yield from self.core.ports()
 707         yield from self.imem.ports()
 708         yield self.core_bigendian_i
 709         yield self.busy_o
 710
 711     def ports(self):
 712         return list(self)
 713
 714     def external_ports(self):
 715         ports = self.pc_i.ports()
 716         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 717                 ]
 718
 719         if self.jtag_en:
 720             ports += list(self.jtag.external_ports())
 721         else:
 722             # don't add DMI if JTAG is enabled
 723             ports += list(self.dbg.dmi.ports())
 724
 725         ports += list(self.imem.ibus.fields.values())
 726         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 727
 728         if self.sram4x4k:
 729             for sram in self.sram4k:
 730                 ports += list(sram.bus.fields.values())
 731
 732         if self.xics:
 733             ports += list(self.xics_icp.bus.fields.values())
 734             ports += list(self.xics_ics.bus.fields.values())
 735             ports.append(self.int_level_i)
 736
 737         if self.gpio:
 738             ports += list(self.simple_gpio.bus.fields.values())
 739             ports.append(self.gpio_o)
 740
 741         return ports
 742
 743     def ports(self):
 744         return list(self)
 745
 746
 747 class TestIssuer(Elaboratable):
 748     def __init__(self, pspec):
 749         self.ti = TestIssuerInternal(pspec)
 750
 751         self.pll = DummyPLL()
 752
 753         # PLL direct clock or not
 754         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 755         if self.pll_en:
 756             self.pll_18_o = Signal(reset_less=True)
 757
 758     def elaborate(self, platform):
 759         m = Module()
 760         comb = m.d.comb
 761
 762         # TestIssuer runs at direct clock
 763         m.submodules.ti = ti = self.ti
 764         cd_int = ClockDomain("coresync")
 765
 766         if self.pll_en:
 767             # ClockSelect runs at PLL output internal clock rate
 768             m.submodules.pll = pll = self.pll
 769
 770             # add clock domains from PLL
 771             cd_pll = ClockDomain("pllclk")
 772             m.domains += cd_pll
 773
 774             # PLL clock established.  has the side-effect of running clklsel
 775             # at the PLL's speed (see DomainRenamer("pllclk") above)
 776             pllclk = ClockSignal("pllclk")
 777             comb += pllclk.eq(pll.clk_pll_o)
 778
 779             # wire up external 24mhz to PLL
 780             comb += pll.clk_24_i.eq(ClockSignal())
 781
 782             # output 18 mhz PLL test signal
 783             comb += self.pll_18_o.eq(pll.pll_18_o)
 784
 785             # now wire up ResetSignals.  don't mind them being in this domain
 786             pll_rst = ResetSignal("pllclk")
 787             comb += pll_rst.eq(ResetSignal())
 788
 789         # internal clock is set to selector clock-out.  has the side-effect of
 790         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 791         intclk = ClockSignal("coresync")
 792         if self.pll_en:
 793             comb += intclk.eq(pll.clk_pll_o)
 794         else:
 795             comb += intclk.eq(ClockSignal())
 796
 797         return m
 798
 799     def ports(self):
 800         return list(self.ti.ports()) + list(self.pll.ports()) + \
 801                [ClockSignal(), ResetSignal()]
 802
 803     def external_ports(self):
 804         ports = self.ti.external_ports()
 805         ports.append(ClockSignal())
 806         ports.append(ResetSignal())
 807         if self.pll_en:
 808             ports.append(self.pll.clk_sel_i)
 809             ports.append(self.pll_18_o)
 810             ports.append(self.pll.pll_lck_o)
 811         return ports
 812
 813
 814 if __name__ == '__main__':
 815     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 816              'spr': 1,
 817              'div': 1,
 818              'mul': 1,
 819              'shiftrot': 1
 820             }
 821     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 822                          imem_ifacetype='bare_wb',
 823                          addr_wid=48,
 824                          mask_wid=8,
 825                          reg_wid=64,
 826                          units=units)
 827     dut = TestIssuer(pspec)
 828     vl = main(dut, ports=dut.ports(), name="test_issuer")
 829
 830     if len(sys.argv) == 1:
 831         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 832         with open("test_issuer.il", "w") as f:
 833             f.write(vl)