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Skip fetching integer predicate mask when register number is zero
[soc.git] / src / soc / simple / issuer.py
1 """simple core issuer
2
3 not in any way intended for production use. this runs a FSM that:
4
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
9 * increments the PC
10 * does it all over again
11
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
15 improved.
16 """
17
18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
19 ClockDomain, DomainRenamer, Mux, Const, Repl)
20 from nmigen.cli import rtlil
21 from nmigen.cli import main
22 import sys
23
24 from soc.decoder.power_decoder import create_pdecode
25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
27 from soc.decoder.decode2execute1 import Data
28 from soc.experiment.testmem import TestMemory # test only for instructions
29 from soc.regfile.regfiles import StateRegs, FastRegs
30 from soc.simple.core import NonProductionCore
31 from soc.config.test.test_loadstore import TestMemPspec
32 from soc.config.ifetch import ConfigFetchUnit
33 from soc.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
34 SVP64PredMode)
35 from soc.debug.dmi import CoreDebug, DMIInterface
36 from soc.debug.jtag import JTAG
37 from soc.config.pinouts import get_pinspecs
38 from soc.config.state import CoreState
39 from soc.interrupts.xics import XICS_ICP, XICS_ICS
40 from soc.bus.simple_gpio import SimpleGPIO
41 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
42 from soc.clock.select import ClockSelect
43 from soc.clock.dummypll import DummyPLL
44 from soc.sv.svstate import SVSTATERec
45
46
47 from nmutil.util import rising_edge
48
49 def get_insn(f_instr_o, pc):
50 if f_instr_o.width == 32:
51 return f_instr_o
52 else:
53 # 64-bit: bit 2 of pc decides which word to select
54 return f_instr_o.word_select(pc[2], 32)
55
56 # gets state input or reads from state regfile
57 def state_get(m, state_i, name, regfile, regnum):
58 comb = m.d.comb
59 sync = m.d.sync
60 # read the PC
61 res = Signal(64, reset_less=True, name=name)
62 res_ok_delay = Signal(name="%s_ok_delay" % name)
63 sync += res_ok_delay.eq(~state_i.ok)
64 with m.If(state_i.ok):
65 # incoming override (start from pc_i)
66 comb += res.eq(state_i.data)
67 with m.Else():
68 # otherwise read StateRegs regfile for PC...
69 comb += regfile.ren.eq(1<<regnum)
70 # ... but on a 1-clock delay
71 with m.If(res_ok_delay):
72 comb += res.eq(regfile.data_o)
73 return res
74
75 def get_predint(m, mask, name):
76 """decode SVP64 predicate integer mask field to reg number and invert
77 this is identical to the equivalent function in ISACaller except that
78 it doesn't read the INT directly, it just decodes "what needs to be done"
79 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
80 """
81 comb = m.d.comb
82 regread = Signal(5, name=name+"regread")
83 invert = Signal(name=name+"invert")
84 unary = Signal(name=name+"unary")
85 with m.Switch(mask):
86 with m.Case(SVP64PredInt.ALWAYS.value):
87 comb += regread.eq(0)
88 comb += invert.eq(1)
89 with m.Case(SVP64PredInt.R3_UNARY.value):
90 comb += regread.eq(3)
91 comb += unary.eq(1)
92 with m.Case(SVP64PredInt.R3.value):
93 comb += regread.eq(3)
94 with m.Case(SVP64PredInt.R3_N.value):
95 comb += regread.eq(3)
96 comb += invert.eq(1)
97 with m.Case(SVP64PredInt.R10.value):
98 comb += regread.eq(10)
99 with m.Case(SVP64PredInt.R10_N.value):
100 comb += regread.eq(10)
101 comb += invert.eq(1)
102 with m.Case(SVP64PredInt.R30.value):
103 comb += regread.eq(30)
104 with m.Case(SVP64PredInt.R30_N.value):
105 comb += regread.eq(30)
106 comb += invert.eq(1)
107 return regread, invert, unary
108
109 def get_predcr(m, mask, name):
110 """decode SVP64 predicate CR to reg number field and invert status
111 this is identical to _get_predcr in ISACaller
112 """
113 comb = m.d.comb
114 idx = Signal(2, name=name+"idx")
115 invert = Signal(name=name+"crinvert")
116 with m.Switch(mask):
117 with m.Case(SVP64PredCR.LT.value):
118 comb += idx.eq(0)
119 comb += invert.eq(1)
120 with m.Case(SVP64PredCR.GE.value):
121 comb += idx.eq(0)
122 comb += invert.eq(0)
123 with m.Case(SVP64PredCR.GT.value):
124 comb += idx.eq(1)
125 comb += invert.eq(1)
126 with m.Case(SVP64PredCR.LE.value):
127 comb += idx.eq(1)
128 comb += invert.eq(0)
129 with m.Case(SVP64PredCR.EQ.value):
130 comb += idx.eq(2)
131 comb += invert.eq(1)
132 with m.Case(SVP64PredCR.NE.value):
133 comb += idx.eq(1)
134 comb += invert.eq(0)
135 with m.Case(SVP64PredCR.SO.value):
136 comb += idx.eq(3)
137 comb += invert.eq(1)
138 with m.Case(SVP64PredCR.NS.value):
139 comb += idx.eq(3)
140 comb += invert.eq(0)
141 return idx, invert
142
143
144 class TestIssuerInternal(Elaboratable):
145 """TestIssuer - reads instructions from TestMemory and issues them
146
147 efficiency and speed is not the main goal here: functional correctness
148 and code clarity is. optimisations (which almost 100% interfere with
149 easy understanding) come later.
150 """
151 def __init__(self, pspec):
152
153 # test is SVP64 is to be enabled
154 self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
155
156 # JTAG interface. add this right at the start because if it's
157 # added it *modifies* the pspec, by adding enable/disable signals
158 # for parts of the rest of the core
159 self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
160 if self.jtag_en:
161 subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
162 'pwm', 'sd0', 'sdr'}
163 self.jtag = JTAG(get_pinspecs(subset=subset))
164 # add signals to pspec to enable/disable icache and dcache
165 # (or data and intstruction wishbone if icache/dcache not included)
166 # https://bugs.libre-soc.org/show_bug.cgi?id=520
167 # TODO: do we actually care if these are not domain-synchronised?
168 # honestly probably not.
169 pspec.wb_icache_en = self.jtag.wb_icache_en
170 pspec.wb_dcache_en = self.jtag.wb_dcache_en
171 self.wb_sram_en = self.jtag.wb_sram_en
172 else:
173 self.wb_sram_en = Const(1)
174
175 # add 4k sram blocks?
176 self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
177 pspec.sram4x4kblock == True)
178 if self.sram4x4k:
179 self.sram4k = []
180 for i in range(4):
181 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
182 features={'err'}))
183
184 # add interrupt controller?
185 self.xics = hasattr(pspec, "xics") and pspec.xics == True
186 if self.xics:
187 self.xics_icp = XICS_ICP()
188 self.xics_ics = XICS_ICS()
189 self.int_level_i = self.xics_ics.int_level_i
190
191 # add GPIO peripheral?
192 self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
193 if self.gpio:
194 self.simple_gpio = SimpleGPIO()
195 self.gpio_o = self.simple_gpio.gpio_o
196
197 # main instruction core. suitable for prototyping / demo only
198 self.core = core = NonProductionCore(pspec)
199
200 # instruction decoder. goes into Trap Record
201 pdecode = create_pdecode()
202 self.cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE)
203 self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
204 opkls=IssuerDecode2ToOperand,
205 svp64_en=self.svp64_en)
206 if self.svp64_en:
207 self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
208
209 # Test Instruction memory
210 self.imem = ConfigFetchUnit(pspec).fu
211
212 # DMI interface
213 self.dbg = CoreDebug()
214
215 # instruction go/monitor
216 self.pc_o = Signal(64, reset_less=True)
217 self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
218 self.svstate_i = Data(32, "svstate_i") # ditto
219 self.core_bigendian_i = Signal() # TODO: set based on MSR.LE
220 self.busy_o = Signal(reset_less=True)
221 self.memerr_o = Signal(reset_less=True)
222
223 # STATE regfile read /write ports for PC, MSR, SVSTATE
224 staterf = self.core.regs.rf['state']
225 self.state_r_pc = staterf.r_ports['cia'] # PC rd
226 self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
227 self.state_r_msr = staterf.r_ports['msr'] # MSR rd
228 self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
229 self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
230
231 # DMI interface access
232 intrf = self.core.regs.rf['int']
233 crrf = self.core.regs.rf['cr']
234 xerrf = self.core.regs.rf['xer']
235 self.int_r = intrf.r_ports['dmi'] # INT read
236 self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
237 self.xer_r = xerrf.r_ports['full_xer'] # XER read
238
239 # for predication
240 self.int_pred = intrf.r_ports['pred'] # INT predicate read
241 self.cr_pred = crrf.r_ports['cr_pred'] # CR predicate read
242
243 # hack method of keeping an eye on whether branch/trap set the PC
244 self.state_nia = self.core.regs.rf['state'].w_ports['nia']
245 self.state_nia.wen.name = 'state_nia_wen'
246
247 # pulse to synchronize the simulator at instruction end
248 self.insn_done = Signal()
249
250 if self.svp64_en:
251 # store copies of predicate masks
252 self.srcmask = Signal(64)
253 self.dstmask = Signal(64)
254
255 def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
256 fetch_pc_ready_o, fetch_pc_valid_i,
257 fetch_insn_valid_o, fetch_insn_ready_i):
258 """fetch FSM
259
260 this FSM performs fetch of raw instruction data, partial-decodes
261 it 32-bit at a time to detect SVP64 prefixes, and will optionally
262 read a 2nd 32-bit quantity if that occurs.
263 """
264 comb = m.d.comb
265 sync = m.d.sync
266 pdecode2 = self.pdecode2
267 cur_state = self.cur_state
268 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
269
270 msr_read = Signal(reset=1)
271
272 with m.FSM(name='fetch_fsm'):
273
274 # waiting (zzz)
275 with m.State("IDLE"):
276 comb += fetch_pc_ready_o.eq(1)
277 with m.If(fetch_pc_valid_i):
278 # instruction allowed to go: start by reading the PC
279 # capture the PC and also drop it into Insn Memory
280 # we have joined a pair of combinatorial memory
281 # lookups together. this is Generally Bad.
282 comb += self.imem.a_pc_i.eq(pc)
283 comb += self.imem.a_valid_i.eq(1)
284 comb += self.imem.f_valid_i.eq(1)
285 sync += cur_state.pc.eq(pc)
286 sync += cur_state.svstate.eq(svstate) # and svstate
287
288 # initiate read of MSR. arrives one clock later
289 comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
290 sync += msr_read.eq(0)
291
292 m.next = "INSN_READ" # move to "wait for bus" phase
293
294 # dummy pause to find out why simulation is not keeping up
295 with m.State("INSN_READ"):
296 # one cycle later, msr/sv read arrives. valid only once.
297 with m.If(~msr_read):
298 sync += msr_read.eq(1) # yeah don't read it again
299 sync += cur_state.msr.eq(self.state_r_msr.data_o)
300 with m.If(self.imem.f_busy_o): # zzz...
301 # busy: stay in wait-read
302 comb += self.imem.a_valid_i.eq(1)
303 comb += self.imem.f_valid_i.eq(1)
304 with m.Else():
305 # not busy: instruction fetched
306 insn = get_insn(self.imem.f_instr_o, cur_state.pc)
307 if self.svp64_en:
308 svp64 = self.svp64
309 # decode the SVP64 prefix, if any
310 comb += svp64.raw_opcode_in.eq(insn)
311 comb += svp64.bigendian.eq(self.core_bigendian_i)
312 # pass the decoded prefix (if any) to PowerDecoder2
313 sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
314 # remember whether this is a prefixed instruction, so
315 # the FSM can readily loop when VL==0
316 sync += is_svp64_mode.eq(svp64.is_svp64_mode)
317 # calculate the address of the following instruction
318 insn_size = Mux(svp64.is_svp64_mode, 8, 4)
319 sync += nia.eq(cur_state.pc + insn_size)
320 with m.If(~svp64.is_svp64_mode):
321 # with no prefix, store the instruction
322 # and hand it directly to the next FSM
323 sync += dec_opcode_i.eq(insn)
324 m.next = "INSN_READY"
325 with m.Else():
326 # fetch the rest of the instruction from memory
327 comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
328 comb += self.imem.a_valid_i.eq(1)
329 comb += self.imem.f_valid_i.eq(1)
330 m.next = "INSN_READ2"
331 else:
332 # not SVP64 - 32-bit only
333 sync += nia.eq(cur_state.pc + 4)
334 sync += dec_opcode_i.eq(insn)
335 m.next = "INSN_READY"
336
337 with m.State("INSN_READ2"):
338 with m.If(self.imem.f_busy_o): # zzz...
339 # busy: stay in wait-read
340 comb += self.imem.a_valid_i.eq(1)
341 comb += self.imem.f_valid_i.eq(1)
342 with m.Else():
343 # not busy: instruction fetched
344 insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
345 sync += dec_opcode_i.eq(insn)
346 m.next = "INSN_READY"
347 # TODO: probably can start looking at pdecode2.rm_dec
348 # here or maybe even in INSN_READ state, if svp64_mode
349 # detected, in order to trigger - and wait for - the
350 # predicate reading.
351 pmode = pdecode2.rm_dec.predmode
352 """
353 if pmode != SVP64PredMode.ALWAYS.value:
354 fire predicate loading FSM and wait before
355 moving to INSN_READY
356 else:
357 sync += self.srcmask.eq(-1) # set to all 1s
358 sync += self.dstmask.eq(-1) # set to all 1s
359 m.next = "INSN_READY"
360 """
361
362 with m.State("INSN_READY"):
363 # hand over the instruction, to be decoded
364 comb += fetch_insn_valid_o.eq(1)
365 with m.If(fetch_insn_ready_i):
366 m.next = "IDLE"
367
368 def fetch_predicate_fsm(self, m,
369 pred_insn_valid_i, pred_insn_ready_o,
370 pred_mask_valid_o, pred_mask_ready_i):
371 """fetch_predicate_fsm - obtains (constructs in the case of CR)
372 src/dest predicate masks
373
374 https://bugs.libre-soc.org/show_bug.cgi?id=617
375 the predicates can be read here, by using IntRegs r_ports['pred']
376 or CRRegs r_ports['pred']. in the case of CRs it will have to
377 be done through multiple reads, extracting one relevant at a time.
378 later, a faster way would be to use the 32-bit-wide CR port but
379 this is more complex decoding, here. equivalent code used in
380 ISACaller is "from soc.decoder.isa.caller import get_predcr"
381 """
382 comb = m.d.comb
383 sync = m.d.sync
384 pdecode2 = self.pdecode2
385 rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
386 predmode = rm_dec.predmode
387 srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
388 cr_pred, int_pred = self.cr_pred, self.int_pred # read regfiles
389
390 # elif predmode == CR:
391 # CR-src sidx, sinvert = get_predcr(m, srcpred)
392 # CR-dst didx, dinvert = get_predcr(m, dstpred)
393 # TODO read CR-src and CR-dst into self.srcmask+dstmask with loop
394 # has to cope with first one then the other
395 # for cr_idx = FSM-state-loop(0..VL-1):
396 # FSM-state-trigger-CR-read:
397 # cr_ren = (1<<7-(cr_idx+SVP64CROffs.CRPred))
398 # comb += cr_pred.ren.eq(cr_ren)
399 # FSM-state-1-clock-later-actual-Read:
400 # cr_field = Signal(4)
401 # cr_bit = Signal(1)
402 # # read the CR field, select the appropriate bit
403 # comb += cr_field.eq(cr_pred.data_o)
404 # comb += cr_bit.eq(cr_field.bit_select(idx)))
405 # # just like in branch BO tests
406 # comd += self.srcmask[cr_idx].eq(inv ^ cr_bit)
407
408 # decode predicates
409 sregread, sinvert, sunary = get_predint(m, srcpred, 's')
410 dregread, dinvert, dunary = get_predint(m, dstpred, 'd')
411 sidx, scrinvert = get_predcr(m, srcpred, 's')
412 didx, dcrinvert = get_predcr(m, dstpred, 'd')
413
414 with m.FSM(name="fetch_predicate"):
415
416 with m.State("FETCH_PRED_IDLE"):
417 comb += pred_insn_ready_o.eq(1)
418 with m.If(pred_insn_valid_i):
419 with m.If(predmode == SVP64PredMode.INT):
420 # skip fetching destination mask register, when zero
421 with m.If(dregread == 0):
422 sync += self.dstmask.eq(-1)
423 # directly go to fetch source mask register
424 # guaranteed not to be zero (otherwise predmode
425 # would be SVP64PredMode.ALWAYS, not INT)
426 comb += int_pred.addr.eq(sregread)
427 comb += int_pred.ren.eq(1)
428 m.next = "INT_SRC_READ"
429 # fetch destination predicate register
430 with m.Else():
431 comb += int_pred.addr.eq(dregread)
432 comb += int_pred.ren.eq(1)
433 m.next = "INT_DST_READ"
434 with m.Else():
435 sync += self.srcmask.eq(-1)
436 sync += self.dstmask.eq(-1)
437 m.next = "FETCH_PRED_DONE"
438
439 with m.State("INT_DST_READ"):
440 # store destination mask
441 inv = Repl(dinvert, 64)
442 sync += self.dstmask.eq(self.int_pred.data_o ^ inv)
443 # skip fetching source mask register, when zero
444 with m.If(sregread == 0):
445 sync += self.srcmask.eq(-1)
446 m.next = "FETCH_PRED_DONE"
447 # fetch source predicate register
448 with m.Else():
449 comb += int_pred.addr.eq(sregread)
450 comb += int_pred.ren.eq(1)
451 m.next = "INT_SRC_READ"
452
453 with m.State("INT_SRC_READ"):
454 # store source mask
455 inv = Repl(sinvert, 64)
456 sync += self.srcmask.eq(self.int_pred.data_o ^ inv)
457 m.next = "FETCH_PRED_DONE"
458
459 with m.State("FETCH_PRED_DONE"):
460 comb += pred_mask_valid_o.eq(1)
461 with m.If(pred_mask_ready_i):
462 m.next = "FETCH_PRED_IDLE"
463
464 def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
465 dbg, core_rst, is_svp64_mode,
466 fetch_pc_ready_o, fetch_pc_valid_i,
467 fetch_insn_valid_o, fetch_insn_ready_i,
468 pred_insn_valid_i, pred_insn_ready_o,
469 pred_mask_valid_o, pred_mask_ready_i,
470 exec_insn_valid_i, exec_insn_ready_o,
471 exec_pc_valid_o, exec_pc_ready_i):
472 """issue FSM
473
474 decode / issue FSM. this interacts with the "fetch" FSM
475 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
476 (outgoing). also interacts with the "execute" FSM
477 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
478 (incoming).
479 SVP64 RM prefixes have already been set up by the
480 "fetch" phase, so execute is fairly straightforward.
481 """
482
483 comb = m.d.comb
484 sync = m.d.sync
485 pdecode2 = self.pdecode2
486 cur_state = self.cur_state
487
488 # temporaries
489 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
490
491 # for updating svstate (things like srcstep etc.)
492 update_svstate = Signal() # set this (below) if updating
493 new_svstate = SVSTATERec("new_svstate")
494 comb += new_svstate.eq(cur_state.svstate)
495
496 # precalculate srcstep+1 and dststep+1
497 cur_srcstep = cur_state.svstate.srcstep
498 cur_dststep = cur_state.svstate.dststep
499 next_srcstep = Signal.like(cur_srcstep)
500 next_dststep = Signal.like(cur_dststep)
501 comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
502 comb += next_dststep.eq(cur_state.svstate.dststep+1)
503
504 with m.FSM(name="issue_fsm"):
505
506 # sync with the "fetch" phase which is reading the instruction
507 # at this point, there is no instruction running, that
508 # could inadvertently update the PC.
509 with m.State("ISSUE_START"):
510 # wait on "core stop" release, before next fetch
511 # need to do this here, in case we are in a VL==0 loop
512 with m.If(~dbg.core_stop_o & ~core_rst):
513 comb += fetch_pc_valid_i.eq(1) # tell fetch to start
514 with m.If(fetch_pc_ready_o): # fetch acknowledged us
515 m.next = "INSN_WAIT"
516 with m.Else():
517 # tell core it's stopped, and acknowledge debug handshake
518 comb += core.core_stopped_i.eq(1)
519 comb += dbg.core_stopped_i.eq(1)
520 # while stopped, allow updating the PC and SVSTATE
521 with m.If(self.pc_i.ok):
522 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
523 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
524 sync += pc_changed.eq(1)
525 with m.If(self.svstate_i.ok):
526 comb += new_svstate.eq(self.svstate_i.data)
527 comb += update_svstate.eq(1)
528 sync += sv_changed.eq(1)
529
530 # decode the instruction when it arrives
531 with m.State("INSN_WAIT"):
532 comb += fetch_insn_ready_i.eq(1)
533 with m.If(fetch_insn_valid_o):
534 # decode the instruction
535 sync += core.e.eq(pdecode2.e)
536 sync += core.state.eq(cur_state)
537 sync += core.raw_insn_i.eq(dec_opcode_i)
538 sync += core.bigendian_i.eq(self.core_bigendian_i)
539 # set RA_OR_ZERO detection in satellite decoders
540 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
541 # loop into ISSUE_START if it's a SVP64 instruction
542 # and VL == 0. this because VL==0 is a for-loop
543 # from 0 to 0 i.e. always, always a NOP.
544 cur_vl = cur_state.svstate.vl
545 with m.If(is_svp64_mode & (cur_vl == 0)):
546 # update the PC before fetching the next instruction
547 # since we are in a VL==0 loop, no instruction was
548 # executed that we could be overwriting
549 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
550 comb += self.state_w_pc.data_i.eq(nia)
551 comb += self.insn_done.eq(1)
552 m.next = "ISSUE_START"
553 with m.Else():
554 m.next = "PRED_START" # start fetching the predicate
555
556 with m.State("PRED_START"):
557 comb += pred_insn_valid_i.eq(1) # tell fetch_pred to start
558 with m.If(pred_insn_ready_o): # fetch_pred acknowledged us
559 m.next = "MASK_WAIT"
560
561 with m.State("MASK_WAIT"):
562 comb += pred_mask_ready_i.eq(1) # ready to receive the masks
563 with m.If(pred_mask_valid_o): # predication masks are ready
564 m.next = "INSN_EXECUTE"
565
566 # handshake with execution FSM, move to "wait" once acknowledged
567 with m.State("INSN_EXECUTE"):
568 # with m.If(is_svp64_mode):
569 # TODO advance src/dst step to "skip" over predicated-out
570 # from self.srcmask and self.dstmask
571 # https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
572 # but still without exceeding VL in either case
573 # IMPORTANT: when changing src/dest step, have to
574 # jump to m.next = "DECODE_SV" to deal with the change in
575 # SVSTATE
576
577 with m.If(is_svp64_mode):
578
579 pred_src_zero = pdecode2.rm_dec.pred_sz
580 pred_dst_zero = pdecode2.rm_dec.pred_dz
581
582 """
583 if not pred_src_zero:
584 if (((1<<cur_srcstep) & self.srcmask) == 0) and
585 (cur_srcstep != vl):
586 comb += update_svstate.eq(1)
587 comb += new_svstate.srcstep.eq(next_srcstep)
588 sync += sv_changed.eq(1)
589
590 if not pred_dst_zero:
591 if (((1<<cur_dststep) & self.dstmask) == 0) and
592 (cur_dststep != vl):
593 comb += new_svstate.dststep.eq(next_dststep)
594 comb += update_svstate.eq(1)
595 sync += sv_changed.eq(1)
596
597 if update_svstate:
598 m.next = "DECODE_SV"
599 """
600
601 comb += exec_insn_valid_i.eq(1) # trigger execute
602 with m.If(exec_insn_ready_o): # execute acknowledged us
603 m.next = "EXECUTE_WAIT"
604
605 with m.State("EXECUTE_WAIT"):
606 # wait on "core stop" release, at instruction end
607 # need to do this here, in case we are in a VL>1 loop
608 with m.If(~dbg.core_stop_o & ~core_rst):
609 comb += exec_pc_ready_i.eq(1)
610 with m.If(exec_pc_valid_o):
611
612 # was this the last loop iteration?
613 is_last = Signal()
614 cur_vl = cur_state.svstate.vl
615 comb += is_last.eq(next_srcstep == cur_vl)
616
617 # if either PC or SVSTATE were changed by the previous
618 # instruction, go directly back to Fetch, without
619 # updating either PC or SVSTATE
620 with m.If(pc_changed | sv_changed):
621 m.next = "ISSUE_START"
622
623 # also return to Fetch, when no output was a vector
624 # (regardless of SRCSTEP and VL), or when the last
625 # instruction was really the last one of the VL loop
626 with m.Elif((~pdecode2.loop_continue) | is_last):
627 # before going back to fetch, update the PC state
628 # register with the NIA.
629 # ok here we are not reading the branch unit.
630 # TODO: this just blithely overwrites whatever
631 # pipeline updated the PC
632 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
633 comb += self.state_w_pc.data_i.eq(nia)
634 # reset SRCSTEP before returning to Fetch
635 with m.If(pdecode2.loop_continue):
636 comb += new_svstate.srcstep.eq(0)
637 comb += new_svstate.dststep.eq(0)
638 comb += update_svstate.eq(1)
639 m.next = "ISSUE_START"
640
641 # returning to Execute? then, first update SRCSTEP
642 with m.Else():
643 comb += new_svstate.srcstep.eq(next_srcstep)
644 comb += new_svstate.dststep.eq(next_dststep)
645 comb += update_svstate.eq(1)
646 m.next = "DECODE_SV"
647
648 with m.Else():
649 comb += core.core_stopped_i.eq(1)
650 comb += dbg.core_stopped_i.eq(1)
651 # while stopped, allow updating the PC and SVSTATE
652 with m.If(self.pc_i.ok):
653 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
654 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
655 sync += pc_changed.eq(1)
656 with m.If(self.svstate_i.ok):
657 comb += new_svstate.eq(self.svstate_i.data)
658 comb += update_svstate.eq(1)
659 sync += sv_changed.eq(1)
660
661 # need to decode the instruction again, after updating SRCSTEP
662 # in the previous state.
663 # mostly a copy of INSN_WAIT, but without the actual wait
664 with m.State("DECODE_SV"):
665 # decode the instruction
666 sync += core.e.eq(pdecode2.e)
667 sync += core.state.eq(cur_state)
668 sync += core.bigendian_i.eq(self.core_bigendian_i)
669 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
670 m.next = "INSN_EXECUTE" # move to "execute"
671
672 # check if svstate needs updating: if so, write it to State Regfile
673 with m.If(update_svstate):
674 comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
675 comb += self.state_w_sv.data_i.eq(new_svstate)
676 sync += cur_state.svstate.eq(new_svstate) # for next clock
677
678 def execute_fsm(self, m, core, pc_changed, sv_changed,
679 exec_insn_valid_i, exec_insn_ready_o,
680 exec_pc_valid_o, exec_pc_ready_i):
681 """execute FSM
682
683 execute FSM. this interacts with the "issue" FSM
684 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
685 (outgoing). SVP64 RM prefixes have already been set up by the
686 "issue" phase, so execute is fairly straightforward.
687 """
688
689 comb = m.d.comb
690 sync = m.d.sync
691 pdecode2 = self.pdecode2
692
693 # temporaries
694 core_busy_o = core.busy_o # core is busy
695 core_ivalid_i = core.ivalid_i # instruction is valid
696 core_issue_i = core.issue_i # instruction is issued
697 insn_type = core.e.do.insn_type # instruction MicroOp type
698
699 with m.FSM(name="exec_fsm"):
700
701 # waiting for instruction bus (stays there until not busy)
702 with m.State("INSN_START"):
703 comb += exec_insn_ready_o.eq(1)
704 with m.If(exec_insn_valid_i):
705 comb += core_ivalid_i.eq(1) # instruction is valid
706 comb += core_issue_i.eq(1) # and issued
707 sync += sv_changed.eq(0)
708 sync += pc_changed.eq(0)
709 m.next = "INSN_ACTIVE" # move to "wait completion"
710
711 # instruction started: must wait till it finishes
712 with m.State("INSN_ACTIVE"):
713 with m.If(insn_type != MicrOp.OP_NOP):
714 comb += core_ivalid_i.eq(1) # instruction is valid
715 # note changes to PC and SVSTATE
716 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
717 sync += sv_changed.eq(1)
718 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
719 sync += pc_changed.eq(1)
720 with m.If(~core_busy_o): # instruction done!
721 comb += exec_pc_valid_o.eq(1)
722 with m.If(exec_pc_ready_i):
723 comb += self.insn_done.eq(1)
724 m.next = "INSN_START" # back to fetch
725
726 def setup_peripherals(self, m):
727 comb, sync = m.d.comb, m.d.sync
728
729 m.submodules.core = core = DomainRenamer("coresync")(self.core)
730 m.submodules.imem = imem = self.imem
731 m.submodules.dbg = dbg = self.dbg
732 if self.jtag_en:
733 m.submodules.jtag = jtag = self.jtag
734 # TODO: UART2GDB mux, here, from external pin
735 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
736 sync += dbg.dmi.connect_to(jtag.dmi)
737
738 cur_state = self.cur_state
739
740 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
741 if self.sram4x4k:
742 for i, sram in enumerate(self.sram4k):
743 m.submodules["sram4k_%d" % i] = sram
744 comb += sram.enable.eq(self.wb_sram_en)
745
746 # XICS interrupt handler
747 if self.xics:
748 m.submodules.xics_icp = icp = self.xics_icp
749 m.submodules.xics_ics = ics = self.xics_ics
750 comb += icp.ics_i.eq(ics.icp_o) # connect ICS to ICP
751 sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
752
753 # GPIO test peripheral
754 if self.gpio:
755 m.submodules.simple_gpio = simple_gpio = self.simple_gpio
756
757 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
758 # XXX causes litex ECP5 test to get wrong idea about input and output
759 # (but works with verilator sim *sigh*)
760 #if self.gpio and self.xics:
761 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
762
763 # instruction decoder
764 pdecode = create_pdecode()
765 m.submodules.dec2 = pdecode2 = self.pdecode2
766 if self.svp64_en:
767 m.submodules.svp64 = svp64 = self.svp64
768
769 # convenience
770 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
771 intrf = self.core.regs.rf['int']
772
773 # clock delay power-on reset
774 cd_por = ClockDomain(reset_less=True)
775 cd_sync = ClockDomain()
776 core_sync = ClockDomain("coresync")
777 m.domains += cd_por, cd_sync, core_sync
778
779 ti_rst = Signal(reset_less=True)
780 delay = Signal(range(4), reset=3)
781 with m.If(delay != 0):
782 m.d.por += delay.eq(delay - 1)
783 comb += cd_por.clk.eq(ClockSignal())
784
785 # power-on reset delay
786 core_rst = ResetSignal("coresync")
787 comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
788 comb += core_rst.eq(ti_rst)
789
790 # busy/halted signals from core
791 comb += self.busy_o.eq(core.busy_o)
792 comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
793
794 # temporary hack: says "go" immediately for both address gen and ST
795 l0 = core.l0
796 ldst = core.fus.fus['ldst0']
797 st_go_edge = rising_edge(m, ldst.st.rel_o)
798 m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
799 m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
800
801 return core_rst
802
803 def elaborate(self, platform):
804 m = Module()
805 # convenience
806 comb, sync = m.d.comb, m.d.sync
807 cur_state = self.cur_state
808 pdecode2 = self.pdecode2
809 dbg = self.dbg
810 core = self.core
811
812 # set up peripherals and core
813 core_rst = self.setup_peripherals(m)
814
815 # PC and instruction from I-Memory
816 comb += self.pc_o.eq(cur_state.pc)
817 pc_changed = Signal() # note write to PC
818 sv_changed = Signal() # note write to SVSTATE
819
820 # read state either from incoming override or from regfile
821 # TODO: really should be doing MSR in the same way
822 pc = state_get(m, self.pc_i, "pc", # read PC
823 self.state_r_pc, StateRegs.PC)
824 svstate = state_get(m, self.svstate_i, "svstate", # read SVSTATE
825 self.state_r_sv, StateRegs.SVSTATE)
826
827 # don't write pc every cycle
828 comb += self.state_w_pc.wen.eq(0)
829 comb += self.state_w_pc.data_i.eq(0)
830
831 # don't read msr every cycle
832 comb += self.state_r_msr.ren.eq(0)
833
834 # address of the next instruction, in the absence of a branch
835 # depends on the instruction size
836 nia = Signal(64, reset_less=True)
837
838 # connect up debug signals
839 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
840 comb += dbg.terminate_i.eq(core.core_terminate_o)
841 comb += dbg.state.pc.eq(pc)
842 comb += dbg.state.svstate.eq(svstate)
843 comb += dbg.state.msr.eq(cur_state.msr)
844
845 # pass the prefix mode from Fetch to Issue, so the latter can loop
846 # on VL==0
847 is_svp64_mode = Signal()
848
849 # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
850 # these are the handshake signals between fetch and decode/execute
851
852 # fetch FSM can run as soon as the PC is valid
853 fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
854 fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
855
856 # fetch FSM hands over the instruction to be decoded / issued
857 fetch_insn_valid_o = Signal()
858 fetch_insn_ready_i = Signal()
859
860 # predicate fetch FSM decodes and fetches the predicate
861 pred_insn_valid_i = Signal()
862 pred_insn_ready_o = Signal()
863
864 # predicate fetch FSM delivers the masks
865 pred_mask_valid_o = Signal()
866 pred_mask_ready_i = Signal()
867
868 # issue FSM delivers the instruction to the be executed
869 exec_insn_valid_i = Signal()
870 exec_insn_ready_o = Signal()
871
872 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
873 exec_pc_valid_o = Signal()
874 exec_pc_ready_i = Signal()
875
876 # the FSMs here are perhaps unusual in that they detect conditions
877 # then "hold" information, combinatorially, for the core
878 # (as opposed to using sync - which would be on a clock's delay)
879 # this includes the actual opcode, valid flags and so on.
880
881 # Fetch, then predicate fetch, then Issue, then Execute.
882 # Issue is where the VL for-loop # lives. the ready/valid
883 # signalling is used to communicate between the four.
884
885 self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
886 fetch_pc_ready_o, fetch_pc_valid_i,
887 fetch_insn_valid_o, fetch_insn_ready_i)
888
889 self.issue_fsm(m, core, pc_changed, sv_changed, nia,
890 dbg, core_rst, is_svp64_mode,
891 fetch_pc_ready_o, fetch_pc_valid_i,
892 fetch_insn_valid_o, fetch_insn_ready_i,
893 pred_insn_valid_i, pred_insn_ready_o,
894 pred_mask_valid_o, pred_mask_ready_i,
895 exec_insn_valid_i, exec_insn_ready_o,
896 exec_pc_valid_o, exec_pc_ready_i)
897
898 self.fetch_predicate_fsm(m,
899 pred_insn_valid_i, pred_insn_ready_o,
900 pred_mask_valid_o, pred_mask_ready_i)
901
902 self.execute_fsm(m, core, pc_changed, sv_changed,
903 exec_insn_valid_i, exec_insn_ready_o,
904 exec_pc_valid_o, exec_pc_ready_i)
905
906 # this bit doesn't have to be in the FSM: connect up to read
907 # regfiles on demand from DMI
908 self.do_dmi(m, dbg)
909
910 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
911 # (which uses that in PowerDecoder2 to raise 0x900 exception)
912 self.tb_dec_fsm(m, cur_state.dec)
913
914 return m
915
916 def do_dmi(self, m, dbg):
917 """deals with DMI debug requests
918
919 currently only provides read requests for the INT regfile, CR and XER
920 it will later also deal with *writing* to these regfiles.
921 """
922 comb = m.d.comb
923 sync = m.d.sync
924 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
925 intrf = self.core.regs.rf['int']
926
927 with m.If(d_reg.req): # request for regfile access being made
928 # TODO: error-check this
929 # XXX should this be combinatorial? sync better?
930 if intrf.unary:
931 comb += self.int_r.ren.eq(1<<d_reg.addr)
932 else:
933 comb += self.int_r.addr.eq(d_reg.addr)
934 comb += self.int_r.ren.eq(1)
935 d_reg_delay = Signal()
936 sync += d_reg_delay.eq(d_reg.req)
937 with m.If(d_reg_delay):
938 # data arrives one clock later
939 comb += d_reg.data.eq(self.int_r.data_o)
940 comb += d_reg.ack.eq(1)
941
942 # sigh same thing for CR debug
943 with m.If(d_cr.req): # request for regfile access being made
944 comb += self.cr_r.ren.eq(0b11111111) # enable all
945 d_cr_delay = Signal()
946 sync += d_cr_delay.eq(d_cr.req)
947 with m.If(d_cr_delay):
948 # data arrives one clock later
949 comb += d_cr.data.eq(self.cr_r.data_o)
950 comb += d_cr.ack.eq(1)
951
952 # aaand XER...
953 with m.If(d_xer.req): # request for regfile access being made
954 comb += self.xer_r.ren.eq(0b111111) # enable all
955 d_xer_delay = Signal()
956 sync += d_xer_delay.eq(d_xer.req)
957 with m.If(d_xer_delay):
958 # data arrives one clock later
959 comb += d_xer.data.eq(self.xer_r.data_o)
960 comb += d_xer.ack.eq(1)
961
962 def tb_dec_fsm(self, m, spr_dec):
963 """tb_dec_fsm
964
965 this is a FSM for updating either dec or tb. it runs alternately
966 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
967 value to DEC, however the regfile has "passthrough" on it so this
968 *should* be ok.
969
970 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
971 """
972
973 comb, sync = m.d.comb, m.d.sync
974 fast_rf = self.core.regs.rf['fast']
975 fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
976 fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
977
978 with m.FSM() as fsm:
979
980 # initiates read of current DEC
981 with m.State("DEC_READ"):
982 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
983 comb += fast_r_dectb.ren.eq(1)
984 m.next = "DEC_WRITE"
985
986 # waits for DEC read to arrive (1 cycle), updates with new value
987 with m.State("DEC_WRITE"):
988 new_dec = Signal(64)
989 # TODO: MSR.LPCR 32-bit decrement mode
990 comb += new_dec.eq(fast_r_dectb.data_o - 1)
991 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
992 comb += fast_w_dectb.wen.eq(1)
993 comb += fast_w_dectb.data_i.eq(new_dec)
994 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
995 m.next = "TB_READ"
996
997 # initiates read of current TB
998 with m.State("TB_READ"):
999 comb += fast_r_dectb.addr.eq(FastRegs.TB)
1000 comb += fast_r_dectb.ren.eq(1)
1001 m.next = "TB_WRITE"
1002
1003 # waits for read TB to arrive, initiates write of current TB
1004 with m.State("TB_WRITE"):
1005 new_tb = Signal(64)
1006 comb += new_tb.eq(fast_r_dectb.data_o + 1)
1007 comb += fast_w_dectb.addr.eq(FastRegs.TB)
1008 comb += fast_w_dectb.wen.eq(1)
1009 comb += fast_w_dectb.data_i.eq(new_tb)
1010 m.next = "DEC_READ"
1011
1012 return m
1013
1014 def __iter__(self):
1015 yield from self.pc_i.ports()
1016 yield self.pc_o
1017 yield self.memerr_o
1018 yield from self.core.ports()
1019 yield from self.imem.ports()
1020 yield self.core_bigendian_i
1021 yield self.busy_o
1022
1023 def ports(self):
1024 return list(self)
1025
1026 def external_ports(self):
1027 ports = self.pc_i.ports()
1028 ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
1029 ]
1030
1031 if self.jtag_en:
1032 ports += list(self.jtag.external_ports())
1033 else:
1034 # don't add DMI if JTAG is enabled
1035 ports += list(self.dbg.dmi.ports())
1036
1037 ports += list(self.imem.ibus.fields.values())
1038 ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
1039
1040 if self.sram4x4k:
1041 for sram in self.sram4k:
1042 ports += list(sram.bus.fields.values())
1043
1044 if self.xics:
1045 ports += list(self.xics_icp.bus.fields.values())
1046 ports += list(self.xics_ics.bus.fields.values())
1047 ports.append(self.int_level_i)
1048
1049 if self.gpio:
1050 ports += list(self.simple_gpio.bus.fields.values())
1051 ports.append(self.gpio_o)
1052
1053 return ports
1054
1055 def ports(self):
1056 return list(self)
1057
1058
1059 class TestIssuer(Elaboratable):
1060 def __init__(self, pspec):
1061 self.ti = TestIssuerInternal(pspec)
1062
1063 self.pll = DummyPLL()
1064
1065 # PLL direct clock or not
1066 self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
1067 if self.pll_en:
1068 self.pll_18_o = Signal(reset_less=True)
1069
1070 def elaborate(self, platform):
1071 m = Module()
1072 comb = m.d.comb
1073
1074 # TestIssuer runs at direct clock
1075 m.submodules.ti = ti = self.ti
1076 cd_int = ClockDomain("coresync")
1077
1078 if self.pll_en:
1079 # ClockSelect runs at PLL output internal clock rate
1080 m.submodules.pll = pll = self.pll
1081
1082 # add clock domains from PLL
1083 cd_pll = ClockDomain("pllclk")
1084 m.domains += cd_pll
1085
1086 # PLL clock established. has the side-effect of running clklsel
1087 # at the PLL's speed (see DomainRenamer("pllclk") above)
1088 pllclk = ClockSignal("pllclk")
1089 comb += pllclk.eq(pll.clk_pll_o)
1090
1091 # wire up external 24mhz to PLL
1092 comb += pll.clk_24_i.eq(ClockSignal())
1093
1094 # output 18 mhz PLL test signal
1095 comb += self.pll_18_o.eq(pll.pll_18_o)
1096
1097 # now wire up ResetSignals. don't mind them being in this domain
1098 pll_rst = ResetSignal("pllclk")
1099 comb += pll_rst.eq(ResetSignal())
1100
1101 # internal clock is set to selector clock-out. has the side-effect of
1102 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1103 intclk = ClockSignal("coresync")
1104 if self.pll_en:
1105 comb += intclk.eq(pll.clk_pll_o)
1106 else:
1107 comb += intclk.eq(ClockSignal())
1108
1109 return m
1110
1111 def ports(self):
1112 return list(self.ti.ports()) + list(self.pll.ports()) + \
1113 [ClockSignal(), ResetSignal()]
1114
1115 def external_ports(self):
1116 ports = self.ti.external_ports()
1117 ports.append(ClockSignal())
1118 ports.append(ResetSignal())
1119 if self.pll_en:
1120 ports.append(self.pll.clk_sel_i)
1121 ports.append(self.pll_18_o)
1122 ports.append(self.pll.pll_lck_o)
1123 return ports
1124
1125
1126 if __name__ == '__main__':
1127 units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1128 'spr': 1,
1129 'div': 1,
1130 'mul': 1,
1131 'shiftrot': 1
1132 }
1133 pspec = TestMemPspec(ldst_ifacetype='bare_wb',
1134 imem_ifacetype='bare_wb',
1135 addr_wid=48,
1136 mask_wid=8,
1137 reg_wid=64,
1138 units=units)
1139 dut = TestIssuer(pspec)
1140 vl = main(dut, ports=dut.ports(), name="test_issuer")
1141
1142 if len(sys.argv) == 1:
1143 vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
1144 with open("test_issuer.il", "w") as f:
1145 f.write(vl)