src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # JTAG interface.  add this right at the start because if it's
  64         # added it *modifies* the pspec, by adding enable/disable signals
  65         # for parts of the rest of the core
  66         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  67         if self.jtag_en:
  68             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  69                       'pwm', 'sd0', 'sdr'}
  70             self.jtag = JTAG(get_pinspecs(subset=subset))
  71             # add signals to pspec to enable/disable icache and dcache
  72             # (or data and intstruction wishbone if icache/dcache not included)
  73             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  74             # TODO: do we actually care if these are not domain-synchronised?
  75             # honestly probably not.
  76             pspec.wb_icache_en = self.jtag.wb_icache_en
  77             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  78             self.wb_sram_en = self.jtag.wb_sram_en
  79         else:
  80             self.wb_sram_en = Const(1)
  81
  82         # add 4k sram blocks?
  83         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  84                          pspec.sram4x4kblock == True)
  85         if self.sram4x4k:
  86             self.sram4k = []
  87             for i in range(4):
  88                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i))
  89
  90         # add interrupt controller?
  91         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  92         if self.xics:
  93             self.xics_icp = XICS_ICP()
  94             self.xics_ics = XICS_ICS()
  95             self.int_level_i = self.xics_ics.int_level_i
  96
  97         # add GPIO peripheral?
  98         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
  99         if self.gpio:
 100             self.simple_gpio = SimpleGPIO()
 101             self.gpio_o = self.simple_gpio.gpio_o
 102
 103         # main instruction core25
 104         self.core = core = NonProductionCore(pspec)
 105
 106         # instruction decoder.  goes into Trap Record
 107         pdecode = create_pdecode()
 108         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 109         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 110                                      opkls=IssuerDecode2ToOperand)
 111         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 112
 113         # Test Instruction memory
 114         self.imem = ConfigFetchUnit(pspec).fu
 115         # one-row cache of instruction read
 116         self.iline = Signal(64) # one instruction line
 117         self.iprev_adr = Signal(64) # previous address: if different, do read
 118
 119         # DMI interface
 120         self.dbg = CoreDebug()
 121
 122         # instruction go/monitor
 123         self.pc_o = Signal(64, reset_less=True)
 124         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 125         self.svstate_i = Data(32, "svstate_i") # ditto
 126         self.core_bigendian_i = Signal()
 127         self.busy_o = Signal(reset_less=True)
 128         self.memerr_o = Signal(reset_less=True)
 129
 130         # STATE regfile read /write ports for PC, MSR, SVSTATE
 131         staterf = self.core.regs.rf['state']
 132         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 133         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 134         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 135         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 136         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 137
 138         # DMI interface access
 139         intrf = self.core.regs.rf['int']
 140         crrf = self.core.regs.rf['cr']
 141         xerrf = self.core.regs.rf['xer']
 142         self.int_r = intrf.r_ports['dmi'] # INT read
 143         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 144         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 145
 146         # hack method of keeping an eye on whether branch/trap set the PC
 147         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 148         self.state_nia.wen.name = 'state_nia_wen'
 149
 150     def fetch_fsm(self, m, core, pc, svstate, pc_changed, insn_done,
 151                         fetch_pc_ready_o, fetch_pc_valid_i,
 152                         fetch_insn_valid_o, fetch_insn_ready_i):
 153         """fetch FSM
 154         this FSM performs fetch of raw instruction data, partial-decodes
 155         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 156         read a 2nd 32-bit quantity if that occurs.
 157         """
 158         comb = m.d.comb
 159         sync = m.d.sync
 160         pdecode2 = self.pdecode2
 161         svp64 = self.svp64
 162         cur_state = self.cur_state
 163
 164         # latches copy of raw fetched instruction
 165         fetch_insn_o = Signal(32, reset_less=True)
 166         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 167         sync += dec_opcode_i.eq(fetch_insn_o)  # actual opcode
 168
 169         msr_read = Signal(reset=1)
 170
 171         # address of the next instruction, in the absence of a branch
 172         # depends on the instruction size
 173         nia = Signal(64, reset_less=True)
 174
 175         with m.FSM(name='fetch_fsm'):
 176
 177             # waiting (zzz)
 178             with m.State("IDLE"):
 179                 comb += fetch_pc_ready_o.eq(1)
 180                 with m.If(fetch_pc_valid_i):
 181                     # instruction allowed to go: start by reading the PC
 182                     # capture the PC and also drop it into Insn Memory
 183                     # we have joined a pair of combinatorial memory
 184                     # lookups together.  this is Generally Bad.
 185                     comb += self.imem.a_pc_i.eq(pc)
 186                     comb += self.imem.a_valid_i.eq(1)
 187                     comb += self.imem.f_valid_i.eq(1)
 188                     sync += cur_state.pc.eq(pc)
 189                     sync += cur_state.svstate.eq(svstate) # and svstate
 190
 191                     # initiate read of MSR. arrives one clock later
 192                     comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 193                     sync += msr_read.eq(0)
 194
 195                     m.next = "INSN_READ"  # move to "wait for bus" phase
 196
 197             # dummy pause to find out why simulation is not keeping up
 198             with m.State("INSN_READ"):
 199                 # one cycle later, msr/sv read arrives.  valid only once.
 200                 with m.If(~msr_read):
 201                     sync += msr_read.eq(1) # yeah don't read it again
 202                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 203                 with m.If(self.imem.f_busy_o): # zzz...
 204                     # busy: stay in wait-read
 205                     comb += self.imem.a_valid_i.eq(1)
 206                     comb += self.imem.f_valid_i.eq(1)
 207                 with m.Else():
 208                     # not busy: instruction fetched
 209                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 210                     # decode the SVP64 prefix, if any
 211                     comb += svp64.raw_opcode_in.eq(insn)
 212                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 213                     # pass the decoded prefix (if any) to PowerDecoder2
 214                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 215                     # calculate the address of the following instruction
 216                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 217                     sync += nia.eq(cur_state.pc + insn_size)
 218                     with m.If(~svp64.is_svp64_mode):
 219                         # with no prefix, store the instruction
 220                         # and hand it directly to the next FSM
 221                         comb += fetch_insn_o.eq(insn)
 222                         m.next = "INSN_READY"
 223                     with m.Else():
 224                         # fetch the rest of the instruction from memory
 225                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 226                         comb += self.imem.a_valid_i.eq(1)
 227                         comb += self.imem.f_valid_i.eq(1)
 228                         m.next = "INSN_READ2"
 229
 230             with m.State("INSN_READ2"):
 231                 with m.If(self.imem.f_busy_o):  # zzz...
 232                     # busy: stay in wait-read
 233                     comb += self.imem.a_valid_i.eq(1)
 234                     comb += self.imem.f_valid_i.eq(1)
 235                 with m.Else():
 236                     # not busy: instruction fetched
 237                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 238                     comb += fetch_insn_o.eq(insn)
 239                     m.next = "INSN_READY"
 240
 241             with m.State("INSN_READY"):
 242                 # hand over the instruction, to be decoded
 243                 comb += fetch_insn_valid_o.eq(1)
 244                 with m.If(fetch_insn_ready_i):
 245                     m.next = "IDLE"
 246
 247         # code-morph: moving the actual PC-setting out of "execute"
 248         # so that it's easier to move this into an "issue" FSM.
 249
 250         # ok here we are not reading the branch unit.  TODO
 251         # this just blithely overwrites whatever pipeline
 252         # updated the PC
 253         core_busy_o = core.busy_o                 # core is busy
 254         with m.If(insn_done & (~pc_changed) & (~core_busy_o)):
 255             comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 256             comb += self.state_w_pc.data_i.eq(nia)
 257
 258     def issue_fsm(self, m, core, pc_changed, sv_changed,
 259                   dbg, core_rst,
 260                   fetch_pc_ready_o, fetch_pc_valid_i,
 261                   fetch_insn_valid_o, fetch_insn_ready_i,
 262                   exec_insn_valid_i, exec_insn_ready_o,
 263                   exec_pc_valid_o, exec_pc_ready_i):
 264         """issue FSM
 265
 266         decode / issue FSM.  this interacts with the "fetch" FSM
 267         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 268         (outgoing). also interacts with the "execute" FSM
 269         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 270         (incoming).
 271         SVP64 RM prefixes have already been set up by the
 272         "fetch" phase, so execute is fairly straightforward.
 273         """
 274
 275         comb = m.d.comb
 276         sync = m.d.sync
 277         pdecode2 = self.pdecode2
 278         cur_state = self.cur_state
 279
 280         # temporaries
 281         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 282
 283         # for updating svstate (things like srcstep etc.)
 284         update_svstate = Signal() # set this (below) if updating
 285         new_svstate = SVSTATERec("new_svstate")
 286         comb += new_svstate.eq(cur_state.svstate)
 287
 288         with m.FSM(name="issue_fsm"):
 289
 290             # Wait on "core stop" release, at reset
 291             with m.State("WAIT_RESET"):
 292                 with m.If(~dbg.core_stop_o & ~core_rst):
 293                     m.next = "INSN_FETCH"
 294                 with m.Else():
 295                     comb += core.core_stopped_i.eq(1)
 296                     comb += dbg.core_stopped_i.eq(1)
 297
 298             # go fetch the instruction at the current PC
 299             # at this point, there is no instruction running, that
 300             # could inadvertently update the PC.
 301             with m.State("INSN_FETCH"):
 302                 # TODO: update PC here, before fetch
 303                 comb += fetch_pc_valid_i.eq(1)
 304                 with m.If(fetch_pc_ready_o):
 305                     m.next = "INSN_WAIT"
 306
 307             # decode the instruction when it arrives
 308             with m.State("INSN_WAIT"):
 309                 comb += fetch_insn_ready_i.eq(1)
 310                 with m.If(fetch_insn_valid_o):
 311                     # decode the instruction
 312                     sync += core.e.eq(pdecode2.e)
 313                     sync += core.state.eq(cur_state)
 314                     sync += core.raw_insn_i.eq(dec_opcode_i)
 315                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 316                     # TODO: loop into INSN_FETCH if it's a vector instruction
 317                     #       and VL == 0.  this because VL==0 is a for-loop
 318                     #       from 0 to 0 i.e. always, always a NOP.
 319                     m.next = "INSN_EXECUTE"  # move to "execute"
 320
 321             with m.State("INSN_EXECUTE"):
 322                 comb += exec_insn_valid_i.eq(1)
 323                 with m.If(exec_insn_ready_o):
 324                     m.next = "EXECUTE_WAIT"
 325
 326             with m.State("EXECUTE_WAIT"):
 327                 # wait on "core stop" release, at instruction end
 328                 with m.If(~dbg.core_stop_o & ~core_rst):
 329                     comb += exec_pc_ready_i.eq(1)
 330                     with m.If(exec_pc_valid_o):
 331                         # TODO: update SRCSTEP here (in new_svstate)
 332                         #       and set update_svstate to True *as long as*
 333                         #       PC / SVSTATE was not modified.  that's an
 334                         #       exception (or setvl was called)
 335                         # TODO: loop into INSN_EXECUTE if it's a vector
 336                         #       instruction and SRCSTEP != VL-1 and
 337                         #       PowerDecoder.no_out_vec is True
 338                         #       unless PC / SVSTATE was modified, in that
 339                         #       case do go back to INSN_FETCH.
 340                         m.next = "INSN_FETCH"
 341                 with m.Else():
 342                     comb += core.core_stopped_i.eq(1)
 343                     comb += dbg.core_stopped_i.eq(1)
 344
 345         # check if svstate needs updating: if so, write it to State Regfile
 346         with m.If(update_svstate):
 347             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 348             comb += self.state_w_sv.data_i.eq(new_svstate)
 349             sync += cur_state.svstate.eq(new_svstate) # for next clock
 350
 351     def execute_fsm(self, m, core, insn_done, pc_changed, sv_changed,
 352                     exec_insn_valid_i, exec_insn_ready_o,
 353                     exec_pc_valid_o, exec_pc_ready_i):
 354         """execute FSM
 355
 356         execute FSM. this interacts with the "issue" FSM
 357         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 358         (outgoing). SVP64 RM prefixes have already been set up by the
 359         "issue" phase, so execute is fairly straightforward.
 360         """
 361
 362         comb = m.d.comb
 363         sync = m.d.sync
 364         pdecode2 = self.pdecode2
 365         svp64 = self.svp64
 366
 367         # temporaries
 368         core_busy_o = core.busy_o                 # core is busy
 369         core_ivalid_i = core.ivalid_i             # instruction is valid
 370         core_issue_i = core.issue_i               # instruction is issued
 371         insn_type = core.e.do.insn_type           # instruction MicroOp type
 372
 373         with m.FSM(name="exec_fsm"):
 374
 375             # waiting for instruction bus (stays there until not busy)
 376             with m.State("INSN_START"):
 377                 comb += exec_insn_ready_o.eq(1)
 378                 with m.If(exec_insn_valid_i):
 379                     comb += core_ivalid_i.eq(1)  # instruction is valid
 380                     comb += core_issue_i.eq(1)  # and issued
 381                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 382
 383             # instruction started: must wait till it finishes
 384             with m.State("INSN_ACTIVE"):
 385                 with m.If(insn_type != MicrOp.OP_NOP):
 386                     comb += core_ivalid_i.eq(1) # instruction is valid
 387                 # note changes to PC and SVSTATE
 388                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 389                     sync += sv_changed.eq(1)
 390                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 391                     sync += pc_changed.eq(1)
 392                 with m.If(~core_busy_o): # instruction done!
 393                     comb += insn_done.eq(1)
 394                     sync += core.e.eq(0)
 395                     sync += core.raw_insn_i.eq(0)
 396                     sync += core.bigendian_i.eq(0)
 397                     sync += sv_changed.eq(0)
 398                     sync += pc_changed.eq(0)
 399                     comb += exec_pc_valid_o.eq(1)
 400                     with m.If(exec_pc_ready_i):
 401                         m.next = "INSN_START"  # back to fetch
 402
 403     def elaborate(self, platform):
 404         m = Module()
 405         comb, sync = m.d.comb, m.d.sync
 406
 407         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 408         m.submodules.imem = imem = self.imem
 409         m.submodules.dbg = dbg = self.dbg
 410         if self.jtag_en:
 411             m.submodules.jtag = jtag = self.jtag
 412             # TODO: UART2GDB mux, here, from external pin
 413             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 414             sync += dbg.dmi.connect_to(jtag.dmi)
 415
 416         cur_state = self.cur_state
 417
 418         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 419         if self.sram4x4k:
 420             for i, sram in enumerate(self.sram4k):
 421                 m.submodules["sram4k_%d" % i] = sram
 422                 comb += sram.enable.eq(self.wb_sram_en)
 423
 424         # XICS interrupt handler
 425         if self.xics:
 426             m.submodules.xics_icp = icp = self.xics_icp
 427             m.submodules.xics_ics = ics = self.xics_ics
 428             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 429             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 430
 431         # GPIO test peripheral
 432         if self.gpio:
 433             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 434
 435         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 436         # XXX causes litex ECP5 test to get wrong idea about input and output
 437         # (but works with verilator sim *sigh*)
 438         #if self.gpio and self.xics:
 439         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 440
 441         # instruction decoder
 442         pdecode = create_pdecode()
 443         m.submodules.dec2 = pdecode2 = self.pdecode2
 444         m.submodules.svp64 = svp64 = self.svp64
 445
 446         # convenience
 447         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 448         intrf = self.core.regs.rf['int']
 449
 450         # clock delay power-on reset
 451         cd_por  = ClockDomain(reset_less=True)
 452         cd_sync = ClockDomain()
 453         core_sync = ClockDomain("coresync")
 454         m.domains += cd_por, cd_sync, core_sync
 455
 456         ti_rst = Signal(reset_less=True)
 457         delay = Signal(range(4), reset=3)
 458         with m.If(delay != 0):
 459             m.d.por += delay.eq(delay - 1)
 460         comb += cd_por.clk.eq(ClockSignal())
 461
 462         # power-on reset delay
 463         core_rst = ResetSignal("coresync")
 464         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 465         comb += core_rst.eq(ti_rst)
 466
 467         # busy/halted signals from core
 468         comb += self.busy_o.eq(core.busy_o)
 469         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 470
 471         # temporary hack: says "go" immediately for both address gen and ST
 472         l0 = core.l0
 473         ldst = core.fus.fus['ldst0']
 474         st_go_edge = rising_edge(m, ldst.st.rel_o)
 475         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 476         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 477
 478         # PC and instruction from I-Memory
 479         comb += self.pc_o.eq(cur_state.pc)
 480         pc_changed = Signal() # note write to PC
 481         sv_changed = Signal() # note write to SVSTATE
 482         insn_done = Signal()  # fires just once
 483
 484         # read the PC
 485         pc = Signal(64, reset_less=True)
 486         pc_ok_delay = Signal()
 487         sync += pc_ok_delay.eq(~self.pc_i.ok)
 488         with m.If(self.pc_i.ok):
 489             # incoming override (start from pc_i)
 490             comb += pc.eq(self.pc_i.data)
 491         with m.Else():
 492             # otherwise read StateRegs regfile for PC...
 493             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 494         # ... but on a 1-clock delay
 495         with m.If(pc_ok_delay):
 496             comb += pc.eq(self.state_r_pc.data_o)
 497
 498         # read svstate
 499         svstate = Signal(64, reset_less=True)
 500         svstate_ok_delay = Signal()
 501         sync += svstate_ok_delay.eq(~self.svstate_i.ok)
 502         with m.If(self.svstate_i.ok):
 503             # incoming override (start from svstate__i)
 504             comb += svstate.eq(self.svstate_i.data)
 505         with m.Else():
 506             # otherwise read StateRegs regfile for SVSTATE...
 507             comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 508         # ... but on a 1-clock delay
 509         with m.If(svstate_ok_delay):
 510             comb += svstate.eq(self.state_r_sv.data_o)
 511
 512         # don't write pc every cycle
 513         comb += self.state_w_pc.wen.eq(0)
 514         comb += self.state_w_pc.data_i.eq(0)
 515
 516         # don't read msr every cycle
 517         comb += self.state_r_msr.ren.eq(0)
 518
 519         # connect up debug signals
 520         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 521         comb += dbg.terminate_i.eq(core.core_terminate_o)
 522         comb += dbg.state.pc.eq(pc)
 523         comb += dbg.state.svstate.eq(svstate)
 524         comb += dbg.state.msr.eq(cur_state.msr)
 525
 526         # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
 527         # these are the handshake signals between fetch and decode/execute
 528
 529         # fetch FSM can run as soon as the PC is valid
 530         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 531         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 532
 533         # fetch FSM hands over the instruction to be decoded / issued
 534         fetch_insn_valid_o = Signal()
 535         fetch_insn_ready_i = Signal()
 536
 537         # issue FSM delivers the instruction to the be executed
 538         exec_insn_valid_i = Signal()
 539         exec_insn_ready_o = Signal()
 540
 541         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 542         exec_pc_valid_o = Signal()
 543         exec_pc_ready_i = Signal()
 544
 545         # actually use a nmigen FSM for the first time (w00t)
 546         # this FSM is perhaps unusual in that it detects conditions
 547         # then "holds" information, combinatorially, for the core
 548         # (as opposed to using sync - which would be on a clock's delay)
 549         # this includes the actual opcode, valid flags and so on.
 550
 551         self.fetch_fsm(m, core, pc, svstate, pc_changed, insn_done,
 552                        fetch_pc_ready_o, fetch_pc_valid_i,
 553                        fetch_insn_valid_o, fetch_insn_ready_i)
 554
 555         # TODO: an SVSTATE-based for-loop FSM that goes in between
 556         # fetch pc/insn ready/valid and advances SVSTATE.srcstep
 557         # until it reaches VL-1 or PowerDecoder2.no_out_vec is True.
 558         self.issue_fsm(m, core, pc_changed, sv_changed,
 559                        dbg, core_rst,
 560                        fetch_pc_ready_o, fetch_pc_valid_i,
 561                        fetch_insn_valid_o, fetch_insn_ready_i,
 562                        exec_insn_valid_i, exec_insn_ready_o,
 563                        exec_pc_ready_i, exec_pc_valid_o)
 564
 565         self.execute_fsm(m, core, insn_done, pc_changed, sv_changed,
 566                          exec_insn_valid_i, exec_insn_ready_o,
 567                          exec_pc_ready_i, exec_pc_valid_o)
 568
 569         # this bit doesn't have to be in the FSM: connect up to read
 570         # regfiles on demand from DMI
 571         with m.If(d_reg.req): # request for regfile access being made
 572             # TODO: error-check this
 573             # XXX should this be combinatorial?  sync better?
 574             if intrf.unary:
 575                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 576             else:
 577                 comb += self.int_r.addr.eq(d_reg.addr)
 578                 comb += self.int_r.ren.eq(1)
 579         d_reg_delay  = Signal()
 580         sync += d_reg_delay.eq(d_reg.req)
 581         with m.If(d_reg_delay):
 582             # data arrives one clock later
 583             comb += d_reg.data.eq(self.int_r.data_o)
 584             comb += d_reg.ack.eq(1)
 585
 586         # sigh same thing for CR debug
 587         with m.If(d_cr.req): # request for regfile access being made
 588             comb += self.cr_r.ren.eq(0b11111111) # enable all
 589         d_cr_delay  = Signal()
 590         sync += d_cr_delay.eq(d_cr.req)
 591         with m.If(d_cr_delay):
 592             # data arrives one clock later
 593             comb += d_cr.data.eq(self.cr_r.data_o)
 594             comb += d_cr.ack.eq(1)
 595
 596         # aaand XER...
 597         with m.If(d_xer.req): # request for regfile access being made
 598             comb += self.xer_r.ren.eq(0b111111) # enable all
 599         d_xer_delay  = Signal()
 600         sync += d_xer_delay.eq(d_xer.req)
 601         with m.If(d_xer_delay):
 602             # data arrives one clock later
 603             comb += d_xer.data.eq(self.xer_r.data_o)
 604             comb += d_xer.ack.eq(1)
 605
 606         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 607         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 608         self.tb_dec_fsm(m, cur_state.dec)
 609
 610         return m
 611
 612     def tb_dec_fsm(self, m, spr_dec):
 613         """tb_dec_fsm
 614
 615         this is a FSM for updating either dec or tb.  it runs alternately
 616         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 617         value to DEC, however the regfile has "passthrough" on it so this
 618         *should* be ok.
 619
 620         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 621         """
 622
 623         comb, sync = m.d.comb, m.d.sync
 624         fast_rf = self.core.regs.rf['fast']
 625         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 626         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 627
 628         with m.FSM() as fsm:
 629
 630             # initiates read of current DEC
 631             with m.State("DEC_READ"):
 632                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 633                 comb += fast_r_dectb.ren.eq(1)
 634                 m.next = "DEC_WRITE"
 635
 636             # waits for DEC read to arrive (1 cycle), updates with new value
 637             with m.State("DEC_WRITE"):
 638                 new_dec = Signal(64)
 639                 # TODO: MSR.LPCR 32-bit decrement mode
 640                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 641                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 642                 comb += fast_w_dectb.wen.eq(1)
 643                 comb += fast_w_dectb.data_i.eq(new_dec)
 644                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 645                 m.next = "TB_READ"
 646
 647             # initiates read of current TB
 648             with m.State("TB_READ"):
 649                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 650                 comb += fast_r_dectb.ren.eq(1)
 651                 m.next = "TB_WRITE"
 652
 653             # waits for read TB to arrive, initiates write of current TB
 654             with m.State("TB_WRITE"):
 655                 new_tb = Signal(64)
 656                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 657                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 658                 comb += fast_w_dectb.wen.eq(1)
 659                 comb += fast_w_dectb.data_i.eq(new_tb)
 660                 m.next = "DEC_READ"
 661
 662         return m
 663
 664     def __iter__(self):
 665         yield from self.pc_i.ports()
 666         yield self.pc_o
 667         yield self.memerr_o
 668         yield from self.core.ports()
 669         yield from self.imem.ports()
 670         yield self.core_bigendian_i
 671         yield self.busy_o
 672
 673     def ports(self):
 674         return list(self)
 675
 676     def external_ports(self):
 677         ports = self.pc_i.ports()
 678         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 679                 ]
 680
 681         if self.jtag_en:
 682             ports += list(self.jtag.external_ports())
 683         else:
 684             # don't add DMI if JTAG is enabled
 685             ports += list(self.dbg.dmi.ports())
 686
 687         ports += list(self.imem.ibus.fields.values())
 688         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 689
 690         if self.sram4x4k:
 691             for sram in self.sram4k:
 692                 ports += list(sram.bus.fields.values())
 693
 694         if self.xics:
 695             ports += list(self.xics_icp.bus.fields.values())
 696             ports += list(self.xics_ics.bus.fields.values())
 697             ports.append(self.int_level_i)
 698
 699         if self.gpio:
 700             ports += list(self.simple_gpio.bus.fields.values())
 701             ports.append(self.gpio_o)
 702
 703         return ports
 704
 705     def ports(self):
 706         return list(self)
 707
 708
 709 class TestIssuer(Elaboratable):
 710     def __init__(self, pspec):
 711         self.ti = TestIssuerInternal(pspec)
 712
 713         self.pll = DummyPLL()
 714
 715         # PLL direct clock or not
 716         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 717         if self.pll_en:
 718             self.pll_18_o = Signal(reset_less=True)
 719
 720     def elaborate(self, platform):
 721         m = Module()
 722         comb = m.d.comb
 723
 724         # TestIssuer runs at direct clock
 725         m.submodules.ti = ti = self.ti
 726         cd_int = ClockDomain("coresync")
 727
 728         if self.pll_en:
 729             # ClockSelect runs at PLL output internal clock rate
 730             m.submodules.pll = pll = self.pll
 731
 732             # add clock domains from PLL
 733             cd_pll = ClockDomain("pllclk")
 734             m.domains += cd_pll
 735
 736             # PLL clock established.  has the side-effect of running clklsel
 737             # at the PLL's speed (see DomainRenamer("pllclk") above)
 738             pllclk = ClockSignal("pllclk")
 739             comb += pllclk.eq(pll.clk_pll_o)
 740
 741             # wire up external 24mhz to PLL
 742             comb += pll.clk_24_i.eq(ClockSignal())
 743
 744             # output 18 mhz PLL test signal
 745             comb += self.pll_18_o.eq(pll.pll_18_o)
 746
 747             # now wire up ResetSignals.  don't mind them being in this domain
 748             pll_rst = ResetSignal("pllclk")
 749             comb += pll_rst.eq(ResetSignal())
 750
 751         # internal clock is set to selector clock-out.  has the side-effect of
 752         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 753         intclk = ClockSignal("coresync")
 754         if self.pll_en:
 755             comb += intclk.eq(pll.clk_pll_o)
 756         else:
 757             comb += intclk.eq(ClockSignal())
 758
 759         return m
 760
 761     def ports(self):
 762         return list(self.ti.ports()) + list(self.pll.ports()) + \
 763                [ClockSignal(), ResetSignal()]
 764
 765     def external_ports(self):
 766         ports = self.ti.external_ports()
 767         ports.append(ClockSignal())
 768         ports.append(ResetSignal())
 769         if self.pll_en:
 770             ports.append(self.pll.clk_sel_i)
 771             ports.append(self.pll_18_o)
 772             ports.append(self.pll.pll_lck_o)
 773         return ports
 774
 775
 776 if __name__ == '__main__':
 777     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 778              'spr': 1,
 779              'div': 1,
 780              'mul': 1,
 781              'shiftrot': 1
 782             }
 783     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 784                          imem_ifacetype='bare_wb',
 785                          addr_wid=48,
 786                          mask_wid=8,
 787                          reg_wid=64,
 788                          units=units)
 789     dut = TestIssuer(pspec)
 790     vl = main(dut, ports=dut.ports(), name="test_issuer")
 791
 792     if len(sys.argv) == 1:
 793         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 794         with open("test_issuer.il", "w") as f:
 795             f.write(vl)