src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const, Repl, Cat)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from nmutil.singlepipe import ControlBase
  25 from soc.simple.core_data import FetchOutput, FetchInput
  26
  27 from nmigen.lib.coding import PriorityEncoder
  28
  29 from openpower.decoder.power_decoder import create_pdecode
  30 from openpower.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  31 from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
  32 from openpower.decoder.decode2execute1 import Data
  33 from openpower.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
  34                                            SVP64PredMode)
  35 from openpower.state import CoreState
  36 from openpower.consts import (CR, SVP64CROffs, MSR)
  37 from soc.experiment.testmem import TestMemory  # test only for instructions
  38 from soc.regfile.regfiles import StateRegs, FastRegs
  39 from soc.simple.core import NonProductionCore
  40 from soc.config.test.test_loadstore import TestMemPspec
  41 from soc.config.ifetch import ConfigFetchUnit
  42 from soc.debug.dmi import CoreDebug, DMIInterface
  43 from soc.debug.jtag import JTAG
  44 from soc.config.pinouts import get_pinspecs
  45 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  46 from soc.bus.simple_gpio import SimpleGPIO
  47 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  48 from soc.clock.select import ClockSelect
  49 from soc.clock.dummypll import DummyPLL
  50 from openpower.sv.svstate import SVSTATERec
  51 from soc.experiment.icache import ICache
  52
  53 from nmutil.util import rising_edge
  54
  55
  56 def get_insn(f_instr_o, pc):
  57     if f_instr_o.width == 32:
  58         return f_instr_o
  59     else:
  60         # 64-bit: bit 2 of pc decides which word to select
  61         return f_instr_o.word_select(pc[2], 32)
  62
  63 # gets state input or reads from state regfile
  64
  65
  66 def state_get(m, res, core_rst, state_i, name, regfile, regnum):
  67     comb = m.d.comb
  68     sync = m.d.sync
  69     # read the {insert state variable here}
  70     res_ok_delay = Signal(name="%s_ok_delay" % name)
  71     with m.If(~core_rst):
  72         sync += res_ok_delay.eq(~state_i.ok)
  73         with m.If(state_i.ok):
  74             # incoming override (start from pc_i)
  75             comb += res.eq(state_i.data)
  76         with m.Else():
  77             # otherwise read StateRegs regfile for {insert state here}...
  78             comb += regfile.ren.eq(1 << regnum)
  79         # ... but on a 1-clock delay
  80         with m.If(res_ok_delay):
  81             comb += res.eq(regfile.o_data)
  82
  83
  84 def get_predint(m, mask, name):
  85     """decode SVP64 predicate integer mask field to reg number and invert
  86     this is identical to the equivalent function in ISACaller except that
  87     it doesn't read the INT directly, it just decodes "what needs to be done"
  88     i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
  89
  90     * all1s is set to indicate that no mask is to be applied.
  91     * regread indicates the GPR register number to be read
  92     * invert is set to indicate that the register value is to be inverted
  93     * unary indicates that the contents of the register is to be shifted 1<<r3
  94     """
  95     comb = m.d.comb
  96     regread = Signal(5, name=name+"regread")
  97     invert = Signal(name=name+"invert")
  98     unary = Signal(name=name+"unary")
  99     all1s = Signal(name=name+"all1s")
 100     with m.Switch(mask):
 101         with m.Case(SVP64PredInt.ALWAYS.value):
 102             comb += all1s.eq(1)      # use 0b1111 (all ones)
 103         with m.Case(SVP64PredInt.R3_UNARY.value):
 104             comb += regread.eq(3)
 105             comb += unary.eq(1)        # 1<<r3 - shift r3 (single bit)
 106         with m.Case(SVP64PredInt.R3.value):
 107             comb += regread.eq(3)
 108         with m.Case(SVP64PredInt.R3_N.value):
 109             comb += regread.eq(3)
 110             comb += invert.eq(1)
 111         with m.Case(SVP64PredInt.R10.value):
 112             comb += regread.eq(10)
 113         with m.Case(SVP64PredInt.R10_N.value):
 114             comb += regread.eq(10)
 115             comb += invert.eq(1)
 116         with m.Case(SVP64PredInt.R30.value):
 117             comb += regread.eq(30)
 118         with m.Case(SVP64PredInt.R30_N.value):
 119             comb += regread.eq(30)
 120             comb += invert.eq(1)
 121     return regread, invert, unary, all1s
 122
 123
 124 def get_predcr(m, mask, name):
 125     """decode SVP64 predicate CR to reg number field and invert status
 126     this is identical to _get_predcr in ISACaller
 127     """
 128     comb = m.d.comb
 129     idx = Signal(2, name=name+"idx")
 130     invert = Signal(name=name+"crinvert")
 131     with m.Switch(mask):
 132         with m.Case(SVP64PredCR.LT.value):
 133             comb += idx.eq(CR.LT)
 134             comb += invert.eq(0)
 135         with m.Case(SVP64PredCR.GE.value):
 136             comb += idx.eq(CR.LT)
 137             comb += invert.eq(1)
 138         with m.Case(SVP64PredCR.GT.value):
 139             comb += idx.eq(CR.GT)
 140             comb += invert.eq(0)
 141         with m.Case(SVP64PredCR.LE.value):
 142             comb += idx.eq(CR.GT)
 143             comb += invert.eq(1)
 144         with m.Case(SVP64PredCR.EQ.value):
 145             comb += idx.eq(CR.EQ)
 146             comb += invert.eq(0)
 147         with m.Case(SVP64PredCR.NE.value):
 148             comb += idx.eq(CR.EQ)
 149             comb += invert.eq(1)
 150         with m.Case(SVP64PredCR.SO.value):
 151             comb += idx.eq(CR.SO)
 152             comb += invert.eq(0)
 153         with m.Case(SVP64PredCR.NS.value):
 154             comb += idx.eq(CR.SO)
 155             comb += invert.eq(1)
 156     return idx, invert
 157
 158
 159 class TestIssuerBase(Elaboratable):
 160     """TestIssuerBase - common base class for Issuers
 161
 162     takes care of power-on reset, peripherals, debug, DEC/TB,
 163     and gets PC/MSR/SVSTATE from the State Regfile etc.
 164     """
 165
 166     def __init__(self, pspec):
 167
 168         # test if microwatt compatibility is to be enabled
 169         self.microwatt_compat = (hasattr(pspec, "microwatt_compat") and
 170                                  (pspec.microwatt_compat == True))
 171         self.alt_reset = Signal(reset_less=True) # not connected yet (microwatt)
 172
 173         # test is SVP64 is to be enabled
 174         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
 175
 176         # and if regfiles are reduced
 177         self.regreduce_en = (hasattr(pspec, "regreduce") and
 178                              (pspec.regreduce == True))
 179
 180         # and if overlap requested
 181         self.allow_overlap = (hasattr(pspec, "allow_overlap") and
 182                               (pspec.allow_overlap == True))
 183
 184         # and get the core domain
 185         self.core_domain = "coresync"
 186         if (hasattr(pspec, "core_domain") and
 187             isinstance(pspec.core_domain, str)):
 188             self.core_domain = pspec.core_domain
 189
 190         # JTAG interface.  add this right at the start because if it's
 191         # added it *modifies* the pspec, by adding enable/disable signals
 192         # for parts of the rest of the core
 193         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
 194         #self.dbg_domain = "sync"  # sigh "dbgsunc" too problematic
 195         self.dbg_domain = "dbgsync" # domain for DMI/JTAG clock
 196         if self.jtag_en:
 197             # XXX MUST keep this up-to-date with litex, and
 198             # soc-cocotb-sim, and err.. all needs sorting out, argh
 199             subset = ['uart',
 200                       'mtwi',
 201                       'eint', 'gpio', 'mspi0',
 202                       # 'mspi1', - disabled for now
 203                       # 'pwm', 'sd0', - disabled for now
 204                       'sdr']
 205             self.jtag = JTAG(get_pinspecs(subset=subset),
 206                              domain=self.dbg_domain)
 207             # add signals to pspec to enable/disable icache and dcache
 208             # (or data and intstruction wishbone if icache/dcache not included)
 209             # https://bugs.libre-soc.org/show_bug.cgi?id=520
 210             # TODO: do we actually care if these are not domain-synchronised?
 211             # honestly probably not.
 212             pspec.wb_icache_en = self.jtag.wb_icache_en
 213             pspec.wb_dcache_en = self.jtag.wb_dcache_en
 214             self.wb_sram_en = self.jtag.wb_sram_en
 215         else:
 216             self.wb_sram_en = Const(1)
 217
 218         # add 4k sram blocks?
 219         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
 220                          pspec.sram4x4kblock == True)
 221         if self.sram4x4k:
 222             self.sram4k = []
 223             for i in range(4):
 224                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
 225                                                     # features={'err'}
 226                                                     ))
 227
 228         # add interrupt controller?
 229         self.xics = hasattr(pspec, "xics") and pspec.xics == True
 230         if self.xics:
 231             self.xics_icp = XICS_ICP()
 232             self.xics_ics = XICS_ICS()
 233             self.int_level_i = self.xics_ics.int_level_i
 234         else:
 235             self.ext_irq = Signal()
 236
 237         # add GPIO peripheral?
 238         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
 239         if self.gpio:
 240             self.simple_gpio = SimpleGPIO()
 241             self.gpio_o = self.simple_gpio.gpio_o
 242
 243         # main instruction core.  suitable for prototyping / demo only
 244         self.core = core = NonProductionCore(pspec)
 245         self.core_rst = ResetSignal(self.core_domain)
 246
 247         # instruction decoder.  goes into Trap Record
 248         #pdecode = create_pdecode()
 249         self.cur_state = CoreState("cur")  # current state (MSR/PC/SVSTATE)
 250         self.pdecode2 = PowerDecode2(None, state=self.cur_state,
 251                                      opkls=IssuerDecode2ToOperand,
 252                                      svp64_en=self.svp64_en,
 253                                      regreduce_en=self.regreduce_en)
 254         pdecode = self.pdecode2.dec
 255
 256         if self.svp64_en:
 257             self.svp64 = SVP64PrefixDecoder()  # for decoding SVP64 prefix
 258
 259         self.update_svstate = Signal()  # set this if updating svstate
 260         self.new_svstate = new_svstate = SVSTATERec("new_svstate")
 261
 262         # Test Instruction memory
 263         if hasattr(core, "icache"):
 264             # XXX BLECH! use pspec to transfer the I-Cache to ConfigFetchUnit
 265             # truly dreadful.  needs a huge reorg.
 266             pspec.icache = core.icache
 267         self.imem = ConfigFetchUnit(pspec).fu
 268
 269         # DMI interface
 270         self.dbg = CoreDebug()
 271         self.dbg_rst_i = Signal(reset_less=True)
 272
 273         # instruction go/monitor
 274         self.pc_o = Signal(64, reset_less=True)
 275         self.pc_i = Data(64, "pc_i")  # set "ok" to indicate "please change me"
 276         self.msr_i = Data(64, "msr_i") # set "ok" to indicate "please change me"
 277         self.svstate_i = Data(64, "svstate_i")  # ditto
 278         self.core_bigendian_i = Signal()  # TODO: set based on MSR.LE
 279         self.busy_o = Signal(reset_less=True)
 280         self.memerr_o = Signal(reset_less=True)
 281
 282         # STATE regfile read /write ports for PC, MSR, SVSTATE
 283         staterf = self.core.regs.rf['state']
 284         self.state_r_msr = staterf.r_ports['msr']  # MSR rd
 285         self.state_r_pc = staterf.r_ports['cia']  # PC rd
 286         self.state_r_sv = staterf.r_ports['sv']  # SVSTATE rd
 287
 288         self.state_w_msr = staterf.w_ports['d_wr2']  # MSR wr
 289         self.state_w_pc = staterf.w_ports['d_wr1']  # PC wr
 290         self.state_w_sv = staterf.w_ports['sv']  # SVSTATE wr
 291
 292         # DMI interface access
 293         intrf = self.core.regs.rf['int']
 294         crrf = self.core.regs.rf['cr']
 295         xerrf = self.core.regs.rf['xer']
 296         self.int_r = intrf.r_ports['dmi']  # INT read
 297         self.cr_r = crrf.r_ports['full_cr_dbg']  # CR read
 298         self.xer_r = xerrf.r_ports['full_xer']  # XER read
 299
 300         if self.svp64_en:
 301             # for predication
 302             self.int_pred = intrf.r_ports['pred']  # INT predicate read
 303             self.cr_pred = crrf.r_ports['cr_pred']  # CR predicate read
 304
 305         # hack method of keeping an eye on whether branch/trap set the PC
 306         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 307         self.state_nia.wen.name = 'state_nia_wen'
 308
 309         # pulse to synchronize the simulator at instruction end
 310         self.insn_done = Signal()
 311
 312         # indicate any instruction still outstanding, in execution
 313         self.any_busy = Signal()
 314
 315         if self.svp64_en:
 316             # store copies of predicate masks
 317             self.srcmask = Signal(64)
 318             self.dstmask = Signal(64)
 319
 320         # sigh, the wishbone addresses are not wishbone-compliant in microwatt
 321         if self.microwatt_compat:
 322             self.ibus_adr = Signal(32, name='wishbone_insn_out.adr')
 323             self.dbus_adr = Signal(32, name='wishbone_data_out.adr')
 324
 325         # add an output of the PC and instruction, and whether it was requested
 326         # this is for verilator debug purposes
 327         if self.microwatt_compat:
 328             self.nia = Signal(64)
 329             self.nia_req = Signal(1)
 330             self.insn = Signal(32)
 331
 332     def setup_peripherals(self, m):
 333         comb, sync = m.d.comb, m.d.sync
 334
 335         # okaaaay so the debug module must be in coresync clock domain
 336         # but NOT its reset signal. to cope with this, set every single
 337         # submodule explicitly in coresync domain, debug and JTAG
 338         # in their own one but using *external* reset.
 339         csd = DomainRenamer(self.core_domain)
 340         dbd = DomainRenamer(self.dbg_domain)
 341
 342         if self.microwatt_compat:
 343             m.submodules.core = core = self.core
 344         else:
 345             m.submodules.core = core = csd(self.core)
 346         # this _so_ needs sorting out.  ICache is added down inside
 347         # LoadStore1 and is already a submodule of LoadStore1
 348         if not isinstance(self.imem, ICache):
 349             m.submodules.imem = imem = csd(self.imem)
 350         m.submodules.dbg = dbg = dbd(self.dbg)
 351         if self.jtag_en:
 352             m.submodules.jtag = jtag = dbd(self.jtag)
 353             # TODO: UART2GDB mux, here, from external pin
 354             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 355             sync += dbg.dmi.connect_to(jtag.dmi)
 356
 357         # fixup the clocks in microwatt-compat mode (but leave resets alone
 358         # so that microwatt soc.vhdl can pull a reset on the core or DMI
 359         # can do it, just like in TestIssuer)
 360         if self.microwatt_compat:
 361             intclk = ClockSignal(self.core_domain)
 362             dbgclk = ClockSignal(self.dbg_domain)
 363             if self.core_domain != 'sync':
 364                 comb += intclk.eq(ClockSignal())
 365             if self.dbg_domain != 'sync':
 366                 comb += dbgclk.eq(ClockSignal())
 367
 368         # drop the first 3 bits of the incoming wishbone addresses
 369         # this can go if using later versions of microwatt (not now)
 370         if self.microwatt_compat:
 371             ibus = self.imem.ibus
 372             dbus = self.core.l0.cmpi.wb_bus()
 373             comb += self.ibus_adr.eq(Cat(Const(0, 3), ibus.adr))
 374             comb += self.dbus_adr.eq(Cat(Const(0, 3), dbus.adr))
 375
 376         cur_state = self.cur_state
 377
 378         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 379         if self.sram4x4k:
 380             for i, sram in enumerate(self.sram4k):
 381                 m.submodules["sram4k_%d" % i] = csd(sram)
 382                 comb += sram.enable.eq(self.wb_sram_en)
 383
 384         # XICS interrupt handler
 385         if self.xics:
 386             m.submodules.xics_icp = icp = csd(self.xics_icp)
 387             m.submodules.xics_ics = ics = csd(self.xics_ics)
 388             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 389             sync += cur_state.eint.eq(icp.core_irq_o)  # connect ICP to core
 390         else:
 391             sync += cur_state.eint.eq(self.ext_irq)  # connect externally
 392
 393         # GPIO test peripheral
 394         if self.gpio:
 395             m.submodules.simple_gpio = simple_gpio = csd(self.simple_gpio)
 396
 397         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 398         # XXX causes litex ECP5 test to get wrong idea about input and output
 399         # (but works with verilator sim *sigh*)
 400         # if self.gpio and self.xics:
 401         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 402
 403         # instruction decoder
 404         pdecode = create_pdecode()
 405         m.submodules.dec2 = pdecode2 = csd(self.pdecode2)
 406         if self.svp64_en:
 407             m.submodules.svp64 = svp64 = csd(self.svp64)
 408
 409         # convenience
 410         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 411         intrf = self.core.regs.rf['int']
 412
 413         # clock delay power-on reset
 414         cd_por = ClockDomain(reset_less=True)
 415         cd_sync = ClockDomain()
 416         m.domains += cd_por, cd_sync
 417         core_sync = ClockDomain(self.core_domain)
 418         if self.core_domain != "sync":
 419             m.domains += core_sync
 420         if self.dbg_domain != "sync":
 421             dbg_sync = ClockDomain(self.dbg_domain)
 422             m.domains += dbg_sync
 423
 424         ti_rst = Signal(reset_less=True)
 425         delay = Signal(range(4), reset=3)
 426         with m.If(delay != 0):
 427             m.d.por += delay.eq(delay - 1)
 428         comb += cd_por.clk.eq(ClockSignal())
 429
 430         # power-on reset delay
 431         core_rst = ResetSignal(self.core_domain)
 432         if self.core_domain != "sync":
 433             comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 434             comb += core_rst.eq(ti_rst)
 435         else:
 436             with m.If(delay != 0 | dbg.core_rst_o):
 437                 comb += core_rst.eq(1)
 438
 439         # connect external reset signal to DMI Reset
 440         if self.dbg_domain != "sync":
 441             dbg_rst = ResetSignal(self.dbg_domain)
 442             comb += dbg_rst.eq(self.dbg_rst_i)
 443
 444         # busy/halted signals from core
 445         core_busy_o = ~core.p.o_ready | core.n.o_data.busy_o  # core is busy
 446         comb += self.busy_o.eq(core_busy_o)
 447         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 448
 449         # temporary hack: says "go" immediately for both address gen and ST
 450         l0 = core.l0
 451         ldst = core.fus.fus['ldst0']
 452         st_go_edge = rising_edge(m, ldst.st.rel_o)
 453         # link addr-go direct to rel
 454         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o)
 455         m.d.comb += ldst.st.go_i.eq(st_go_edge)  # link store-go to rising rel
 456
 457     def do_dmi(self, m, dbg):
 458         """deals with DMI debug requests
 459
 460         currently only provides read requests for the INT regfile, CR and XER
 461         it will later also deal with *writing* to these regfiles.
 462         """
 463         comb = m.d.comb
 464         sync = m.d.sync
 465         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 466         intrf = self.core.regs.rf['int']
 467
 468         with m.If(d_reg.req):  # request for regfile access being made
 469             # TODO: error-check this
 470             # XXX should this be combinatorial?  sync better?
 471             if intrf.unary:
 472                 comb += self.int_r.ren.eq(1 << d_reg.addr)
 473             else:
 474                 comb += self.int_r.addr.eq(d_reg.addr)
 475                 comb += self.int_r.ren.eq(1)
 476         d_reg_delay = Signal()
 477         sync += d_reg_delay.eq(d_reg.req)
 478         with m.If(d_reg_delay):
 479             # data arrives one clock later
 480             comb += d_reg.data.eq(self.int_r.o_data)
 481             comb += d_reg.ack.eq(1)
 482
 483         # sigh same thing for CR debug
 484         with m.If(d_cr.req):  # request for regfile access being made
 485             comb += self.cr_r.ren.eq(0b11111111)  # enable all
 486         d_cr_delay = Signal()
 487         sync += d_cr_delay.eq(d_cr.req)
 488         with m.If(d_cr_delay):
 489             # data arrives one clock later
 490             comb += d_cr.data.eq(self.cr_r.o_data)
 491             comb += d_cr.ack.eq(1)
 492
 493         # aaand XER...
 494         with m.If(d_xer.req):  # request for regfile access being made
 495             comb += self.xer_r.ren.eq(0b111111)  # enable all
 496         d_xer_delay = Signal()
 497         sync += d_xer_delay.eq(d_xer.req)
 498         with m.If(d_xer_delay):
 499             # data arrives one clock later
 500             comb += d_xer.data.eq(self.xer_r.o_data)
 501             comb += d_xer.ack.eq(1)
 502
 503     def tb_dec_fsm(self, m, spr_dec):
 504         """tb_dec_fsm
 505
 506         this is a FSM for updating either dec or tb.  it runs alternately
 507         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 508         value to DEC, however the regfile has "passthrough" on it so this
 509         *should* be ok.
 510
 511         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 512         """
 513
 514         comb, sync = m.d.comb, m.d.sync
 515         fast_rf = self.core.regs.rf['fast']
 516         fast_r_dectb = fast_rf.r_ports['issue']  # DEC/TB
 517         fast_w_dectb = fast_rf.w_ports['issue']  # DEC/TB
 518
 519         with m.FSM() as fsm:
 520
 521             # initiates read of current DEC
 522             with m.State("DEC_READ"):
 523                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 524                 comb += fast_r_dectb.ren.eq(1)
 525                 m.next = "DEC_WRITE"
 526
 527             # waits for DEC read to arrive (1 cycle), updates with new value
 528             with m.State("DEC_WRITE"):
 529                 new_dec = Signal(64)
 530                 # TODO: MSR.LPCR 32-bit decrement mode
 531                 comb += new_dec.eq(fast_r_dectb.o_data - 1)
 532                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 533                 comb += fast_w_dectb.wen.eq(1)
 534                 comb += fast_w_dectb.i_data.eq(new_dec)
 535                 sync += spr_dec.eq(new_dec)  # copy into cur_state for decoder
 536                 m.next = "TB_READ"
 537
 538             # initiates read of current TB
 539             with m.State("TB_READ"):
 540                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 541                 comb += fast_r_dectb.ren.eq(1)
 542                 m.next = "TB_WRITE"
 543
 544             # waits for read TB to arrive, initiates write of current TB
 545             with m.State("TB_WRITE"):
 546                 new_tb = Signal(64)
 547                 comb += new_tb.eq(fast_r_dectb.o_data + 1)
 548                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 549                 comb += fast_w_dectb.wen.eq(1)
 550                 comb += fast_w_dectb.i_data.eq(new_tb)
 551                 m.next = "DEC_READ"
 552
 553         return m
 554
 555     def elaborate(self, platform):
 556         m = Module()
 557         # convenience
 558         comb, sync = m.d.comb, m.d.sync
 559         cur_state = self.cur_state
 560         pdecode2 = self.pdecode2
 561         dbg = self.dbg
 562
 563         # set up peripherals and core
 564         core_rst = self.core_rst
 565         self.setup_peripherals(m)
 566
 567         # reset current state if core reset requested
 568         with m.If(core_rst):
 569             m.d.sync += self.cur_state.eq(0)
 570
 571         # check halted condition: requested PC to execute matches DMI stop addr
 572         # and immediately stop. address of 0xffff_ffff_ffff_ffff can never
 573         # match
 574         halted = Signal()
 575         comb += halted.eq(dbg.stop_addr_o == dbg.state.pc)
 576         with m.If(halted):
 577             comb += dbg.core_stopped_i.eq(1)
 578             comb += dbg.terminate_i.eq(1)
 579
 580         # PC and instruction from I-Memory
 581         comb += self.pc_o.eq(cur_state.pc)
 582         self.pc_changed = Signal()  # note write to PC
 583         self.msr_changed = Signal()  # note write to MSR
 584         self.sv_changed = Signal()  # note write to SVSTATE
 585
 586         # read state either from incoming override or from regfile
 587         state = CoreState("get")  # current state (MSR/PC/SVSTATE)
 588         state_get(m, state.msr, core_rst, self.msr_i,
 589                        "msr",                  # read MSR
 590                        self.state_r_msr, StateRegs.MSR)
 591         state_get(m, state.pc, core_rst, self.pc_i,
 592                        "pc",                  # read PC
 593                        self.state_r_pc, StateRegs.PC)
 594         state_get(m, state.svstate, core_rst, self.svstate_i,
 595                             "svstate",   # read SVSTATE
 596                             self.state_r_sv, StateRegs.SVSTATE)
 597
 598         # don't write pc every cycle
 599         comb += self.state_w_pc.wen.eq(0)
 600         comb += self.state_w_pc.i_data.eq(0)
 601
 602         # connect up debug state.  note "combinatorially same" below,
 603         # this is a bit naff, passing state over in the dbg class, but
 604         # because it is combinatorial it achieves the desired goal
 605         comb += dbg.state.eq(state)
 606
 607         # this bit doesn't have to be in the FSM: connect up to read
 608         # regfiles on demand from DMI
 609         self.do_dmi(m, dbg)
 610
 611         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 612         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 613         self.tb_dec_fsm(m, cur_state.dec)
 614
 615         # while stopped, allow updating the MSR, PC and SVSTATE.
 616         # these are mainly for debugging purposes (including DMI/JTAG)
 617         with m.If(dbg.core_stopped_i):
 618             with m.If(self.pc_i.ok):
 619                 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 620                 comb += self.state_w_pc.i_data.eq(self.pc_i.data)
 621                 sync += self.pc_changed.eq(1)
 622             with m.If(self.msr_i.ok):
 623                 comb += self.state_w_msr.wen.eq(1 << StateRegs.MSR)
 624                 comb += self.state_w_msr.i_data.eq(self.msr_i.data)
 625                 sync += self.msr_changed.eq(1)
 626             with m.If(self.svstate_i.ok | self.update_svstate):
 627                 with m.If(self.svstate_i.ok): # over-ride from external source
 628                     comb += self.new_svstate.eq(self.svstate_i.data)
 629                 comb += self.state_w_sv.wen.eq(1 << StateRegs.SVSTATE)
 630                 comb += self.state_w_sv.i_data.eq(self.new_svstate)
 631                 sync += self.sv_changed.eq(1)
 632
 633         # start renaming some of the ports to match microwatt
 634         if self.microwatt_compat:
 635             self.core.o.core_terminate_o.name = "terminated_out"
 636             # names of DMI interface
 637             self.dbg.dmi.addr_i.name = 'dmi_addr'
 638             self.dbg.dmi.din.name    = 'dmi_din'
 639             self.dbg.dmi.dout.name   = 'dmi_dout'
 640             self.dbg.dmi.req_i.name  = 'dmi_req'
 641             self.dbg.dmi.we_i.name   = 'dmi_wr'
 642             self.dbg.dmi.ack_o.name  = 'dmi_ack'
 643             # wishbone instruction bus
 644             ibus = self.imem.ibus
 645             ibus.adr.name = 'wishbone_insn_out.adr'
 646             ibus.dat_w.name = 'wishbone_insn_out.dat'
 647             ibus.sel.name = 'wishbone_insn_out.sel'
 648             ibus.cyc.name = 'wishbone_insn_out.cyc'
 649             ibus.stb.name = 'wishbone_insn_out.stb'
 650             ibus.we.name = 'wishbone_insn_out.we'
 651             ibus.dat_r.name = 'wishbone_insn_in.dat'
 652             ibus.ack.name = 'wishbone_insn_in.ack'
 653             ibus.stall.name = 'wishbone_insn_in.stall'
 654             # wishbone data bus
 655             dbus = self.core.l0.cmpi.wb_bus()
 656             dbus.adr.name = 'wishbone_data_out.adr'
 657             dbus.dat_w.name = 'wishbone_data_out.dat'
 658             dbus.sel.name = 'wishbone_data_out.sel'
 659             dbus.cyc.name = 'wishbone_data_out.cyc'
 660             dbus.stb.name = 'wishbone_data_out.stb'
 661             dbus.we.name = 'wishbone_data_out.we'
 662             dbus.dat_r.name = 'wishbone_data_in.dat'
 663             dbus.ack.name = 'wishbone_data_in.ack'
 664             dbus.stall.name = 'wishbone_data_in.stall'
 665
 666         return m
 667
 668     def __iter__(self):
 669         yield from self.pc_i.ports()
 670         yield from self.msr_i.ports()
 671         yield self.pc_o
 672         yield self.memerr_o
 673         yield from self.core.ports()
 674         yield from self.imem.ports()
 675         yield self.core_bigendian_i
 676         yield self.busy_o
 677
 678     def ports(self):
 679         return list(self)
 680
 681     def external_ports(self):
 682         if self.microwatt_compat:
 683             ports = [self.core.o.core_terminate_o,
 684                      self.ext_irq,
 685                      self.alt_reset, # not connected yet
 686                      self.nia, self.insn, self.nia_req,
 687                      ClockSignal(),
 688                      ResetSignal(),
 689                     ]
 690             ports += list(self.dbg.dmi.ports())
 691             # for dbus/ibus microwatt, exclude err btw and cti
 692             for name, sig in self.imem.ibus.fields.items():
 693                 if name not in ['err', 'bte', 'cti', 'adr']:
 694                     ports.append(sig)
 695             for name, sig in self.core.l0.cmpi.wb_bus().fields.items():
 696                 if name not in ['err', 'bte', 'cti', 'adr']:
 697                     ports.append(sig)
 698             # microwatt non-compliant with wishbone
 699             ports.append(self.ibus_adr)
 700             ports.append(self.dbus_adr)
 701             return ports
 702
 703         ports = self.pc_i.ports()
 704         ports = self.msr_i.ports()
 705         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 706                   ]
 707
 708         if self.jtag_en:
 709             ports += list(self.jtag.external_ports())
 710         else:
 711             # don't add DMI if JTAG is enabled
 712             ports += list(self.dbg.dmi.ports())
 713
 714         ports += list(self.imem.ibus.fields.values())
 715         ports += list(self.core.l0.cmpi.wb_bus().fields.values())
 716
 717         if self.sram4x4k:
 718             for sram in self.sram4k:
 719                 ports += list(sram.bus.fields.values())
 720
 721         if self.xics:
 722             ports += list(self.xics_icp.bus.fields.values())
 723             ports += list(self.xics_ics.bus.fields.values())
 724             ports.append(self.int_level_i)
 725         else:
 726             ports.append(self.ext_irq)
 727
 728         if self.gpio:
 729             ports += list(self.simple_gpio.bus.fields.values())
 730             ports.append(self.gpio_o)
 731
 732         return ports
 733
 734     def ports(self):
 735         return list(self)
 736
 737
 738 class TestIssuerInternal(TestIssuerBase):
 739     """TestIssuer - reads instructions from TestMemory and issues them
 740
 741     efficiency and speed is not the main goal here: functional correctness
 742     and code clarity is.  optimisations (which almost 100% interfere with
 743     easy understanding) come later.
 744     """
 745
 746     def fetch_fsm(self, m, dbg, core, pc, msr, svstate, nia, is_svp64_mode,
 747                         fetch_pc_o_ready, fetch_pc_i_valid,
 748                         fetch_insn_o_valid, fetch_insn_i_ready):
 749         """fetch FSM
 750
 751         this FSM performs fetch of raw instruction data, partial-decodes
 752         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 753         read a 2nd 32-bit quantity if that occurs.
 754         """
 755         comb = m.d.comb
 756         sync = m.d.sync
 757         pdecode2 = self.pdecode2
 758         cur_state = self.cur_state
 759         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 760
 761         # also note instruction fetch failed
 762         if hasattr(core, "icache"):
 763             fetch_failed = core.icache.i_out.fetch_failed
 764             flush_needed = True
 765         else:
 766             fetch_failed = Const(0, 1)
 767             flush_needed = False
 768
 769         # set priv / virt mode on I-Cache, sigh
 770         if isinstance(self.imem, ICache):
 771             comb += self.imem.i_in.priv_mode.eq(~msr[MSR.PR])
 772             comb += self.imem.i_in.virt_mode.eq(msr[MSR.IR]) # Instr. Redir (VM)
 773
 774         with m.FSM(name='fetch_fsm'):
 775
 776             # waiting (zzz)
 777             with m.State("IDLE"):
 778                 # fetch allowed if not failed and stopped but not stepping
 779                 # (see dmi.py for how core_stop_o is generated)
 780                 with m.If(~fetch_failed & ~dbg.core_stop_o):
 781                     comb += fetch_pc_o_ready.eq(1)
 782                 with m.If(fetch_pc_i_valid & ~pdecode2.instr_fault
 783                           & ~dbg.core_stop_o):
 784                     # instruction allowed to go: start by reading the PC
 785                     # capture the PC and also drop it into Insn Memory
 786                     # we have joined a pair of combinatorial memory
 787                     # lookups together.  this is Generally Bad.
 788                     comb += self.imem.a_pc_i.eq(pc)
 789                     comb += self.imem.a_i_valid.eq(1)
 790                     comb += self.imem.f_i_valid.eq(1)
 791                     # transfer state to output
 792                     sync += cur_state.pc.eq(pc)
 793                     sync += cur_state.svstate.eq(svstate)  # and svstate
 794                     sync += cur_state.msr.eq(msr)  # and msr
 795
 796                     m.next = "INSN_READ"  # move to "wait for bus" phase
 797
 798             # dummy pause to find out why simulation is not keeping up
 799             with m.State("INSN_READ"):
 800                 # when using "single-step" mode, checking dbg.stopping_o
 801                 # prevents progress.  allow fetch to proceed once started
 802                 stopping = Const(0)
 803                 #if self.allow_overlap:
 804                 #    stopping = dbg.stopping_o
 805                 with m.If(stopping):
 806                     # stopping: jump back to idle
 807                     m.next = "IDLE"
 808                 with m.Else():
 809                     with m.If(self.imem.f_busy_o &
 810                               ~pdecode2.instr_fault):  # zzz...
 811                         # busy but not fetch failed: stay in wait-read
 812                         comb += self.imem.a_pc_i.eq(pc)
 813                         comb += self.imem.a_i_valid.eq(1)
 814                         comb += self.imem.f_i_valid.eq(1)
 815                     with m.Else():
 816                         # not busy (or fetch failed!): instruction fetched
 817                         # when fetch failed, the instruction gets ignored
 818                         # by the decoder
 819                         if hasattr(core, "icache"):
 820                             # blech, icache returns actual instruction
 821                             insn = self.imem.f_instr_o
 822                         else:
 823                             # but these return raw memory
 824                             insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 825                         if self.svp64_en:
 826                             svp64 = self.svp64
 827                             # decode the SVP64 prefix, if any
 828                             comb += svp64.raw_opcode_in.eq(insn)
 829                             comb += svp64.bigendian.eq(self.core_bigendian_i)
 830                             # pass the decoded prefix (if any) to PowerDecoder2
 831                             sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 832                             sync += pdecode2.is_svp64_mode.eq(is_svp64_mode)
 833                             # remember whether this is a prefixed instruction,
 834                             # so the FSM can readily loop when VL==0
 835                             sync += is_svp64_mode.eq(svp64.is_svp64_mode)
 836                             # calculate the address of the following instruction
 837                             insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 838                             sync += nia.eq(cur_state.pc + insn_size)
 839                             with m.If(~svp64.is_svp64_mode):
 840                                 # with no prefix, store the instruction
 841                                 # and hand it directly to the next FSM
 842                                 sync += dec_opcode_i.eq(insn)
 843                                 m.next = "INSN_READY"
 844                             with m.Else():
 845                                 # fetch the rest of the instruction from memory
 846                                 comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 847                                 comb += self.imem.a_i_valid.eq(1)
 848                                 comb += self.imem.f_i_valid.eq(1)
 849                                 m.next = "INSN_READ2"
 850                         else:
 851                             # not SVP64 - 32-bit only
 852                             sync += nia.eq(cur_state.pc + 4)
 853                             sync += dec_opcode_i.eq(insn)
 854                             if self.microwatt_compat:
 855                                 # for verilator debug purposes
 856                                 comb += self.insn.eq(insn)
 857                                 comb += self.nia.eq(cur_state.pc)
 858                                 comb += self.nia_req.eq(1)
 859                             m.next = "INSN_READY"
 860
 861             with m.State("INSN_READ2"):
 862                 with m.If(self.imem.f_busy_o):  # zzz...
 863                     # busy: stay in wait-read
 864                     comb += self.imem.a_i_valid.eq(1)
 865                     comb += self.imem.f_i_valid.eq(1)
 866                 with m.Else():
 867                     # not busy: instruction fetched
 868                     if hasattr(core, "icache"):
 869                         # blech, icache returns actual instruction
 870                         insn = self.imem.f_instr_o
 871                     else:
 872                         insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 873                     sync += dec_opcode_i.eq(insn)
 874                     m.next = "INSN_READY"
 875                     # TODO: probably can start looking at pdecode2.rm_dec
 876                     # here or maybe even in INSN_READ state, if svp64_mode
 877                     # detected, in order to trigger - and wait for - the
 878                     # predicate reading.
 879                     if self.svp64_en:
 880                         pmode = pdecode2.rm_dec.predmode
 881                     """
 882                     if pmode != SVP64PredMode.ALWAYS.value:
 883                         fire predicate loading FSM and wait before
 884                         moving to INSN_READY
 885                     else:
 886                         sync += self.srcmask.eq(-1) # set to all 1s
 887                         sync += self.dstmask.eq(-1) # set to all 1s
 888                         m.next = "INSN_READY"
 889                     """
 890
 891             with m.State("INSN_READY"):
 892                 # hand over the instruction, to be decoded
 893                 comb += fetch_insn_o_valid.eq(1)
 894                 with m.If(fetch_insn_i_ready):
 895                     m.next = "IDLE"
 896
 897
 898     def fetch_predicate_fsm(self, m,
 899                             pred_insn_i_valid, pred_insn_o_ready,
 900                             pred_mask_o_valid, pred_mask_i_ready):
 901         """fetch_predicate_fsm - obtains (constructs in the case of CR)
 902            src/dest predicate masks
 903
 904         https://bugs.libre-soc.org/show_bug.cgi?id=617
 905         the predicates can be read here, by using IntRegs r_ports['pred']
 906         or CRRegs r_ports['pred'].  in the case of CRs it will have to
 907         be done through multiple reads, extracting one relevant at a time.
 908         later, a faster way would be to use the 32-bit-wide CR port but
 909         this is more complex decoding, here.  equivalent code used in
 910         ISACaller is "from openpower.decoder.isa.caller import get_predcr"
 911
 912         note: this ENTIRE FSM is not to be called when svp64 is disabled
 913         """
 914         comb = m.d.comb
 915         sync = m.d.sync
 916         pdecode2 = self.pdecode2
 917         rm_dec = pdecode2.rm_dec  # SVP64RMModeDecode
 918         predmode = rm_dec.predmode
 919         srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
 920         cr_pred, int_pred = self.cr_pred, self.int_pred   # read regfiles
 921         # get src/dst step, so we can skip already used mask bits
 922         cur_state = self.cur_state
 923         srcstep = cur_state.svstate.srcstep
 924         dststep = cur_state.svstate.dststep
 925         cur_vl = cur_state.svstate.vl
 926
 927         # decode predicates
 928         sregread, sinvert, sunary, sall1s = get_predint(m, srcpred, 's')
 929         dregread, dinvert, dunary, dall1s = get_predint(m, dstpred, 'd')
 930         sidx, scrinvert = get_predcr(m, srcpred, 's')
 931         didx, dcrinvert = get_predcr(m, dstpred, 'd')
 932
 933         # store fetched masks, for either intpred or crpred
 934         # when src/dst step is not zero, the skipped mask bits need to be
 935         # shifted-out, before actually storing them in src/dest mask
 936         new_srcmask = Signal(64, reset_less=True)
 937         new_dstmask = Signal(64, reset_less=True)
 938
 939         with m.FSM(name="fetch_predicate"):
 940
 941             with m.State("FETCH_PRED_IDLE"):
 942                 comb += pred_insn_o_ready.eq(1)
 943                 with m.If(pred_insn_i_valid):
 944                     with m.If(predmode == SVP64PredMode.INT):
 945                         # skip fetching destination mask register, when zero
 946                         with m.If(dall1s):
 947                             sync += new_dstmask.eq(-1)
 948                             # directly go to fetch source mask register
 949                             # guaranteed not to be zero (otherwise predmode
 950                             # would be SVP64PredMode.ALWAYS, not INT)
 951                             comb += int_pred.addr.eq(sregread)
 952                             comb += int_pred.ren.eq(1)
 953                             m.next = "INT_SRC_READ"
 954                         # fetch destination predicate register
 955                         with m.Else():
 956                             comb += int_pred.addr.eq(dregread)
 957                             comb += int_pred.ren.eq(1)
 958                             m.next = "INT_DST_READ"
 959                     with m.Elif(predmode == SVP64PredMode.CR):
 960                         # go fetch masks from the CR register file
 961                         sync += new_srcmask.eq(0)
 962                         sync += new_dstmask.eq(0)
 963                         m.next = "CR_READ"
 964                     with m.Else():
 965                         sync += self.srcmask.eq(-1)
 966                         sync += self.dstmask.eq(-1)
 967                         m.next = "FETCH_PRED_DONE"
 968
 969             with m.State("INT_DST_READ"):
 970                 # store destination mask
 971                 inv = Repl(dinvert, 64)
 972                 with m.If(dunary):
 973                     # set selected mask bit for 1<<r3 mode
 974                     dst_shift = Signal(range(64))
 975                     comb += dst_shift.eq(self.int_pred.o_data & 0b111111)
 976                     sync += new_dstmask.eq(1 << dst_shift)
 977                 with m.Else():
 978                     # invert mask if requested
 979                     sync += new_dstmask.eq(self.int_pred.o_data ^ inv)
 980                 # skip fetching source mask register, when zero
 981                 with m.If(sall1s):
 982                     sync += new_srcmask.eq(-1)
 983                     m.next = "FETCH_PRED_SHIFT_MASK"
 984                 # fetch source predicate register
 985                 with m.Else():
 986                     comb += int_pred.addr.eq(sregread)
 987                     comb += int_pred.ren.eq(1)
 988                     m.next = "INT_SRC_READ"
 989
 990             with m.State("INT_SRC_READ"):
 991                 # store source mask
 992                 inv = Repl(sinvert, 64)
 993                 with m.If(sunary):
 994                     # set selected mask bit for 1<<r3 mode
 995                     src_shift = Signal(range(64))
 996                     comb += src_shift.eq(self.int_pred.o_data & 0b111111)
 997                     sync += new_srcmask.eq(1 << src_shift)
 998                 with m.Else():
 999                     # invert mask if requested
1000                     sync += new_srcmask.eq(self.int_pred.o_data ^ inv)
1001                 m.next = "FETCH_PRED_SHIFT_MASK"
1002
1003             # fetch masks from the CR register file
1004             # implements the following loop:
1005             # idx, inv = get_predcr(mask)
1006             # mask = 0
1007             # for cr_idx in range(vl):
1008             #     cr = crl[cr_idx + SVP64CROffs.CRPred]  # takes one cycle
1009             #     if cr[idx] ^ inv:
1010             #         mask |= 1 << cr_idx
1011             # return mask
1012             with m.State("CR_READ"):
1013                 # CR index to be read, which will be ready by the next cycle
1014                 cr_idx = Signal.like(cur_vl, reset_less=True)
1015                 # submit the read operation to the regfile
1016                 with m.If(cr_idx != cur_vl):
1017                     # the CR read port is unary ...
1018                     # ren = 1 << cr_idx
1019                     # ... in MSB0 convention ...
1020                     # ren = 1 << (7 - cr_idx)
1021                     # ... and with an offset:
1022                     # ren = 1 << (7 - off - cr_idx)
1023                     idx = SVP64CROffs.CRPred + cr_idx
1024                     comb += cr_pred.ren.eq(1 << (7 - idx))
1025                     # signal data valid in the next cycle
1026                     cr_read = Signal(reset_less=True)
1027                     sync += cr_read.eq(1)
1028                     # load the next index
1029                     sync += cr_idx.eq(cr_idx + 1)
1030                 with m.Else():
1031                     # exit on loop end
1032                     sync += cr_read.eq(0)
1033                     sync += cr_idx.eq(0)
1034                     m.next = "FETCH_PRED_SHIFT_MASK"
1035                 with m.If(cr_read):
1036                     # compensate for the one cycle delay on the regfile
1037                     cur_cr_idx = Signal.like(cur_vl)
1038                     comb += cur_cr_idx.eq(cr_idx - 1)
1039                     # read the CR field, select the appropriate bit
1040                     cr_field = Signal(4)
1041                     scr_bit = Signal()
1042                     dcr_bit = Signal()
1043                     comb += cr_field.eq(cr_pred.o_data)
1044                     comb += scr_bit.eq(cr_field.bit_select(sidx, 1)
1045                                        ^ scrinvert)
1046                     comb += dcr_bit.eq(cr_field.bit_select(didx, 1)
1047                                        ^ dcrinvert)
1048                     # set the corresponding mask bit
1049                     bit_to_set = Signal.like(self.srcmask)
1050                     comb += bit_to_set.eq(1 << cur_cr_idx)
1051                     with m.If(scr_bit):
1052                         sync += new_srcmask.eq(new_srcmask | bit_to_set)
1053                     with m.If(dcr_bit):
1054                         sync += new_dstmask.eq(new_dstmask | bit_to_set)
1055
1056             with m.State("FETCH_PRED_SHIFT_MASK"):
1057                 # shift-out skipped mask bits
1058                 sync += self.srcmask.eq(new_srcmask >> srcstep)
1059                 sync += self.dstmask.eq(new_dstmask >> dststep)
1060                 m.next = "FETCH_PRED_DONE"
1061
1062             with m.State("FETCH_PRED_DONE"):
1063                 comb += pred_mask_o_valid.eq(1)
1064                 with m.If(pred_mask_i_ready):
1065                     m.next = "FETCH_PRED_IDLE"
1066
1067     def issue_fsm(self, m, core, nia,
1068                   dbg, core_rst, is_svp64_mode,
1069                   fetch_pc_o_ready, fetch_pc_i_valid,
1070                   fetch_insn_o_valid, fetch_insn_i_ready,
1071                   pred_insn_i_valid, pred_insn_o_ready,
1072                   pred_mask_o_valid, pred_mask_i_ready,
1073                   exec_insn_i_valid, exec_insn_o_ready,
1074                   exec_pc_o_valid, exec_pc_i_ready):
1075         """issue FSM
1076
1077         decode / issue FSM.  this interacts with the "fetch" FSM
1078         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
1079         (outgoing). also interacts with the "execute" FSM
1080         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
1081         (incoming).
1082         SVP64 RM prefixes have already been set up by the
1083         "fetch" phase, so execute is fairly straightforward.
1084         """
1085
1086         comb = m.d.comb
1087         sync = m.d.sync
1088         pdecode2 = self.pdecode2
1089         cur_state = self.cur_state
1090         new_svstate = self.new_svstate
1091
1092         # temporaries
1093         dec_opcode_i = pdecode2.dec.raw_opcode_in  # raw opcode
1094
1095         # for updating svstate (things like srcstep etc.)
1096         comb += new_svstate.eq(cur_state.svstate)
1097
1098         # precalculate srcstep+1 and dststep+1
1099         cur_srcstep = cur_state.svstate.srcstep
1100         cur_dststep = cur_state.svstate.dststep
1101         next_srcstep = Signal.like(cur_srcstep)
1102         next_dststep = Signal.like(cur_dststep)
1103         comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
1104         comb += next_dststep.eq(cur_state.svstate.dststep+1)
1105
1106         # note if an exception happened.  in a pipelined or OoO design
1107         # this needs to be accompanied by "shadowing" (or stalling)
1108         exc_happened = self.core.o.exc_happened
1109         # also note instruction fetch failed
1110         if hasattr(core, "icache"):
1111             fetch_failed = core.icache.i_out.fetch_failed
1112             flush_needed = True
1113             # set to fault in decoder
1114             # update (highest priority) instruction fault
1115             rising_fetch_failed = rising_edge(m, fetch_failed)
1116             with m.If(rising_fetch_failed):
1117                 sync += pdecode2.instr_fault.eq(1)
1118         else:
1119             fetch_failed = Const(0, 1)
1120             flush_needed = False
1121
1122         with m.FSM(name="issue_fsm"):
1123
1124             # sync with the "fetch" phase which is reading the instruction
1125             # at this point, there is no instruction running, that
1126             # could inadvertently update the PC.
1127             with m.State("ISSUE_START"):
1128                 # reset instruction fault
1129                 sync += pdecode2.instr_fault.eq(0)
1130                 # wait on "core stop" release, before next fetch
1131                 # need to do this here, in case we are in a VL==0 loop
1132                 with m.If(~dbg.core_stop_o & ~core_rst):
1133                     comb += fetch_pc_i_valid.eq(1)  # tell fetch to start
1134                     with m.If(fetch_pc_o_ready):   # fetch acknowledged us
1135                         m.next = "INSN_WAIT"
1136                 with m.Else():
1137                     # tell core it's stopped, and acknowledge debug handshake
1138                     comb += dbg.core_stopped_i.eq(1)
1139                     # while stopped, allow updating SVSTATE
1140                     with m.If(self.svstate_i.ok):
1141                         comb += new_svstate.eq(self.svstate_i.data)
1142                         comb += self.update_svstate.eq(1)
1143                         sync += self.sv_changed.eq(1)
1144
1145             # wait for an instruction to arrive from Fetch
1146             with m.State("INSN_WAIT"):
1147                 # when using "single-step" mode, checking dbg.stopping_o
1148                 # prevents progress.  allow issue to proceed once started
1149                 stopping = Const(0)
1150                 #if self.allow_overlap:
1151                 #    stopping = dbg.stopping_o
1152                 with m.If(stopping):
1153                     # stopping: jump back to idle
1154                     m.next = "ISSUE_START"
1155                     if flush_needed:
1156                         # request the icache to stop asserting "failed"
1157                         comb += core.icache.flush_in.eq(1)
1158                     # stop instruction fault
1159                     sync += pdecode2.instr_fault.eq(0)
1160                 with m.Else():
1161                     comb += fetch_insn_i_ready.eq(1)
1162                     with m.If(fetch_insn_o_valid):
1163                         # loop into ISSUE_START if it's a SVP64 instruction
1164                         # and VL == 0.  this because VL==0 is a for-loop
1165                         # from 0 to 0 i.e. always, always a NOP.
1166                         cur_vl = cur_state.svstate.vl
1167                         with m.If(is_svp64_mode & (cur_vl == 0)):
1168                             # update the PC before fetching the next instruction
1169                             # since we are in a VL==0 loop, no instruction was
1170                             # executed that we could be overwriting
1171                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
1172                             comb += self.state_w_pc.i_data.eq(nia)
1173                             comb += self.insn_done.eq(1)
1174                             m.next = "ISSUE_START"
1175                         with m.Else():
1176                             if self.svp64_en:
1177                                 m.next = "PRED_START"  # fetching predicate
1178                             else:
1179                                 m.next = "DECODE_SV"  # skip predication
1180
1181             with m.State("PRED_START"):
1182                 comb += pred_insn_i_valid.eq(1)  # tell fetch_pred to start
1183                 with m.If(pred_insn_o_ready):  # fetch_pred acknowledged us
1184                     m.next = "MASK_WAIT"
1185
1186             with m.State("MASK_WAIT"):
1187                 comb += pred_mask_i_ready.eq(1)  # ready to receive the masks
1188                 with m.If(pred_mask_o_valid):  # predication masks are ready
1189                     m.next = "PRED_SKIP"
1190
1191             # skip zeros in predicate
1192             with m.State("PRED_SKIP"):
1193                 with m.If(~is_svp64_mode):
1194                     m.next = "DECODE_SV"  # nothing to do
1195                 with m.Else():
1196                     if self.svp64_en:
1197                         pred_src_zero = pdecode2.rm_dec.pred_sz
1198                         pred_dst_zero = pdecode2.rm_dec.pred_dz
1199
1200                         # new srcstep, after skipping zeros
1201                         skip_srcstep = Signal.like(cur_srcstep)
1202                         # value to be added to the current srcstep
1203                         src_delta = Signal.like(cur_srcstep)
1204                         # add leading zeros to srcstep, if not in zero mode
1205                         with m.If(~pred_src_zero):
1206                             # priority encoder (count leading zeros)
1207                             # append guard bit, in case the mask is all zeros
1208                             pri_enc_src = PriorityEncoder(65)
1209                             m.submodules.pri_enc_src = pri_enc_src
1210                             comb += pri_enc_src.i.eq(Cat(self.srcmask,
1211                                                          Const(1, 1)))
1212                             comb += src_delta.eq(pri_enc_src.o)
1213                         # apply delta to srcstep
1214                         comb += skip_srcstep.eq(cur_srcstep + src_delta)
1215                         # shift-out all leading zeros from the mask
1216                         # plus the leading "one" bit
1217                         # TODO count leading zeros and shift-out the zero
1218                         #      bits, in the same step, in hardware
1219                         sync += self.srcmask.eq(self.srcmask >> (src_delta+1))
1220
1221                         # same as above, but for dststep
1222                         skip_dststep = Signal.like(cur_dststep)
1223                         dst_delta = Signal.like(cur_dststep)
1224                         with m.If(~pred_dst_zero):
1225                             pri_enc_dst = PriorityEncoder(65)
1226                             m.submodules.pri_enc_dst = pri_enc_dst
1227                             comb += pri_enc_dst.i.eq(Cat(self.dstmask,
1228                                                          Const(1, 1)))
1229                             comb += dst_delta.eq(pri_enc_dst.o)
1230                         comb += skip_dststep.eq(cur_dststep + dst_delta)
1231                         sync += self.dstmask.eq(self.dstmask >> (dst_delta+1))
1232
1233                         # TODO: initialize mask[VL]=1 to avoid passing past VL
1234                         with m.If((skip_srcstep >= cur_vl) |
1235                                   (skip_dststep >= cur_vl)):
1236                             # end of VL loop. Update PC and reset src/dst step
1237                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
1238                             comb += self.state_w_pc.i_data.eq(nia)
1239                             comb += new_svstate.srcstep.eq(0)
1240                             comb += new_svstate.dststep.eq(0)
1241                             comb += self.update_svstate.eq(1)
1242                             # synchronize with the simulator
1243                             comb += self.insn_done.eq(1)
1244                             # go back to Issue
1245                             m.next = "ISSUE_START"
1246                         with m.Else():
1247                             # update new src/dst step
1248                             comb += new_svstate.srcstep.eq(skip_srcstep)
1249                             comb += new_svstate.dststep.eq(skip_dststep)
1250                             comb += self.update_svstate.eq(1)
1251                             # proceed to Decode
1252                             m.next = "DECODE_SV"
1253
1254                         # pass predicate mask bits through to satellite decoders
1255                         # TODO: for SIMD this will be *multiple* bits
1256                         sync += core.i.sv_pred_sm.eq(self.srcmask[0])
1257                         sync += core.i.sv_pred_dm.eq(self.dstmask[0])
1258
1259             # after src/dst step have been updated, we are ready
1260             # to decode the instruction
1261             with m.State("DECODE_SV"):
1262                 # decode the instruction
1263                 with m.If(~fetch_failed):
1264                     sync += pdecode2.instr_fault.eq(0)
1265                 sync += core.i.e.eq(pdecode2.e)
1266                 sync += core.i.state.eq(cur_state)
1267                 sync += core.i.raw_insn_i.eq(dec_opcode_i)
1268                 sync += core.i.bigendian_i.eq(self.core_bigendian_i)
1269                 if self.svp64_en:
1270                     sync += core.i.sv_rm.eq(pdecode2.sv_rm)
1271                     # set RA_OR_ZERO detection in satellite decoders
1272                     sync += core.i.sv_a_nz.eq(pdecode2.sv_a_nz)
1273                     # and svp64 detection
1274                     sync += core.i.is_svp64_mode.eq(is_svp64_mode)
1275                     # and svp64 bit-rev'd ldst mode
1276                     ldst_dec = pdecode2.use_svp64_ldst_dec
1277                     sync += core.i.use_svp64_ldst_dec.eq(ldst_dec)
1278                 # after decoding, reset any previous exception condition,
1279                 # allowing it to be set again during the next execution
1280                 sync += pdecode2.ldst_exc.eq(0)
1281
1282                 m.next = "INSN_EXECUTE"  # move to "execute"
1283
1284             # handshake with execution FSM, move to "wait" once acknowledged
1285             with m.State("INSN_EXECUTE"):
1286                 # when using "single-step" mode, checking dbg.stopping_o
1287                 # prevents progress.  allow execute to proceed once started
1288                 stopping = Const(0)
1289                 #if self.allow_overlap:
1290                 #    stopping = dbg.stopping_o
1291                 with m.If(stopping):
1292                     # stopping: jump back to idle
1293                     m.next = "ISSUE_START"
1294                     if flush_needed:
1295                         # request the icache to stop asserting "failed"
1296                         comb += core.icache.flush_in.eq(1)
1297                     # stop instruction fault
1298                     sync += pdecode2.instr_fault.eq(0)
1299                 with m.Else():
1300                     comb += exec_insn_i_valid.eq(1)  # trigger execute
1301                     with m.If(exec_insn_o_ready):   # execute acknowledged us
1302                         m.next = "EXECUTE_WAIT"
1303
1304             with m.State("EXECUTE_WAIT"):
1305                 comb += exec_pc_i_ready.eq(1)
1306                 # see https://bugs.libre-soc.org/show_bug.cgi?id=636
1307                 # the exception info needs to be blatted into
1308                 # pdecode.ldst_exc, and the instruction "re-run".
1309                 # when ldst_exc.happened is set, the PowerDecoder2
1310                 # reacts very differently: it re-writes the instruction
1311                 # with a "trap" (calls PowerDecoder2.trap()) which
1312                 # will *overwrite* whatever was requested and jump the
1313                 # PC to the exception address, as well as alter MSR.
1314                 # nothing else needs to be done other than to note
1315                 # the change of PC and MSR (and, later, SVSTATE)
1316                 with m.If(exc_happened):
1317                     mmu = core.fus.get_exc("mmu0")
1318                     ldst = core.fus.get_exc("ldst0")
1319                     if mmu is not None:
1320                         with m.If(fetch_failed):
1321                             # instruction fetch: exception is from MMU
1322                             # reset instr_fault (highest priority)
1323                             sync += pdecode2.ldst_exc.eq(mmu)
1324                             sync += pdecode2.instr_fault.eq(0)
1325                             if flush_needed:
1326                                 # request icache to stop asserting "failed"
1327                                 comb += core.icache.flush_in.eq(1)
1328                     with m.If(~fetch_failed):
1329                         # otherwise assume it was a LDST exception
1330                         sync += pdecode2.ldst_exc.eq(ldst)
1331
1332                 with m.If(exec_pc_o_valid):
1333
1334                     # was this the last loop iteration?
1335                     is_last = Signal()
1336                     cur_vl = cur_state.svstate.vl
1337                     comb += is_last.eq(next_srcstep == cur_vl)
1338
1339                     with m.If(pdecode2.instr_fault):
1340                         # reset instruction fault, try again
1341                         sync += pdecode2.instr_fault.eq(0)
1342                         m.next = "ISSUE_START"
1343
1344                     # return directly to Decode if Execute generated an
1345                     # exception.
1346                     with m.Elif(pdecode2.ldst_exc.happened):
1347                         m.next = "DECODE_SV"
1348
1349                     # if MSR, PC or SVSTATE were changed by the previous
1350                     # instruction, go directly back to Fetch, without
1351                     # updating either MSR PC or SVSTATE
1352                     with m.Elif(self.msr_changed | self.pc_changed |
1353                                 self.sv_changed):
1354                         m.next = "ISSUE_START"
1355
1356                     # also return to Fetch, when no output was a vector
1357                     # (regardless of SRCSTEP and VL), or when the last
1358                     # instruction was really the last one of the VL loop
1359                     with m.Elif((~pdecode2.loop_continue) | is_last):
1360                         # before going back to fetch, update the PC state
1361                         # register with the NIA.
1362                         # ok here we are not reading the branch unit.
1363                         # TODO: this just blithely overwrites whatever
1364                         #       pipeline updated the PC
1365                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
1366                         comb += self.state_w_pc.i_data.eq(nia)
1367                         # reset SRCSTEP before returning to Fetch
1368                         if self.svp64_en:
1369                             with m.If(pdecode2.loop_continue):
1370                                 comb += new_svstate.srcstep.eq(0)
1371                                 comb += new_svstate.dststep.eq(0)
1372                                 comb += self.update_svstate.eq(1)
1373                         else:
1374                             comb += new_svstate.srcstep.eq(0)
1375                             comb += new_svstate.dststep.eq(0)
1376                             comb += self.update_svstate.eq(1)
1377                         m.next = "ISSUE_START"
1378
1379                     # returning to Execute? then, first update SRCSTEP
1380                     with m.Else():
1381                         comb += new_svstate.srcstep.eq(next_srcstep)
1382                         comb += new_svstate.dststep.eq(next_dststep)
1383                         comb += self.update_svstate.eq(1)
1384                         # return to mask skip loop
1385                         m.next = "PRED_SKIP"
1386
1387
1388         # check if svstate needs updating: if so, write it to State Regfile
1389         with m.If(self.update_svstate):
1390             sync += cur_state.svstate.eq(self.new_svstate)  # for next clock
1391
1392     def execute_fsm(self, m, core,
1393                     exec_insn_i_valid, exec_insn_o_ready,
1394                     exec_pc_o_valid, exec_pc_i_ready):
1395         """execute FSM
1396
1397         execute FSM. this interacts with the "issue" FSM
1398         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
1399         (outgoing). SVP64 RM prefixes have already been set up by the
1400         "issue" phase, so execute is fairly straightforward.
1401         """
1402
1403         comb = m.d.comb
1404         sync = m.d.sync
1405         dbg = self.dbg
1406         pdecode2 = self.pdecode2
1407
1408         # temporaries
1409         core_busy_o = core.n.o_data.busy_o  # core is busy
1410         core_ivalid_i = core.p.i_valid              # instruction is valid
1411
1412         if hasattr(core, "icache"):
1413             fetch_failed = core.icache.i_out.fetch_failed
1414         else:
1415             fetch_failed = Const(0, 1)
1416
1417         with m.FSM(name="exec_fsm"):
1418
1419             # waiting for instruction bus (stays there until not busy)
1420             with m.State("INSN_START"):
1421                 comb += exec_insn_o_ready.eq(1)
1422                 with m.If(exec_insn_i_valid):
1423                     comb += core_ivalid_i.eq(1)  # instruction is valid/issued
1424                     sync += self.sv_changed.eq(0)
1425                     sync += self.pc_changed.eq(0)
1426                     sync += self.msr_changed.eq(0)
1427                     with m.If(core.p.o_ready):  # only move if accepted
1428                         m.next = "INSN_ACTIVE"  # move to "wait completion"
1429
1430             # instruction started: must wait till it finishes
1431             with m.State("INSN_ACTIVE"):
1432                 # note changes to MSR, PC and SVSTATE
1433                 # XXX oops, really must monitor *all* State Regfile write
1434                 # ports looking for changes!
1435                 with m.If(self.state_nia.wen & (1 << StateRegs.SVSTATE)):
1436                     sync += self.sv_changed.eq(1)
1437                 with m.If(self.state_nia.wen & (1 << StateRegs.MSR)):
1438                     sync += self.msr_changed.eq(1)
1439                 with m.If(self.state_nia.wen & (1 << StateRegs.PC)):
1440                     sync += self.pc_changed.eq(1)
1441                 with m.If(~core_busy_o):  # instruction done!
1442                     comb += exec_pc_o_valid.eq(1)
1443                     with m.If(exec_pc_i_ready):
1444                         # when finished, indicate "done".
1445                         # however, if there was an exception, the instruction
1446                         # is *not* yet done.  this is an implementation
1447                         # detail: we choose to implement exceptions by
1448                         # taking the exception information from the LDST
1449                         # unit, putting that *back* into the PowerDecoder2,
1450                         # and *re-running the entire instruction*.
1451                         # if we erroneously indicate "done" here, it is as if
1452                         # there were *TWO* instructions:
1453                         # 1) the failed LDST 2) a TRAP.
1454                         with m.If(~pdecode2.ldst_exc.happened &
1455                                    ~pdecode2.instr_fault):
1456                             comb += self.insn_done.eq(1)
1457                         m.next = "INSN_START"  # back to fetch
1458                 # terminate returns directly to INSN_START
1459                 with m.If(dbg.terminate_i):
1460                     # comb += self.insn_done.eq(1) - no because it's not
1461                     m.next = "INSN_START"  # back to fetch
1462
1463     def elaborate(self, platform):
1464         m = super().elaborate(platform)
1465         # convenience
1466         comb, sync = m.d.comb, m.d.sync
1467         cur_state = self.cur_state
1468         pdecode2 = self.pdecode2
1469         dbg = self.dbg
1470         core = self.core
1471
1472         # set up peripherals and core
1473         core_rst = self.core_rst
1474
1475         # indicate to outside world if any FU is still executing
1476         comb += self.any_busy.eq(core.n.o_data.any_busy_o)  # any FU executing
1477
1478         # address of the next instruction, in the absence of a branch
1479         # depends on the instruction size
1480         nia = Signal(64)
1481
1482         # connect up debug signals
1483         with m.If(core.o.core_terminate_o):
1484             comb += dbg.terminate_i.eq(1)
1485
1486         # pass the prefix mode from Fetch to Issue, so the latter can loop
1487         # on VL==0
1488         is_svp64_mode = Signal()
1489
1490         # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
1491         # issue, decode/execute, now joined by "Predicate fetch/calculate".
1492         # these are the handshake signals between each
1493
1494         # fetch FSM can run as soon as the PC is valid
1495         fetch_pc_i_valid = Signal()  # Execute tells Fetch "start next read"
1496         fetch_pc_o_ready = Signal()  # Fetch Tells SVSTATE "proceed"
1497
1498         # fetch FSM hands over the instruction to be decoded / issued
1499         fetch_insn_o_valid = Signal()
1500         fetch_insn_i_ready = Signal()
1501
1502         # predicate fetch FSM decodes and fetches the predicate
1503         pred_insn_i_valid = Signal()
1504         pred_insn_o_ready = Signal()
1505
1506         # predicate fetch FSM delivers the masks
1507         pred_mask_o_valid = Signal()
1508         pred_mask_i_ready = Signal()
1509
1510         # issue FSM delivers the instruction to the be executed
1511         exec_insn_i_valid = Signal()
1512         exec_insn_o_ready = Signal()
1513
1514         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
1515         exec_pc_o_valid = Signal()
1516         exec_pc_i_ready = Signal()
1517
1518         # the FSMs here are perhaps unusual in that they detect conditions
1519         # then "hold" information, combinatorially, for the core
1520         # (as opposed to using sync - which would be on a clock's delay)
1521         # this includes the actual opcode, valid flags and so on.
1522
1523         # Fetch, then predicate fetch, then Issue, then Execute.
1524         # Issue is where the VL for-loop # lives.  the ready/valid
1525         # signalling is used to communicate between the four.
1526
1527         self.fetch_fsm(m, dbg, core, dbg.state.pc, dbg.state.msr,
1528                        dbg.state.svstate, nia, is_svp64_mode,
1529                        fetch_pc_o_ready, fetch_pc_i_valid,
1530                        fetch_insn_o_valid, fetch_insn_i_ready)
1531
1532         self.issue_fsm(m, core, nia,
1533                        dbg, core_rst, is_svp64_mode,
1534                        fetch_pc_o_ready, fetch_pc_i_valid,
1535                        fetch_insn_o_valid, fetch_insn_i_ready,
1536                        pred_insn_i_valid, pred_insn_o_ready,
1537                        pred_mask_o_valid, pred_mask_i_ready,
1538                        exec_insn_i_valid, exec_insn_o_ready,
1539                        exec_pc_o_valid, exec_pc_i_ready)
1540
1541         if self.svp64_en:
1542             self.fetch_predicate_fsm(m,
1543                                      pred_insn_i_valid, pred_insn_o_ready,
1544                                      pred_mask_o_valid, pred_mask_i_ready)
1545
1546         self.execute_fsm(m, core,
1547                          exec_insn_i_valid, exec_insn_o_ready,
1548                          exec_pc_o_valid, exec_pc_i_ready)
1549
1550         # whatever was done above, over-ride it if core reset is held
1551         with m.If(core_rst):
1552             sync += nia.eq(0)
1553
1554         return m
1555
1556
1557 class TestIssuer(Elaboratable):
1558     def __init__(self, pspec):
1559         self.ti = TestIssuerInternal(pspec)
1560         self.pll = DummyPLL(instance=True)
1561
1562         self.dbg_rst_i = Signal(reset_less=True)
1563
1564         # PLL direct clock or not
1565         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
1566         if self.pll_en:
1567             self.pll_test_o = Signal(reset_less=True)
1568             self.pll_vco_o = Signal(reset_less=True)
1569             self.clk_sel_i = Signal(2, reset_less=True)
1570             self.ref_clk = ClockSignal()  # can't rename it but that's ok
1571             self.pllclk_clk = ClockSignal("pllclk")
1572
1573     def elaborate(self, platform):
1574         m = Module()
1575         comb = m.d.comb
1576
1577         # TestIssuer nominally runs at main clock, actually it is
1578         # all combinatorial internally except for coresync'd components
1579         m.submodules.ti = ti = self.ti
1580
1581         if self.pll_en:
1582             # ClockSelect runs at PLL output internal clock rate
1583             m.submodules.wrappll = pll = self.pll
1584
1585             # add clock domains from PLL
1586             cd_pll = ClockDomain("pllclk")
1587             m.domains += cd_pll
1588
1589             # PLL clock established.  has the side-effect of running clklsel
1590             # at the PLL's speed (see DomainRenamer("pllclk") above)
1591             pllclk = self.pllclk_clk
1592             comb += pllclk.eq(pll.clk_pll_o)
1593
1594             # wire up external 24mhz to PLL
1595             #comb += pll.clk_24_i.eq(self.ref_clk)
1596             # output 18 mhz PLL test signal, and analog oscillator out
1597             comb += self.pll_test_o.eq(pll.pll_test_o)
1598             comb += self.pll_vco_o.eq(pll.pll_vco_o)
1599
1600             # input to pll clock selection
1601             comb += pll.clk_sel_i.eq(self.clk_sel_i)
1602
1603             # now wire up ResetSignals.  don't mind them being in this domain
1604             pll_rst = ResetSignal("pllclk")
1605             comb += pll_rst.eq(ResetSignal())
1606
1607         # internal clock is set to selector clock-out.  has the side-effect of
1608         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1609         # debug clock runs at coresync internal clock
1610         if self.ti.dbg_domain != 'sync':
1611             cd_dbgsync = ClockDomain("dbgsync")
1612         intclk = ClockSignal(self.ti.core_domain)
1613         dbgclk = ClockSignal(self.ti.dbg_domain)
1614         # XXX BYPASS PLL XXX
1615         # XXX BYPASS PLL XXX
1616         # XXX BYPASS PLL XXX
1617         if self.pll_en:
1618             comb += intclk.eq(self.ref_clk)
1619             assert self.ti.core_domain != 'sync', \
1620                 "cannot set core_domain to sync and use pll at the same time"
1621         else:
1622             if self.ti.core_domain != 'sync':
1623                 comb += intclk.eq(ClockSignal())
1624         if self.ti.dbg_domain != 'sync':
1625             dbgclk = ClockSignal(self.ti.dbg_domain)
1626             comb += dbgclk.eq(intclk)
1627         comb += self.ti.dbg_rst_i.eq(self.dbg_rst_i)
1628
1629         return m
1630
1631     def ports(self):
1632         return list(self.ti.ports()) + list(self.pll.ports()) + \
1633             [ClockSignal(), ResetSignal()]
1634
1635     def external_ports(self):
1636         ports = self.ti.external_ports()
1637         ports.append(ClockSignal())
1638         ports.append(ResetSignal())
1639         if self.pll_en:
1640             ports.append(self.clk_sel_i)
1641             ports.append(self.pll.clk_24_i)
1642             ports.append(self.pll_test_o)
1643             ports.append(self.pll_vco_o)
1644             ports.append(self.pllclk_clk)
1645             ports.append(self.ref_clk)
1646         return ports
1647
1648
1649 if __name__ == '__main__':
1650     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1651              'spr': 1,
1652              'div': 1,
1653              'mul': 1,
1654              'shiftrot': 1
1655              }
1656     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
1657                          imem_ifacetype='bare_wb',
1658                          addr_wid=48,
1659                          mask_wid=8,
1660                          reg_wid=64,
1661                          units=units)
1662     dut = TestIssuer(pspec)
1663     vl = main(dut, ports=dut.ports(), name="test_issuer")
1664
1665     if len(sys.argv) == 1:
1666         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
1667         with open("test_issuer.il", "w") as f:
1668             f.write(vl)