src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # JTAG interface.  add this right at the start because if it's
  64         # added it *modifies* the pspec, by adding enable/disable signals
  65         # for parts of the rest of the core
  66         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  67         if self.jtag_en:
  68             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  69                       'pwm', 'sd0', 'sdr'}
  70             self.jtag = JTAG(get_pinspecs(subset=subset))
  71             # add signals to pspec to enable/disable icache and dcache
  72             # (or data and intstruction wishbone if icache/dcache not included)
  73             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  74             # TODO: do we actually care if these are not domain-synchronised?
  75             # honestly probably not.
  76             pspec.wb_icache_en = self.jtag.wb_icache_en
  77             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  78             self.wb_sram_en = self.jtag.wb_sram_en
  79         else:
  80             self.wb_sram_en = Const(1)
  81
  82         # add 4k sram blocks?
  83         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  84                          pspec.sram4x4kblock == True)
  85         if self.sram4x4k:
  86             self.sram4k = []
  87             for i in range(4):
  88                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i))
  89
  90         # add interrupt controller?
  91         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  92         if self.xics:
  93             self.xics_icp = XICS_ICP()
  94             self.xics_ics = XICS_ICS()
  95             self.int_level_i = self.xics_ics.int_level_i
  96
  97         # add GPIO peripheral?
  98         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
  99         if self.gpio:
 100             self.simple_gpio = SimpleGPIO()
 101             self.gpio_o = self.simple_gpio.gpio_o
 102
 103         # main instruction core25
 104         self.core = core = NonProductionCore(pspec)
 105
 106         # instruction decoder.  goes into Trap Record
 107         pdecode = create_pdecode()
 108         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 109         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 110                                      opkls=IssuerDecode2ToOperand)
 111         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 112
 113         # Test Instruction memory
 114         self.imem = ConfigFetchUnit(pspec).fu
 115         # one-row cache of instruction read
 116         self.iline = Signal(64) # one instruction line
 117         self.iprev_adr = Signal(64) # previous address: if different, do read
 118
 119         # DMI interface
 120         self.dbg = CoreDebug()
 121
 122         # instruction go/monitor
 123         self.pc_o = Signal(64, reset_less=True)
 124         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 125         self.svstate_i = Data(32, "svstate_i") # ditto
 126         self.core_bigendian_i = Signal()
 127         self.busy_o = Signal(reset_less=True)
 128         self.memerr_o = Signal(reset_less=True)
 129
 130         # STATE regfile read /write ports for PC, MSR, SVSTATE
 131         staterf = self.core.regs.rf['state']
 132         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 133         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 134         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 135         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 136         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 137
 138         # DMI interface access
 139         intrf = self.core.regs.rf['int']
 140         crrf = self.core.regs.rf['cr']
 141         xerrf = self.core.regs.rf['xer']
 142         self.int_r = intrf.r_ports['dmi'] # INT read
 143         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 144         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 145
 146         # hack method of keeping an eye on whether branch/trap set the PC
 147         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 148         self.state_nia.wen.name = 'state_nia_wen'
 149
 150     def fetch_fsm(self, m, core, dbg, pc, svstate, pc_changed, insn_done,
 151                         core_rst,
 152                         fetch_pc_ready_o, fetch_pc_valid_i,
 153                         fetch_insn_valid_o, fetch_insn_ready_i):
 154         """fetch FSM
 155         this FSM performs fetch of raw instruction data, partial-decodes
 156         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 157         read a 2nd 32-bit quantity if that occurs.
 158         """
 159         comb = m.d.comb
 160         sync = m.d.sync
 161         pdecode2 = self.pdecode2
 162         svp64 = self.svp64
 163         cur_state = self.cur_state
 164
 165         # latches copy of raw fetched instruction
 166         fetch_insn_o = Signal(32, reset_less=True)
 167         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 168         sync += dec_opcode_i.eq(fetch_insn_o)  # actual opcode
 169
 170         msr_read = Signal(reset=1)
 171
 172         # address of the next instruction, in the absence of a branch
 173         # depends on the instruction size
 174         nia = Signal(64, reset_less=True)
 175
 176         with m.FSM(name='fetch_fsm'):
 177
 178             # waiting (zzz)
 179             with m.State("IDLE"):
 180                 with m.If(~dbg.core_stop_o & ~core_rst):
 181                     comb += fetch_pc_ready_o.eq(1)
 182                     with m.If(fetch_pc_valid_i):
 183                         # instruction allowed to go: start by reading the PC
 184                         # capture the PC and also drop it into Insn Memory
 185                         # we have joined a pair of combinatorial memory
 186                         # lookups together.  this is Generally Bad.
 187                         comb += self.imem.a_pc_i.eq(pc)
 188                         comb += self.imem.a_valid_i.eq(1)
 189                         comb += self.imem.f_valid_i.eq(1)
 190                         sync += cur_state.pc.eq(pc)
 191                         sync += cur_state.svstate.eq(svstate) # and svstate
 192
 193                         # initiate read of MSR. arrives one clock later
 194                         comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 195                         sync += msr_read.eq(0)
 196
 197                         m.next = "INSN_READ"  # move to "wait for bus" phase
 198                 with m.Else():
 199                     comb += core.core_stopped_i.eq(1)
 200                     comb += dbg.core_stopped_i.eq(1)
 201
 202             # dummy pause to find out why simulation is not keeping up
 203             with m.State("INSN_READ"):
 204                 # one cycle later, msr/sv read arrives.  valid only once.
 205                 with m.If(~msr_read):
 206                     sync += msr_read.eq(1) # yeah don't read it again
 207                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 208                 with m.If(self.imem.f_busy_o): # zzz...
 209                     # busy: stay in wait-read
 210                     comb += self.imem.a_valid_i.eq(1)
 211                     comb += self.imem.f_valid_i.eq(1)
 212                 with m.Else():
 213                     # not busy: instruction fetched
 214                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 215                     # decode the SVP64 prefix, if any
 216                     comb += svp64.raw_opcode_in.eq(insn)
 217                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 218                     # pass the decoded prefix (if any) to PowerDecoder2
 219                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 220                     # calculate the address of the following instruction
 221                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 222                     sync += nia.eq(cur_state.pc + insn_size)
 223                     with m.If(~svp64.is_svp64_mode):
 224                         # with no prefix, store the instruction
 225                         # and hand it directly to the next FSM
 226                         comb += fetch_insn_o.eq(insn)
 227                         m.next = "INSN_READY"
 228                     with m.Else():
 229                         # fetch the rest of the instruction from memory
 230                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 231                         comb += self.imem.a_valid_i.eq(1)
 232                         comb += self.imem.f_valid_i.eq(1)
 233                         m.next = "INSN_READ2"
 234
 235             with m.State("INSN_READ2"):
 236                 with m.If(self.imem.f_busy_o):  # zzz...
 237                     # busy: stay in wait-read
 238                     comb += self.imem.a_valid_i.eq(1)
 239                     comb += self.imem.f_valid_i.eq(1)
 240                 with m.Else():
 241                     # not busy: instruction fetched
 242                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 243                     comb += fetch_insn_o.eq(insn)
 244                     m.next = "INSN_READY"
 245
 246             with m.State("INSN_READY"):
 247                 # hand over the instruction, to be decoded
 248                 comb += fetch_insn_valid_o.eq(1)
 249                 with m.If(fetch_insn_ready_i):
 250                     m.next = "IDLE"
 251
 252         # code-morph: moving the actual PC-setting out of "execute"
 253         # so that it's easier to move this into an "issue" FSM.
 254
 255         # ok here we are not reading the branch unit.  TODO
 256         # this just blithely overwrites whatever pipeline
 257         # updated the PC
 258         core_busy_o = core.busy_o                 # core is busy
 259         with m.If(insn_done & (~pc_changed) & (~core_busy_o)):
 260             comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 261             comb += self.state_w_pc.data_i.eq(nia)
 262
 263     def issue_fsm(self, m, core, pc_changed, sv_changed,
 264                   fetch_pc_ready_o, fetch_pc_valid_i,
 265                   fetch_insn_valid_o, fetch_insn_ready_i,
 266                   exec_insn_valid_i, exec_insn_ready_o,
 267                   exec_pc_valid_o, exec_pc_ready_i):
 268         """issue FSM
 269
 270         decode / issue FSM.  this interacts with the "fetch" FSM
 271         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 272         (outgoing). also interacts with the "execute" FSM
 273         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 274         (incoming).
 275         SVP64 RM prefixes have already been set up by the
 276         "fetch" phase, so execute is fairly straightforward.
 277         """
 278
 279         comb = m.d.comb
 280         sync = m.d.sync
 281         pdecode2 = self.pdecode2
 282         cur_state = self.cur_state
 283
 284         # temporaries
 285         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 286
 287         # for updating svstate (things like srcstep etc.)
 288         update_svstate = Signal() # set this (below) if updating
 289         new_svstate = SVSTATERec("new_svstate")
 290         comb += new_svstate.eq(cur_state.svstate)
 291
 292         with m.FSM(name="issue_fsm"):
 293
 294             # go fetch the instruction at the current PC
 295             # at this point, there is no instruction running, that
 296             # could inadvertently update the PC.
 297             with m.State("INSN_FETCH"):
 298                 # TODO: update PC here, before fetch
 299                 comb += fetch_pc_valid_i.eq(1)
 300                 with m.If(fetch_pc_ready_o):
 301                     m.next = "INSN_WAIT"
 302
 303             # decode the instruction when it arrives
 304             with m.State("INSN_WAIT"):
 305                 comb += fetch_insn_ready_i.eq(1)
 306                 with m.If(fetch_insn_valid_o):
 307                     # decode the instruction
 308                     sync += core.e.eq(pdecode2.e)
 309                     sync += core.state.eq(cur_state)
 310                     sync += core.raw_insn_i.eq(dec_opcode_i)
 311                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 312                     # TODO: loop into INSN_FETCH if it's a vector instruction
 313                     #       and VL == 0.  this because VL==0 is a for-loop
 314                     #       from 0 to 0 i.e. always, always a NOP.
 315                     m.next = "INSN_EXECUTE"  # move to "execute"
 316
 317             with m.State("INSN_EXECUTE"):
 318                 comb += exec_insn_valid_i.eq(1)
 319                 with m.If(exec_insn_ready_o):
 320                     m.next = "EXECUTE_WAIT"
 321
 322             with m.State("EXECUTE_WAIT"):
 323                 comb += exec_pc_ready_i.eq(1)
 324                 with m.If(exec_pc_valid_o):
 325                     # TODO: update SRCSTEP here (in new_svstate)
 326                     #       and set update_svstate to True *as long as*
 327                     #       PC / SVSTATE was not modified.  that's an
 328                     #       exception (or setvl was called)
 329                     # TODO: loop into INSN_EXECUTE if it's a vector instruction
 330                     #       and SRCSTEP != VL-1 and PowerDecoder.no_out_vec
 331                     #       is True
 332                     #       unless PC / SVSTATE was modified, in that case do
 333                     #       go back to INSN_FETCH.
 334                     m.next = "INSN_FETCH"
 335
 336         # check if svstate needs updating: if so, write it to State Regfile
 337         with m.If(update_svstate):
 338             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 339             comb += self.state_w_sv.data_i.eq(new_svstate)
 340             sync += cur_state.svstate.eq(new_svstate) # for next clock
 341
 342     def execute_fsm(self, m, core, insn_done, pc_changed, sv_changed,
 343                     exec_insn_valid_i, exec_insn_ready_o,
 344                     exec_pc_valid_o, exec_pc_ready_i):
 345         """execute FSM
 346
 347         execute FSM. this interacts with the "issue" FSM
 348         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 349         (outgoing). SVP64 RM prefixes have already been set up by the
 350         "issue" phase, so execute is fairly straightforward.
 351         """
 352
 353         comb = m.d.comb
 354         sync = m.d.sync
 355         pdecode2 = self.pdecode2
 356         svp64 = self.svp64
 357
 358         # temporaries
 359         core_busy_o = core.busy_o                 # core is busy
 360         core_ivalid_i = core.ivalid_i             # instruction is valid
 361         core_issue_i = core.issue_i               # instruction is issued
 362         insn_type = core.e.do.insn_type           # instruction MicroOp type
 363
 364         with m.FSM(name="exec_fsm"):
 365
 366             # waiting for instruction bus (stays there until not busy)
 367             with m.State("INSN_START"):
 368                 comb += exec_insn_ready_o.eq(1)
 369                 with m.If(exec_insn_valid_i):
 370                     comb += core_ivalid_i.eq(1)  # instruction is valid
 371                     comb += core_issue_i.eq(1)  # and issued
 372                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 373
 374             # instruction started: must wait till it finishes
 375             with m.State("INSN_ACTIVE"):
 376                 with m.If(insn_type != MicrOp.OP_NOP):
 377                     comb += core_ivalid_i.eq(1) # instruction is valid
 378                 # note changes to PC and SVSTATE
 379                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 380                     sync += sv_changed.eq(1)
 381                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 382                     sync += pc_changed.eq(1)
 383                 with m.If(~core_busy_o): # instruction done!
 384                     comb += insn_done.eq(1)
 385                     sync += core.e.eq(0)
 386                     sync += core.raw_insn_i.eq(0)
 387                     sync += core.bigendian_i.eq(0)
 388                     sync += sv_changed.eq(0)
 389                     sync += pc_changed.eq(0)
 390                     comb += exec_pc_valid_o.eq(1)
 391                     with m.If(exec_pc_ready_i):
 392                         m.next = "INSN_START"  # back to fetch
 393
 394     def elaborate(self, platform):
 395         m = Module()
 396         comb, sync = m.d.comb, m.d.sync
 397
 398         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 399         m.submodules.imem = imem = self.imem
 400         m.submodules.dbg = dbg = self.dbg
 401         if self.jtag_en:
 402             m.submodules.jtag = jtag = self.jtag
 403             # TODO: UART2GDB mux, here, from external pin
 404             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 405             sync += dbg.dmi.connect_to(jtag.dmi)
 406
 407         cur_state = self.cur_state
 408
 409         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 410         if self.sram4x4k:
 411             for i, sram in enumerate(self.sram4k):
 412                 m.submodules["sram4k_%d" % i] = sram
 413                 comb += sram.enable.eq(self.wb_sram_en)
 414
 415         # XICS interrupt handler
 416         if self.xics:
 417             m.submodules.xics_icp = icp = self.xics_icp
 418             m.submodules.xics_ics = ics = self.xics_ics
 419             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 420             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 421
 422         # GPIO test peripheral
 423         if self.gpio:
 424             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 425
 426         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 427         # XXX causes litex ECP5 test to get wrong idea about input and output
 428         # (but works with verilator sim *sigh*)
 429         #if self.gpio and self.xics:
 430         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 431
 432         # instruction decoder
 433         pdecode = create_pdecode()
 434         m.submodules.dec2 = pdecode2 = self.pdecode2
 435         m.submodules.svp64 = svp64 = self.svp64
 436
 437         # convenience
 438         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 439         intrf = self.core.regs.rf['int']
 440
 441         # clock delay power-on reset
 442         cd_por  = ClockDomain(reset_less=True)
 443         cd_sync = ClockDomain()
 444         core_sync = ClockDomain("coresync")
 445         m.domains += cd_por, cd_sync, core_sync
 446
 447         ti_rst = Signal(reset_less=True)
 448         delay = Signal(range(4), reset=3)
 449         with m.If(delay != 0):
 450             m.d.por += delay.eq(delay - 1)
 451         comb += cd_por.clk.eq(ClockSignal())
 452
 453         # power-on reset delay
 454         core_rst = ResetSignal("coresync")
 455         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 456         comb += core_rst.eq(ti_rst)
 457
 458         # busy/halted signals from core
 459         comb += self.busy_o.eq(core.busy_o)
 460         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 461
 462         # temporary hack: says "go" immediately for both address gen and ST
 463         l0 = core.l0
 464         ldst = core.fus.fus['ldst0']
 465         st_go_edge = rising_edge(m, ldst.st.rel_o)
 466         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 467         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 468
 469         # PC and instruction from I-Memory
 470         comb += self.pc_o.eq(cur_state.pc)
 471         pc_changed = Signal() # note write to PC
 472         sv_changed = Signal() # note write to SVSTATE
 473         insn_done = Signal()  # fires just once
 474
 475         # read the PC
 476         pc = Signal(64, reset_less=True)
 477         pc_ok_delay = Signal()
 478         sync += pc_ok_delay.eq(~self.pc_i.ok)
 479         with m.If(self.pc_i.ok):
 480             # incoming override (start from pc_i)
 481             comb += pc.eq(self.pc_i.data)
 482         with m.Else():
 483             # otherwise read StateRegs regfile for PC...
 484             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 485         # ... but on a 1-clock delay
 486         with m.If(pc_ok_delay):
 487             comb += pc.eq(self.state_r_pc.data_o)
 488
 489         # read svstate
 490         svstate = Signal(64, reset_less=True)
 491         svstate_ok_delay = Signal()
 492         sync += svstate_ok_delay.eq(~self.svstate_i.ok)
 493         with m.If(self.svstate_i.ok):
 494             # incoming override (start from svstate__i)
 495             comb += svstate.eq(self.svstate_i.data)
 496         with m.Else():
 497             # otherwise read StateRegs regfile for SVSTATE...
 498             comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 499         # ... but on a 1-clock delay
 500         with m.If(svstate_ok_delay):
 501             comb += svstate.eq(self.state_r_sv.data_o)
 502
 503         # don't write pc every cycle
 504         comb += self.state_w_pc.wen.eq(0)
 505         comb += self.state_w_pc.data_i.eq(0)
 506
 507         # don't read msr every cycle
 508         comb += self.state_r_msr.ren.eq(0)
 509
 510         # connect up debug signals
 511         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 512         comb += dbg.terminate_i.eq(core.core_terminate_o)
 513         comb += dbg.state.pc.eq(pc)
 514         comb += dbg.state.svstate.eq(svstate)
 515         comb += dbg.state.msr.eq(cur_state.msr)
 516
 517         # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
 518         # these are the handshake signals between fetch and decode/execute
 519
 520         # fetch FSM can run as soon as the PC is valid
 521         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 522         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 523
 524         # fetch FSM hands over the instruction to be decoded / issued
 525         fetch_insn_valid_o = Signal()
 526         fetch_insn_ready_i = Signal()
 527
 528         # issue FSM delivers the instruction to the be executed
 529         exec_insn_valid_i = Signal()
 530         exec_insn_ready_o = Signal()
 531
 532         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 533         exec_pc_valid_o = Signal()
 534         exec_pc_ready_i = Signal()
 535
 536         # actually use a nmigen FSM for the first time (w00t)
 537         # this FSM is perhaps unusual in that it detects conditions
 538         # then "holds" information, combinatorially, for the core
 539         # (as opposed to using sync - which would be on a clock's delay)
 540         # this includes the actual opcode, valid flags and so on.
 541
 542         self.fetch_fsm(m, core, dbg, pc, svstate, pc_changed, insn_done,
 543                        core_rst,
 544                        fetch_pc_ready_o, fetch_pc_valid_i,
 545                        fetch_insn_valid_o, fetch_insn_ready_i)
 546
 547         # TODO: an SVSTATE-based for-loop FSM that goes in between
 548         # fetch pc/insn ready/valid and advances SVSTATE.srcstep
 549         # until it reaches VL-1 or PowerDecoder2.no_out_vec is True.
 550         self.issue_fsm(m, core, pc_changed, sv_changed,
 551                        fetch_pc_ready_o, fetch_pc_valid_i,
 552                        fetch_insn_valid_o, fetch_insn_ready_i,
 553                        exec_insn_valid_i, exec_insn_ready_o,
 554                        exec_pc_ready_i, exec_pc_valid_o)
 555
 556         self.execute_fsm(m, core, insn_done, pc_changed, sv_changed,
 557                          exec_insn_valid_i, exec_insn_ready_o,
 558                          exec_pc_ready_i, exec_pc_valid_o)
 559
 560         # this bit doesn't have to be in the FSM: connect up to read
 561         # regfiles on demand from DMI
 562         with m.If(d_reg.req): # request for regfile access being made
 563             # TODO: error-check this
 564             # XXX should this be combinatorial?  sync better?
 565             if intrf.unary:
 566                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 567             else:
 568                 comb += self.int_r.addr.eq(d_reg.addr)
 569                 comb += self.int_r.ren.eq(1)
 570         d_reg_delay  = Signal()
 571         sync += d_reg_delay.eq(d_reg.req)
 572         with m.If(d_reg_delay):
 573             # data arrives one clock later
 574             comb += d_reg.data.eq(self.int_r.data_o)
 575             comb += d_reg.ack.eq(1)
 576
 577         # sigh same thing for CR debug
 578         with m.If(d_cr.req): # request for regfile access being made
 579             comb += self.cr_r.ren.eq(0b11111111) # enable all
 580         d_cr_delay  = Signal()
 581         sync += d_cr_delay.eq(d_cr.req)
 582         with m.If(d_cr_delay):
 583             # data arrives one clock later
 584             comb += d_cr.data.eq(self.cr_r.data_o)
 585             comb += d_cr.ack.eq(1)
 586
 587         # aaand XER...
 588         with m.If(d_xer.req): # request for regfile access being made
 589             comb += self.xer_r.ren.eq(0b111111) # enable all
 590         d_xer_delay  = Signal()
 591         sync += d_xer_delay.eq(d_xer.req)
 592         with m.If(d_xer_delay):
 593             # data arrives one clock later
 594             comb += d_xer.data.eq(self.xer_r.data_o)
 595             comb += d_xer.ack.eq(1)
 596
 597         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 598         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 599         self.tb_dec_fsm(m, cur_state.dec)
 600
 601         return m
 602
 603     def tb_dec_fsm(self, m, spr_dec):
 604         """tb_dec_fsm
 605
 606         this is a FSM for updating either dec or tb.  it runs alternately
 607         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 608         value to DEC, however the regfile has "passthrough" on it so this
 609         *should* be ok.
 610
 611         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 612         """
 613
 614         comb, sync = m.d.comb, m.d.sync
 615         fast_rf = self.core.regs.rf['fast']
 616         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 617         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 618
 619         with m.FSM() as fsm:
 620
 621             # initiates read of current DEC
 622             with m.State("DEC_READ"):
 623                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 624                 comb += fast_r_dectb.ren.eq(1)
 625                 m.next = "DEC_WRITE"
 626
 627             # waits for DEC read to arrive (1 cycle), updates with new value
 628             with m.State("DEC_WRITE"):
 629                 new_dec = Signal(64)
 630                 # TODO: MSR.LPCR 32-bit decrement mode
 631                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 632                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 633                 comb += fast_w_dectb.wen.eq(1)
 634                 comb += fast_w_dectb.data_i.eq(new_dec)
 635                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 636                 m.next = "TB_READ"
 637
 638             # initiates read of current TB
 639             with m.State("TB_READ"):
 640                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 641                 comb += fast_r_dectb.ren.eq(1)
 642                 m.next = "TB_WRITE"
 643
 644             # waits for read TB to arrive, initiates write of current TB
 645             with m.State("TB_WRITE"):
 646                 new_tb = Signal(64)
 647                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 648                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 649                 comb += fast_w_dectb.wen.eq(1)
 650                 comb += fast_w_dectb.data_i.eq(new_tb)
 651                 m.next = "DEC_READ"
 652
 653         return m
 654
 655     def __iter__(self):
 656         yield from self.pc_i.ports()
 657         yield self.pc_o
 658         yield self.memerr_o
 659         yield from self.core.ports()
 660         yield from self.imem.ports()
 661         yield self.core_bigendian_i
 662         yield self.busy_o
 663
 664     def ports(self):
 665         return list(self)
 666
 667     def external_ports(self):
 668         ports = self.pc_i.ports()
 669         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 670                 ]
 671
 672         if self.jtag_en:
 673             ports += list(self.jtag.external_ports())
 674         else:
 675             # don't add DMI if JTAG is enabled
 676             ports += list(self.dbg.dmi.ports())
 677
 678         ports += list(self.imem.ibus.fields.values())
 679         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 680
 681         if self.sram4x4k:
 682             for sram in self.sram4k:
 683                 ports += list(sram.bus.fields.values())
 684
 685         if self.xics:
 686             ports += list(self.xics_icp.bus.fields.values())
 687             ports += list(self.xics_ics.bus.fields.values())
 688             ports.append(self.int_level_i)
 689
 690         if self.gpio:
 691             ports += list(self.simple_gpio.bus.fields.values())
 692             ports.append(self.gpio_o)
 693
 694         return ports
 695
 696     def ports(self):
 697         return list(self)
 698
 699
 700 class TestIssuer(Elaboratable):
 701     def __init__(self, pspec):
 702         self.ti = TestIssuerInternal(pspec)
 703
 704         self.pll = DummyPLL()
 705
 706         # PLL direct clock or not
 707         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 708         if self.pll_en:
 709             self.pll_18_o = Signal(reset_less=True)
 710
 711     def elaborate(self, platform):
 712         m = Module()
 713         comb = m.d.comb
 714
 715         # TestIssuer runs at direct clock
 716         m.submodules.ti = ti = self.ti
 717         cd_int = ClockDomain("coresync")
 718
 719         if self.pll_en:
 720             # ClockSelect runs at PLL output internal clock rate
 721             m.submodules.pll = pll = self.pll
 722
 723             # add clock domains from PLL
 724             cd_pll = ClockDomain("pllclk")
 725             m.domains += cd_pll
 726
 727             # PLL clock established.  has the side-effect of running clklsel
 728             # at the PLL's speed (see DomainRenamer("pllclk") above)
 729             pllclk = ClockSignal("pllclk")
 730             comb += pllclk.eq(pll.clk_pll_o)
 731
 732             # wire up external 24mhz to PLL
 733             comb += pll.clk_24_i.eq(ClockSignal())
 734
 735             # output 18 mhz PLL test signal
 736             comb += self.pll_18_o.eq(pll.pll_18_o)
 737
 738             # now wire up ResetSignals.  don't mind them being in this domain
 739             pll_rst = ResetSignal("pllclk")
 740             comb += pll_rst.eq(ResetSignal())
 741
 742         # internal clock is set to selector clock-out.  has the side-effect of
 743         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 744         intclk = ClockSignal("coresync")
 745         if self.pll_en:
 746             comb += intclk.eq(pll.clk_pll_o)
 747         else:
 748             comb += intclk.eq(ClockSignal())
 749
 750         return m
 751
 752     def ports(self):
 753         return list(self.ti.ports()) + list(self.pll.ports()) + \
 754                [ClockSignal(), ResetSignal()]
 755
 756     def external_ports(self):
 757         ports = self.ti.external_ports()
 758         ports.append(ClockSignal())
 759         ports.append(ResetSignal())
 760         if self.pll_en:
 761             ports.append(self.pll.clk_sel_i)
 762             ports.append(self.pll_18_o)
 763             ports.append(self.pll.pll_lck_o)
 764         return ports
 765
 766
 767 if __name__ == '__main__':
 768     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 769              'spr': 1,
 770              'div': 1,
 771              'mul': 1,
 772              'shiftrot': 1
 773             }
 774     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 775                          imem_ifacetype='bare_wb',
 776                          addr_wid=48,
 777                          mask_wid=8,
 778                          reg_wid=64,
 779                          units=units)
 780     dut = TestIssuer(pspec)
 781     vl = main(dut, ports=dut.ports(), name="test_issuer")
 782
 783     if len(sys.argv) == 1:
 784         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 785         with open("test_issuer.il", "w") as f:
 786             f.write(vl)