src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # test is SVP64 is to be enabled
  64         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
  65
  66         # JTAG interface.  add this right at the start because if it's
  67         # added it *modifies* the pspec, by adding enable/disable signals
  68         # for parts of the rest of the core
  69         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  70         if self.jtag_en:
  71             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  72                       'pwm', 'sd0', 'sdr'}
  73             self.jtag = JTAG(get_pinspecs(subset=subset))
  74             # add signals to pspec to enable/disable icache and dcache
  75             # (or data and intstruction wishbone if icache/dcache not included)
  76             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  77             # TODO: do we actually care if these are not domain-synchronised?
  78             # honestly probably not.
  79             pspec.wb_icache_en = self.jtag.wb_icache_en
  80             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  81             self.wb_sram_en = self.jtag.wb_sram_en
  82         else:
  83             self.wb_sram_en = Const(1)
  84
  85         # add 4k sram blocks?
  86         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  87                          pspec.sram4x4kblock == True)
  88         if self.sram4x4k:
  89             self.sram4k = []
  90             for i in range(4):
  91                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
  92                                                     features={'err'}))
  93
  94         # add interrupt controller?
  95         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  96         if self.xics:
  97             self.xics_icp = XICS_ICP()
  98             self.xics_ics = XICS_ICS()
  99             self.int_level_i = self.xics_ics.int_level_i
 100
 101         # add GPIO peripheral?
 102         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
 103         if self.gpio:
 104             self.simple_gpio = SimpleGPIO()
 105             self.gpio_o = self.simple_gpio.gpio_o
 106
 107         # main instruction core25
 108         self.core = core = NonProductionCore(pspec)
 109
 110         # instruction decoder.  goes into Trap Record
 111         pdecode = create_pdecode()
 112         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 113         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 114                                      opkls=IssuerDecode2ToOperand,
 115                                      svp64_en=self.svp64_en)
 116         if self.svp64_en:
 117             self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 118
 119         # Test Instruction memory
 120         self.imem = ConfigFetchUnit(pspec).fu
 121         # one-row cache of instruction read
 122         self.iline = Signal(64) # one instruction line
 123         self.iprev_adr = Signal(64) # previous address: if different, do read
 124
 125         # DMI interface
 126         self.dbg = CoreDebug()
 127
 128         # instruction go/monitor
 129         self.pc_o = Signal(64, reset_less=True)
 130         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 131         self.svstate_i = Data(32, "svstate_i") # ditto
 132         self.core_bigendian_i = Signal()
 133         self.busy_o = Signal(reset_less=True)
 134         self.memerr_o = Signal(reset_less=True)
 135
 136         # STATE regfile read /write ports for PC, MSR, SVSTATE
 137         staterf = self.core.regs.rf['state']
 138         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 139         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 140         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 141         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 142         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 143
 144         # DMI interface access
 145         intrf = self.core.regs.rf['int']
 146         crrf = self.core.regs.rf['cr']
 147         xerrf = self.core.regs.rf['xer']
 148         self.int_r = intrf.r_ports['dmi'] # INT read
 149         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 150         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 151
 152         # hack method of keeping an eye on whether branch/trap set the PC
 153         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 154         self.state_nia.wen.name = 'state_nia_wen'
 155
 156         # pulse to synchronize the simulator at instruction end
 157         self.insn_done = Signal()
 158
 159         if self.svp64_en:
 160             # store copies of predicate masks
 161             self.srcmask = Signal(64)
 162             self.dstmask = Signal(64)
 163
 164     def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
 165                         fetch_pc_ready_o, fetch_pc_valid_i,
 166                         fetch_insn_valid_o, fetch_insn_ready_i):
 167         """fetch FSM
 168         this FSM performs fetch of raw instruction data, partial-decodes
 169         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 170         read a 2nd 32-bit quantity if that occurs.
 171         """
 172         comb = m.d.comb
 173         sync = m.d.sync
 174         pdecode2 = self.pdecode2
 175         cur_state = self.cur_state
 176         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 177
 178         msr_read = Signal(reset=1)
 179
 180         with m.FSM(name='fetch_fsm'):
 181
 182             # waiting (zzz)
 183             with m.State("IDLE"):
 184                 comb += fetch_pc_ready_o.eq(1)
 185                 with m.If(fetch_pc_valid_i):
 186                     # instruction allowed to go: start by reading the PC
 187                     # capture the PC and also drop it into Insn Memory
 188                     # we have joined a pair of combinatorial memory
 189                     # lookups together.  this is Generally Bad.
 190                     comb += self.imem.a_pc_i.eq(pc)
 191                     comb += self.imem.a_valid_i.eq(1)
 192                     comb += self.imem.f_valid_i.eq(1)
 193                     sync += cur_state.pc.eq(pc)
 194                     sync += cur_state.svstate.eq(svstate) # and svstate
 195
 196                     # initiate read of MSR. arrives one clock later
 197                     comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 198                     sync += msr_read.eq(0)
 199
 200                     m.next = "INSN_READ"  # move to "wait for bus" phase
 201
 202             # dummy pause to find out why simulation is not keeping up
 203             with m.State("INSN_READ"):
 204                 # one cycle later, msr/sv read arrives.  valid only once.
 205                 with m.If(~msr_read):
 206                     sync += msr_read.eq(1) # yeah don't read it again
 207                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 208                 with m.If(self.imem.f_busy_o): # zzz...
 209                     # busy: stay in wait-read
 210                     comb += self.imem.a_valid_i.eq(1)
 211                     comb += self.imem.f_valid_i.eq(1)
 212                 with m.Else():
 213                     # not busy: instruction fetched
 214                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 215                     if self.svp64_en:
 216                         svp64 = self.svp64
 217                         # decode the SVP64 prefix, if any
 218                         comb += svp64.raw_opcode_in.eq(insn)
 219                         comb += svp64.bigendian.eq(self.core_bigendian_i)
 220                         # pass the decoded prefix (if any) to PowerDecoder2
 221                         sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 222                         # remember whether this is a prefixed instruction, so
 223                         # the FSM can readily loop when VL==0
 224                         sync += is_svp64_mode.eq(svp64.is_svp64_mode)
 225                         # calculate the address of the following instruction
 226                         insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 227                         sync += nia.eq(cur_state.pc + insn_size)
 228                         with m.If(~svp64.is_svp64_mode):
 229                             # with no prefix, store the instruction
 230                             # and hand it directly to the next FSM
 231                             sync += dec_opcode_i.eq(insn)
 232                             m.next = "INSN_READY"
 233                         with m.Else():
 234                             # fetch the rest of the instruction from memory
 235                             comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 236                             comb += self.imem.a_valid_i.eq(1)
 237                             comb += self.imem.f_valid_i.eq(1)
 238                             m.next = "INSN_READ2"
 239                     else:
 240                         # not SVP64 - 32-bit only
 241                         sync += nia.eq(cur_state.pc + 4)
 242                         sync += dec_opcode_i.eq(insn)
 243                         m.next = "INSN_READY"
 244
 245             with m.State("INSN_READ2"):
 246                 with m.If(self.imem.f_busy_o):  # zzz...
 247                     # busy: stay in wait-read
 248                     comb += self.imem.a_valid_i.eq(1)
 249                     comb += self.imem.f_valid_i.eq(1)
 250                 with m.Else():
 251                     # not busy: instruction fetched
 252                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 253                     sync += dec_opcode_i.eq(insn)
 254                     m.next = "INSN_READY"
 255                     # TODO: probably can start looking at pdecode2.rm_dec
 256                     # here (or maybe even in INSN_READ state, if svp64_mode
 257                     # detected, in order to trigger - and wait for - the
 258                     # predicate reading.
 259
 260             with m.State("INSN_READY"):
 261                 # hand over the instruction, to be decoded
 262                 comb += fetch_insn_valid_o.eq(1)
 263                 with m.If(fetch_insn_ready_i):
 264                     m.next = "IDLE"
 265
 266     def fetch_predicate_fsm(self, m, core, TODO):
 267         """fetch_predicate_fsm - obtains (constructs in the case of CR)
 268            src/dest predicate masks
 269
 270         https://bugs.libre-soc.org/show_bug.cgi?id=617
 271         the predicates can be read here, by using IntRegs r_ports['pred']
 272         or CRRegs r_ports['pred'].  in the case of CRs it will have to
 273         be done through multiple reads, extracting one relevant at a time.
 274         later, a faster way would be to use the 32-bit-wide CR port but
 275         this is more complex decoding, here.  equivalent code used in
 276         ISACaller is "from soc.decoder.isa.caller import get_predcr"
 277         """
 278         comb = m.d.comb
 279         sync = m.d.sync
 280         pdecode2 = self.pdecode2
 281         rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
 282         predmode = rm_dec.predmode
 283         srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
 284
 285     def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
 286                   dbg, core_rst, is_svp64_mode,
 287                   fetch_pc_ready_o, fetch_pc_valid_i,
 288                   fetch_insn_valid_o, fetch_insn_ready_i,
 289                   exec_insn_valid_i, exec_insn_ready_o,
 290                   exec_pc_valid_o, exec_pc_ready_i):
 291         """issue FSM
 292
 293         decode / issue FSM.  this interacts with the "fetch" FSM
 294         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 295         (outgoing). also interacts with the "execute" FSM
 296         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 297         (incoming).
 298         SVP64 RM prefixes have already been set up by the
 299         "fetch" phase, so execute is fairly straightforward.
 300         """
 301
 302         comb = m.d.comb
 303         sync = m.d.sync
 304         pdecode2 = self.pdecode2
 305         cur_state = self.cur_state
 306
 307         # temporaries
 308         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 309
 310         # for updating svstate (things like srcstep etc.)
 311         update_svstate = Signal() # set this (below) if updating
 312         new_svstate = SVSTATERec("new_svstate")
 313         comb += new_svstate.eq(cur_state.svstate)
 314
 315         with m.FSM(name="issue_fsm"):
 316
 317             # sync with the "fetch" phase which is reading the instruction
 318             # at this point, there is no instruction running, that
 319             # could inadvertently update the PC.
 320             with m.State("ISSUE_START"):
 321                 # wait on "core stop" release, before next fetch
 322                 # need to do this here, in case we are in a VL==0 loop
 323                 with m.If(~dbg.core_stop_o & ~core_rst):
 324                     comb += fetch_pc_valid_i.eq(1) # tell fetch to start
 325                     with m.If(fetch_pc_ready_o):   # fetch acknowledged us
 326                         m.next = "INSN_WAIT"
 327                 with m.Else():
 328                     # tell core it's stopped, and acknowledge debug handshake
 329                     comb += core.core_stopped_i.eq(1)
 330                     comb += dbg.core_stopped_i.eq(1)
 331                     # while stopped, allow updating the PC and SVSTATE
 332                     with m.If(self.pc_i.ok):
 333                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 334                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 335                         sync += pc_changed.eq(1)
 336                     with m.If(self.svstate_i.ok):
 337                         comb += new_svstate.eq(self.svstate_i.data)
 338                         comb += update_svstate.eq(1)
 339                         sync += sv_changed.eq(1)
 340
 341             # decode the instruction when it arrives
 342             with m.State("INSN_WAIT"):
 343                 comb += fetch_insn_ready_i.eq(1)
 344                 with m.If(fetch_insn_valid_o):
 345                     # decode the instruction
 346                     sync += core.e.eq(pdecode2.e)
 347                     sync += core.state.eq(cur_state)
 348                     sync += core.raw_insn_i.eq(dec_opcode_i)
 349                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 350                     # set RA_OR_ZERO detection in satellite decoders
 351                     sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
 352                     # loop into ISSUE_START if it's a SVP64 instruction
 353                     # and VL == 0.  this because VL==0 is a for-loop
 354                     # from 0 to 0 i.e. always, always a NOP.
 355                     cur_vl = cur_state.svstate.vl
 356                     with m.If(is_svp64_mode & (cur_vl == 0)):
 357                         # update the PC before fetching the next instruction
 358                         # since we are in a VL==0 loop, no instruction was
 359                         # executed that we could be overwriting
 360                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 361                         comb += self.state_w_pc.data_i.eq(nia)
 362                         comb += self.insn_done.eq(1)
 363                         m.next = "ISSUE_START"
 364                     with m.Else():
 365                         m.next = "INSN_EXECUTE"  # move to "execute"
 366
 367             # handshake with execution FSM, move to "wait" once acknowledged
 368             with m.State("INSN_EXECUTE"):
 369                 # with m.If(is_svp64_mode):
 370                 #    TODO advance src/dst step to "skip" over predicated-out
 371                 #    from self.srcmask and self.dstmask
 372                 #    https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
 373                 #    but still without exceeding VL in either case
 374                 comb += exec_insn_valid_i.eq(1) # trigger execute
 375                 with m.If(exec_insn_ready_o):   # execute acknowledged us
 376                     m.next = "EXECUTE_WAIT"
 377
 378             with m.State("EXECUTE_WAIT"):
 379                 # wait on "core stop" release, at instruction end
 380                 # need to do this here, in case we are in a VL>1 loop
 381                 with m.If(~dbg.core_stop_o & ~core_rst):
 382                     comb += exec_pc_ready_i.eq(1)
 383                     with m.If(exec_pc_valid_o):
 384                         # precalculate srcstep+1 and dststep+1
 385                         next_srcstep = Signal.like(cur_state.svstate.srcstep)
 386                         next_dststep = Signal.like(cur_state.svstate.dststep)
 387                         comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
 388                         comb += next_dststep.eq(cur_state.svstate.dststep+1)
 389
 390                         # was this the last loop iteration?
 391                         is_last = Signal()
 392                         cur_vl = cur_state.svstate.vl
 393                         comb += is_last.eq(next_srcstep == cur_vl)
 394
 395                         # if either PC or SVSTATE were changed by the previous
 396                         # instruction, go directly back to Fetch, without
 397                         # updating either PC or SVSTATE
 398                         with m.If(pc_changed | sv_changed):
 399                             m.next = "ISSUE_START"
 400
 401                         # also return to Fetch, when no output was a vector
 402                         # (regardless of SRCSTEP and VL), or when the last
 403                         # instruction was really the last one of the VL loop
 404                         with m.Elif((~pdecode2.loop_continue) | is_last):
 405                             # before going back to fetch, update the PC state
 406                             # register with the NIA.
 407                             # ok here we are not reading the branch unit.
 408                             # TODO: this just blithely overwrites whatever
 409                             #       pipeline updated the PC
 410                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 411                             comb += self.state_w_pc.data_i.eq(nia)
 412                             # reset SRCSTEP before returning to Fetch
 413                             with m.If(pdecode2.loop_continue):
 414                                 comb += new_svstate.srcstep.eq(0)
 415                                 comb += new_svstate.dststep.eq(0)
 416                                 comb += update_svstate.eq(1)
 417                             m.next = "ISSUE_START"
 418
 419                         # returning to Execute? then, first update SRCSTEP
 420                         with m.Else():
 421                             comb += new_svstate.srcstep.eq(next_srcstep)
 422                             comb += new_svstate.dststep.eq(next_dststep)
 423                             comb += update_svstate.eq(1)
 424                             m.next = "DECODE_SV"
 425
 426                 with m.Else():
 427                     comb += core.core_stopped_i.eq(1)
 428                     comb += dbg.core_stopped_i.eq(1)
 429                     # while stopped, allow updating the PC and SVSTATE
 430                     with m.If(self.pc_i.ok):
 431                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 432                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 433                         sync += pc_changed.eq(1)
 434                     with m.If(self.svstate_i.ok):
 435                         comb += new_svstate.eq(self.svstate_i.data)
 436                         comb += update_svstate.eq(1)
 437                         sync += sv_changed.eq(1)
 438
 439             # need to decode the instruction again, after updating SRCSTEP
 440             # in the previous state.
 441             # mostly a copy of INSN_WAIT, but without the actual wait
 442             with m.State("DECODE_SV"):
 443                 # decode the instruction
 444                 sync += core.e.eq(pdecode2.e)
 445                 sync += core.state.eq(cur_state)
 446                 sync += core.bigendian_i.eq(self.core_bigendian_i)
 447                 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
 448                 m.next = "INSN_EXECUTE"  # move to "execute"
 449
 450         # check if svstate needs updating: if so, write it to State Regfile
 451         with m.If(update_svstate):
 452             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 453             comb += self.state_w_sv.data_i.eq(new_svstate)
 454             sync += cur_state.svstate.eq(new_svstate) # for next clock
 455
 456     def execute_fsm(self, m, core, pc_changed, sv_changed,
 457                     exec_insn_valid_i, exec_insn_ready_o,
 458                     exec_pc_valid_o, exec_pc_ready_i):
 459         """execute FSM
 460
 461         execute FSM. this interacts with the "issue" FSM
 462         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 463         (outgoing). SVP64 RM prefixes have already been set up by the
 464         "issue" phase, so execute is fairly straightforward.
 465         """
 466
 467         comb = m.d.comb
 468         sync = m.d.sync
 469         pdecode2 = self.pdecode2
 470
 471         # temporaries
 472         core_busy_o = core.busy_o                 # core is busy
 473         core_ivalid_i = core.ivalid_i             # instruction is valid
 474         core_issue_i = core.issue_i               # instruction is issued
 475         insn_type = core.e.do.insn_type           # instruction MicroOp type
 476
 477         with m.FSM(name="exec_fsm"):
 478
 479             # waiting for instruction bus (stays there until not busy)
 480             with m.State("INSN_START"):
 481                 comb += exec_insn_ready_o.eq(1)
 482                 with m.If(exec_insn_valid_i):
 483                     comb += core_ivalid_i.eq(1)  # instruction is valid
 484                     comb += core_issue_i.eq(1)  # and issued
 485                     sync += sv_changed.eq(0)
 486                     sync += pc_changed.eq(0)
 487                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 488
 489             # instruction started: must wait till it finishes
 490             with m.State("INSN_ACTIVE"):
 491                 with m.If(insn_type != MicrOp.OP_NOP):
 492                     comb += core_ivalid_i.eq(1) # instruction is valid
 493                 # note changes to PC and SVSTATE
 494                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 495                     sync += sv_changed.eq(1)
 496                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 497                     sync += pc_changed.eq(1)
 498                 with m.If(~core_busy_o): # instruction done!
 499                     comb += exec_pc_valid_o.eq(1)
 500                     with m.If(exec_pc_ready_i):
 501                         comb += self.insn_done.eq(1)
 502                         m.next = "INSN_START"  # back to fetch
 503
 504     def elaborate(self, platform):
 505         m = Module()
 506         comb, sync = m.d.comb, m.d.sync
 507
 508         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 509         m.submodules.imem = imem = self.imem
 510         m.submodules.dbg = dbg = self.dbg
 511         if self.jtag_en:
 512             m.submodules.jtag = jtag = self.jtag
 513             # TODO: UART2GDB mux, here, from external pin
 514             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 515             sync += dbg.dmi.connect_to(jtag.dmi)
 516
 517         cur_state = self.cur_state
 518
 519         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 520         if self.sram4x4k:
 521             for i, sram in enumerate(self.sram4k):
 522                 m.submodules["sram4k_%d" % i] = sram
 523                 comb += sram.enable.eq(self.wb_sram_en)
 524
 525         # XICS interrupt handler
 526         if self.xics:
 527             m.submodules.xics_icp = icp = self.xics_icp
 528             m.submodules.xics_ics = ics = self.xics_ics
 529             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 530             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 531
 532         # GPIO test peripheral
 533         if self.gpio:
 534             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 535
 536         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 537         # XXX causes litex ECP5 test to get wrong idea about input and output
 538         # (but works with verilator sim *sigh*)
 539         #if self.gpio and self.xics:
 540         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 541
 542         # instruction decoder
 543         pdecode = create_pdecode()
 544         m.submodules.dec2 = pdecode2 = self.pdecode2
 545         if self.svp64_en:
 546             m.submodules.svp64 = svp64 = self.svp64
 547
 548         # convenience
 549         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 550         intrf = self.core.regs.rf['int']
 551
 552         # clock delay power-on reset
 553         cd_por  = ClockDomain(reset_less=True)
 554         cd_sync = ClockDomain()
 555         core_sync = ClockDomain("coresync")
 556         m.domains += cd_por, cd_sync, core_sync
 557
 558         ti_rst = Signal(reset_less=True)
 559         delay = Signal(range(4), reset=3)
 560         with m.If(delay != 0):
 561             m.d.por += delay.eq(delay - 1)
 562         comb += cd_por.clk.eq(ClockSignal())
 563
 564         # power-on reset delay
 565         core_rst = ResetSignal("coresync")
 566         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 567         comb += core_rst.eq(ti_rst)
 568
 569         # busy/halted signals from core
 570         comb += self.busy_o.eq(core.busy_o)
 571         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 572
 573         # temporary hack: says "go" immediately for both address gen and ST
 574         l0 = core.l0
 575         ldst = core.fus.fus['ldst0']
 576         st_go_edge = rising_edge(m, ldst.st.rel_o)
 577         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 578         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 579
 580         # PC and instruction from I-Memory
 581         comb += self.pc_o.eq(cur_state.pc)
 582         pc_changed = Signal() # note write to PC
 583         sv_changed = Signal() # note write to SVSTATE
 584
 585         # read the PC
 586         pc = Signal(64, reset_less=True)
 587         pc_ok_delay = Signal()
 588         sync += pc_ok_delay.eq(~self.pc_i.ok)
 589         with m.If(self.pc_i.ok):
 590             # incoming override (start from pc_i)
 591             comb += pc.eq(self.pc_i.data)
 592         with m.Else():
 593             # otherwise read StateRegs regfile for PC...
 594             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 595         # ... but on a 1-clock delay
 596         with m.If(pc_ok_delay):
 597             comb += pc.eq(self.state_r_pc.data_o)
 598
 599         # read svstate
 600         svstate = Signal(64, reset_less=True)
 601         svstate_ok_delay = Signal()
 602         sync += svstate_ok_delay.eq(~self.svstate_i.ok)
 603         with m.If(self.svstate_i.ok):
 604             # incoming override (start from svstate__i)
 605             comb += svstate.eq(self.svstate_i.data)
 606         with m.Else():
 607             # otherwise read StateRegs regfile for SVSTATE...
 608             comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 609         # ... but on a 1-clock delay
 610         with m.If(svstate_ok_delay):
 611             comb += svstate.eq(self.state_r_sv.data_o)
 612
 613         # don't write pc every cycle
 614         comb += self.state_w_pc.wen.eq(0)
 615         comb += self.state_w_pc.data_i.eq(0)
 616
 617         # don't read msr every cycle
 618         comb += self.state_r_msr.ren.eq(0)
 619
 620         # address of the next instruction, in the absence of a branch
 621         # depends on the instruction size
 622         nia = Signal(64, reset_less=True)
 623
 624         # connect up debug signals
 625         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 626         comb += dbg.terminate_i.eq(core.core_terminate_o)
 627         comb += dbg.state.pc.eq(pc)
 628         comb += dbg.state.svstate.eq(svstate)
 629         comb += dbg.state.msr.eq(cur_state.msr)
 630
 631         # pass the prefix mode from Fetch to Issue, so the latter can loop
 632         # on VL==0
 633         is_svp64_mode = Signal()
 634
 635         # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
 636         # these are the handshake signals between fetch and decode/execute
 637
 638         # fetch FSM can run as soon as the PC is valid
 639         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 640         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 641
 642         # fetch FSM hands over the instruction to be decoded / issued
 643         fetch_insn_valid_o = Signal()
 644         fetch_insn_ready_i = Signal()
 645
 646         # issue FSM delivers the instruction to the be executed
 647         exec_insn_valid_i = Signal()
 648         exec_insn_ready_o = Signal()
 649
 650         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 651         exec_pc_valid_o = Signal()
 652         exec_pc_ready_i = Signal()
 653
 654         # the FSMs here are perhaps unusual in that they detect conditions
 655         # then "hold" information, combinatorially, for the core
 656         # (as opposed to using sync - which would be on a clock's delay)
 657         # this includes the actual opcode, valid flags and so on.
 658
 659         # Fetch, then Issue, then Execute. Issue is where the VL for-loop
 660         # lives.  the ready/valid signalling is used to communicate between
 661         # the three.
 662
 663         self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
 664                        fetch_pc_ready_o, fetch_pc_valid_i,
 665                        fetch_insn_valid_o, fetch_insn_ready_i)
 666
 667         self.issue_fsm(m, core, pc_changed, sv_changed, nia,
 668                        dbg, core_rst, is_svp64_mode,
 669                        fetch_pc_ready_o, fetch_pc_valid_i,
 670                        fetch_insn_valid_o, fetch_insn_ready_i,
 671                        exec_insn_valid_i, exec_insn_ready_o,
 672                        exec_pc_valid_o, exec_pc_ready_i)
 673
 674         self.execute_fsm(m, core, pc_changed, sv_changed,
 675                          exec_insn_valid_i, exec_insn_ready_o,
 676                          exec_pc_valid_o, exec_pc_ready_i)
 677
 678         # this bit doesn't have to be in the FSM: connect up to read
 679         # regfiles on demand from DMI
 680         self.do_dmi(m, dbg)
 681
 682         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 683         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 684         self.tb_dec_fsm(m, cur_state.dec)
 685
 686         return m
 687
 688     def do_dmi(self, m, dbg):
 689         comb = m.d.comb
 690         sync = m.d.sync
 691         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 692         intrf = self.core.regs.rf['int']
 693
 694         with m.If(d_reg.req): # request for regfile access being made
 695             # TODO: error-check this
 696             # XXX should this be combinatorial?  sync better?
 697             if intrf.unary:
 698                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 699             else:
 700                 comb += self.int_r.addr.eq(d_reg.addr)
 701                 comb += self.int_r.ren.eq(1)
 702         d_reg_delay  = Signal()
 703         sync += d_reg_delay.eq(d_reg.req)
 704         with m.If(d_reg_delay):
 705             # data arrives one clock later
 706             comb += d_reg.data.eq(self.int_r.data_o)
 707             comb += d_reg.ack.eq(1)
 708
 709         # sigh same thing for CR debug
 710         with m.If(d_cr.req): # request for regfile access being made
 711             comb += self.cr_r.ren.eq(0b11111111) # enable all
 712         d_cr_delay  = Signal()
 713         sync += d_cr_delay.eq(d_cr.req)
 714         with m.If(d_cr_delay):
 715             # data arrives one clock later
 716             comb += d_cr.data.eq(self.cr_r.data_o)
 717             comb += d_cr.ack.eq(1)
 718
 719         # aaand XER...
 720         with m.If(d_xer.req): # request for regfile access being made
 721             comb += self.xer_r.ren.eq(0b111111) # enable all
 722         d_xer_delay  = Signal()
 723         sync += d_xer_delay.eq(d_xer.req)
 724         with m.If(d_xer_delay):
 725             # data arrives one clock later
 726             comb += d_xer.data.eq(self.xer_r.data_o)
 727             comb += d_xer.ack.eq(1)
 728
 729     def tb_dec_fsm(self, m, spr_dec):
 730         """tb_dec_fsm
 731
 732         this is a FSM for updating either dec or tb.  it runs alternately
 733         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 734         value to DEC, however the regfile has "passthrough" on it so this
 735         *should* be ok.
 736
 737         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 738         """
 739
 740         comb, sync = m.d.comb, m.d.sync
 741         fast_rf = self.core.regs.rf['fast']
 742         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 743         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 744
 745         with m.FSM() as fsm:
 746
 747             # initiates read of current DEC
 748             with m.State("DEC_READ"):
 749                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 750                 comb += fast_r_dectb.ren.eq(1)
 751                 m.next = "DEC_WRITE"
 752
 753             # waits for DEC read to arrive (1 cycle), updates with new value
 754             with m.State("DEC_WRITE"):
 755                 new_dec = Signal(64)
 756                 # TODO: MSR.LPCR 32-bit decrement mode
 757                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 758                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 759                 comb += fast_w_dectb.wen.eq(1)
 760                 comb += fast_w_dectb.data_i.eq(new_dec)
 761                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 762                 m.next = "TB_READ"
 763
 764             # initiates read of current TB
 765             with m.State("TB_READ"):
 766                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 767                 comb += fast_r_dectb.ren.eq(1)
 768                 m.next = "TB_WRITE"
 769
 770             # waits for read TB to arrive, initiates write of current TB
 771             with m.State("TB_WRITE"):
 772                 new_tb = Signal(64)
 773                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 774                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 775                 comb += fast_w_dectb.wen.eq(1)
 776                 comb += fast_w_dectb.data_i.eq(new_tb)
 777                 m.next = "DEC_READ"
 778
 779         return m
 780
 781     def __iter__(self):
 782         yield from self.pc_i.ports()
 783         yield self.pc_o
 784         yield self.memerr_o
 785         yield from self.core.ports()
 786         yield from self.imem.ports()
 787         yield self.core_bigendian_i
 788         yield self.busy_o
 789
 790     def ports(self):
 791         return list(self)
 792
 793     def external_ports(self):
 794         ports = self.pc_i.ports()
 795         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 796                 ]
 797
 798         if self.jtag_en:
 799             ports += list(self.jtag.external_ports())
 800         else:
 801             # don't add DMI if JTAG is enabled
 802             ports += list(self.dbg.dmi.ports())
 803
 804         ports += list(self.imem.ibus.fields.values())
 805         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 806
 807         if self.sram4x4k:
 808             for sram in self.sram4k:
 809                 ports += list(sram.bus.fields.values())
 810
 811         if self.xics:
 812             ports += list(self.xics_icp.bus.fields.values())
 813             ports += list(self.xics_ics.bus.fields.values())
 814             ports.append(self.int_level_i)
 815
 816         if self.gpio:
 817             ports += list(self.simple_gpio.bus.fields.values())
 818             ports.append(self.gpio_o)
 819
 820         return ports
 821
 822     def ports(self):
 823         return list(self)
 824
 825
 826 class TestIssuer(Elaboratable):
 827     def __init__(self, pspec):
 828         self.ti = TestIssuerInternal(pspec)
 829
 830         self.pll = DummyPLL()
 831
 832         # PLL direct clock or not
 833         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 834         if self.pll_en:
 835             self.pll_18_o = Signal(reset_less=True)
 836
 837     def elaborate(self, platform):
 838         m = Module()
 839         comb = m.d.comb
 840
 841         # TestIssuer runs at direct clock
 842         m.submodules.ti = ti = self.ti
 843         cd_int = ClockDomain("coresync")
 844
 845         if self.pll_en:
 846             # ClockSelect runs at PLL output internal clock rate
 847             m.submodules.pll = pll = self.pll
 848
 849             # add clock domains from PLL
 850             cd_pll = ClockDomain("pllclk")
 851             m.domains += cd_pll
 852
 853             # PLL clock established.  has the side-effect of running clklsel
 854             # at the PLL's speed (see DomainRenamer("pllclk") above)
 855             pllclk = ClockSignal("pllclk")
 856             comb += pllclk.eq(pll.clk_pll_o)
 857
 858             # wire up external 24mhz to PLL
 859             comb += pll.clk_24_i.eq(ClockSignal())
 860
 861             # output 18 mhz PLL test signal
 862             comb += self.pll_18_o.eq(pll.pll_18_o)
 863
 864             # now wire up ResetSignals.  don't mind them being in this domain
 865             pll_rst = ResetSignal("pllclk")
 866             comb += pll_rst.eq(ResetSignal())
 867
 868         # internal clock is set to selector clock-out.  has the side-effect of
 869         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 870         intclk = ClockSignal("coresync")
 871         if self.pll_en:
 872             comb += intclk.eq(pll.clk_pll_o)
 873         else:
 874             comb += intclk.eq(ClockSignal())
 875
 876         return m
 877
 878     def ports(self):
 879         return list(self.ti.ports()) + list(self.pll.ports()) + \
 880                [ClockSignal(), ResetSignal()]
 881
 882     def external_ports(self):
 883         ports = self.ti.external_ports()
 884         ports.append(ClockSignal())
 885         ports.append(ResetSignal())
 886         if self.pll_en:
 887             ports.append(self.pll.clk_sel_i)
 888             ports.append(self.pll_18_o)
 889             ports.append(self.pll.pll_lck_o)
 890         return ports
 891
 892
 893 if __name__ == '__main__':
 894     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 895              'spr': 1,
 896              'div': 1,
 897              'mul': 1,
 898              'shiftrot': 1
 899             }
 900     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 901                          imem_ifacetype='bare_wb',
 902                          addr_wid=48,
 903                          mask_wid=8,
 904                          reg_wid=64,
 905                          units=units)
 906     dut = TestIssuer(pspec)
 907     vl = main(dut, ports=dut.ports(), name="test_issuer")
 908
 909     if len(sys.argv) == 1:
 910         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 911         with open("test_issuer.il", "w") as f:
 912             f.write(vl)