src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.clock.select import ClockSelect
  41 from soc.clock.dummypll import DummyPLL
  42
  43
  44 from nmutil.util import rising_edge
  45
  46 def get_insn(f_instr_o, pc):
  47     if f_instr_o.width == 32:
  48         return f_instr_o
  49     else:
  50         # 64-bit: bit 2 of pc decides which word to select
  51         return f_instr_o.word_select(pc[2], 32)
  52
  53
  54 class TestIssuerInternal(Elaboratable):
  55     """TestIssuer - reads instructions from TestMemory and issues them
  56
  57     efficiency and speed is not the main goal here: functional correctness is.
  58     """
  59     def __init__(self, pspec):
  60
  61         # JTAG interface.  add this right at the start because if it's
  62         # added it *modifies* the pspec, by adding enable/disable signals
  63         # for parts of the rest of the core
  64         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  65         if self.jtag_en:
  66             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  67                       'pwm', 'sd0', 'sdr'}
  68             self.jtag = JTAG(get_pinspecs(subset=subset))
  69             # add signals to pspec to enable/disable icache and dcache
  70             # (or data and intstruction wishbone if icache/dcache not included)
  71             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  72             # TODO: do we actually care if these are not domain-synchronised?
  73             # honestly probably not.
  74             pspec.wb_icache_en = self.jtag.wb_icache_en
  75             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  76
  77         # add interrupt controller?
  78         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  79         if self.xics:
  80             self.xics_icp = XICS_ICP()
  81             self.xics_ics = XICS_ICS()
  82             self.int_level_i = self.xics_ics.int_level_i
  83
  84         # add GPIO peripheral?
  85         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
  86         if self.gpio:
  87             self.simple_gpio = SimpleGPIO()
  88             self.gpio_o = self.simple_gpio.gpio_o
  89
  90         # main instruction core25
  91         self.core = core = NonProductionCore(pspec)
  92
  93         # instruction decoder.  goes into Trap Record
  94         pdecode = create_pdecode()
  95         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT)
  96         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
  97                                      opkls=IssuerDecode2ToOperand)
  98         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
  99
 100         # Test Instruction memory
 101         self.imem = ConfigFetchUnit(pspec).fu
 102         # one-row cache of instruction read
 103         self.iline = Signal(64) # one instruction line
 104         self.iprev_adr = Signal(64) # previous address: if different, do read
 105
 106         # DMI interface
 107         self.dbg = CoreDebug()
 108
 109         # instruction go/monitor
 110         self.pc_o = Signal(64, reset_less=True)
 111         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 112         self.core_bigendian_i = Signal()
 113         self.busy_o = Signal(reset_less=True)
 114         self.memerr_o = Signal(reset_less=True)
 115
 116         # FAST regfile read /write ports for PC, MSR, DEC/TB
 117         staterf = self.core.regs.rf['state']
 118         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 119         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 120         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 121
 122         # DMI interface access
 123         intrf = self.core.regs.rf['int']
 124         crrf = self.core.regs.rf['cr']
 125         xerrf = self.core.regs.rf['xer']
 126         self.int_r = intrf.r_ports['dmi'] # INT read
 127         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 128         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 129
 130         # hack method of keeping an eye on whether branch/trap set the PC
 131         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 132         self.state_nia.wen.name = 'state_nia_wen'
 133
 134     def elaborate(self, platform):
 135         m = Module()
 136         comb, sync = m.d.comb, m.d.sync
 137
 138         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 139         m.submodules.imem = imem = self.imem
 140         m.submodules.dbg = dbg = self.dbg
 141         if self.jtag_en:
 142             m.submodules.jtag = jtag = self.jtag
 143             # TODO: UART2GDB mux, here, from external pin
 144             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 145             sync += dbg.dmi.connect_to(jtag.dmi)
 146
 147         cur_state = self.cur_state
 148
 149         # XICS interrupt handler
 150         if self.xics:
 151             m.submodules.xics_icp = icp = self.xics_icp
 152             m.submodules.xics_ics = ics = self.xics_ics
 153             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 154             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 155
 156         # GPIO test peripheral
 157         if self.gpio:
 158             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 159
 160         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 161         # XXX causes litex ECP5 test to get wrong idea about input and output
 162         # (but works with verilator sim *sigh*)
 163         #if self.gpio and self.xics:
 164         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 165
 166         # instruction decoder
 167         pdecode = create_pdecode()
 168         m.submodules.dec2 = pdecode2 = self.pdecode2
 169         m.submodules.svp64 = svp64 = self.svp64
 170
 171         # convenience
 172         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 173         intrf = self.core.regs.rf['int']
 174
 175         # clock delay power-on reset
 176         cd_por  = ClockDomain(reset_less=True)
 177         cd_sync = ClockDomain()
 178         core_sync = ClockDomain("coresync")
 179         m.domains += cd_por, cd_sync, core_sync
 180
 181         ti_rst = Signal(reset_less=True)
 182         delay = Signal(range(4), reset=3)
 183         with m.If(delay != 0):
 184             m.d.por += delay.eq(delay - 1)
 185         comb += cd_por.clk.eq(ClockSignal())
 186
 187         # power-on reset delay
 188         core_rst = ResetSignal("coresync")
 189         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 190         comb += core_rst.eq(ti_rst)
 191
 192         # busy/halted signals from core
 193         comb += self.busy_o.eq(core.busy_o)
 194         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 195
 196         # temporary hack: says "go" immediately for both address gen and ST
 197         l0 = core.l0
 198         ldst = core.fus.fus['ldst0']
 199         st_go_edge = rising_edge(m, ldst.st.rel_o)
 200         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 201         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 202
 203         # PC and instruction from I-Memory
 204         pc_changed = Signal() # note write to PC
 205         comb += self.pc_o.eq(cur_state.pc)
 206         ilatch = Signal(32)
 207
 208         # address of the next instruction, in the absence of a branch
 209         # depends on the instruction size
 210         nia = Signal(64, reset_less=True)
 211
 212         # read the PC
 213         pc = Signal(64, reset_less=True)
 214         pc_ok_delay = Signal()
 215         sync += pc_ok_delay.eq(~self.pc_i.ok)
 216         with m.If(self.pc_i.ok):
 217             # incoming override (start from pc_i)
 218             comb += pc.eq(self.pc_i.data)
 219         with m.Else():
 220             # otherwise read StateRegs regfile for PC...
 221             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 222         # ... but on a 1-clock delay
 223         with m.If(pc_ok_delay):
 224             comb += pc.eq(self.state_r_pc.data_o)
 225
 226         # don't write pc every cycle
 227         comb += self.state_w_pc.wen.eq(0)
 228         comb += self.state_w_pc.data_i.eq(0)
 229
 230         # don't read msr every cycle
 231         comb += self.state_r_msr.ren.eq(0)
 232         msr_read = Signal(reset=1)
 233
 234         # connect up debug signals
 235         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 236         comb += dbg.terminate_i.eq(core.core_terminate_o)
 237         comb += dbg.state.pc.eq(pc)
 238         #comb += dbg.state.pc.eq(cur_state.pc)
 239         comb += dbg.state.msr.eq(cur_state.msr)
 240
 241         # temporaries
 242         core_busy_o = core.busy_o                 # core is busy
 243         core_ivalid_i = core.ivalid_i             # instruction is valid
 244         core_issue_i = core.issue_i               # instruction is issued
 245         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 246
 247         insn_type = core.e.do.insn_type
 248
 249         # handshake signals between fetch and decode/execute
 250         # fetch FSM can run as soon as the PC is valid
 251         fetch_pc_valid_i = Signal()
 252         fetch_pc_ready_o = Signal()
 253         # when done, deliver the instruction to the next FSM
 254         fetch_insn_o = Signal(32, reset_less=True)
 255         fetch_insn_valid_o = Signal()
 256         fetch_insn_ready_i = Signal()
 257
 258         # actually use a nmigen FSM for the first time (w00t)
 259         # this FSM is perhaps unusual in that it detects conditions
 260         # then "holds" information, combinatorially, for the core
 261         # (as opposed to using sync - which would be on a clock's delay)
 262         # this includes the actual opcode, valid flags and so on.
 263
 264         # this FSM performs fetch of raw instruction data, partial-decodes
 265         # it 32-bit at a time to detect SVP64 prefixes, and will optionally
 266         # read a 2nd 32-bit quantity if that occurs.
 267
 268         with m.FSM(name='fetch_fsm'):
 269
 270             # waiting (zzz)
 271             with m.State("IDLE"):
 272                 with m.If(~dbg.core_stop_o & ~core_rst):
 273                     comb += fetch_pc_ready_o.eq(1)
 274                     with m.If(fetch_pc_valid_i):
 275                         # instruction allowed to go: start by reading the PC
 276                         # capture the PC and also drop it into Insn Memory
 277                         # we have joined a pair of combinatorial memory
 278                         # lookups together.  this is Generally Bad.
 279                         comb += self.imem.a_pc_i.eq(pc)
 280                         comb += self.imem.a_valid_i.eq(1)
 281                         comb += self.imem.f_valid_i.eq(1)
 282                         sync += cur_state.pc.eq(pc)
 283
 284                         # initiate read of MSR.  arrives one clock later
 285                         comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 286                         sync += msr_read.eq(0)
 287
 288                         m.next = "INSN_READ"  # move to "wait for bus" phase
 289                 with m.Else():
 290                     comb += core.core_stopped_i.eq(1)
 291                     comb += dbg.core_stopped_i.eq(1)
 292
 293             # dummy pause to find out why simulation is not keeping up
 294             with m.State("INSN_READ"):
 295                 # one cycle later, msr read arrives.  valid only once.
 296                 with m.If(~msr_read):
 297                     sync += msr_read.eq(1) # yeah don't read it again
 298                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 299                 with m.If(self.imem.f_busy_o): # zzz...
 300                     # busy: stay in wait-read
 301                     comb += self.imem.a_valid_i.eq(1)
 302                     comb += self.imem.f_valid_i.eq(1)
 303                 with m.Else():
 304                     # not busy: instruction fetched
 305                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 306                     # decode the SVP64 prefix, if any
 307                     comb += svp64.raw_opcode_in.eq(insn)
 308                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 309                     # pass the decoded prefix (if any) to PowerDecoder2
 310                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 311                     # calculate the address of the following instruction
 312                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 313                     sync += nia.eq(cur_state.pc + insn_size)
 314                     with m.If(~svp64.is_svp64_mode):
 315                         # with no prefix, store the instruction
 316                         # and hand it directly to the next FSM
 317                         sync += fetch_insn_o.eq(insn)
 318                         m.next = "INSN_READY"
 319                     with m.Else():
 320                         # fetch the rest of the instruction from memory
 321                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 322                         comb += self.imem.a_valid_i.eq(1)
 323                         comb += self.imem.f_valid_i.eq(1)
 324                         m.next = "INSN_READ2"
 325
 326             with m.State("INSN_READ2"):
 327                 with m.If(self.imem.f_busy_o):  # zzz...
 328                     # busy: stay in wait-read
 329                     comb += self.imem.a_valid_i.eq(1)
 330                     comb += self.imem.f_valid_i.eq(1)
 331                 with m.Else():
 332                     # not busy: instruction fetched
 333                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 334                     sync += fetch_insn_o.eq(insn)
 335                     m.next = "INSN_READY"
 336
 337             with m.State("INSN_READY"):
 338                 # hand over the instruction, to be decoded
 339                 comb += fetch_insn_valid_o.eq(1)
 340                 with m.If(fetch_insn_ready_i):
 341                     m.next = "IDLE"
 342
 343         # decode / issue / execute FSM.  this interacts with the "fetch" FSM
 344         # through fetch_pc_ready/valid (incoming) and fetch_insn_ready/valid
 345         # (outgoing).  SVP64 RM prefixes have already been set up by the
 346         # "fetch" phase, so execute is fairly straightforward.
 347
 348         with m.FSM():
 349
 350             # go fetch the instruction at the current PC
 351             # at this point, there is no instruction running, that
 352             # could inadvertently update the PC.
 353             with m.State("INSN_FETCH"):
 354                 comb += fetch_pc_valid_i.eq(1)
 355                 with m.If(fetch_pc_ready_o):
 356                     m.next = "INSN_WAIT"
 357
 358             # decode the instruction when it arrives
 359             with m.State("INSN_WAIT"):
 360                 comb += fetch_insn_ready_i.eq(1)
 361                 with m.If(fetch_insn_valid_o):
 362                     # decode the instruction
 363                     # TODO, before issuing new instruction first
 364                     # check if it's SVP64. (svp64.is_svp64_mode set)
 365                     # if yes, record the svp64_rm, put that into
 366                     # pdecode2.sv_rm, then read another 32 bits (INSN_FETCH2?)
 367                     comb += dec_opcode_i.eq(fetch_insn_o)  # actual opcode
 368                     sync += core.e.eq(pdecode2.e)
 369                     sync += core.state.eq(cur_state)
 370                     sync += core.raw_insn_i.eq(dec_opcode_i)
 371                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 372                     sync += ilatch.eq(insn) # latch current insn
 373                     # also drop PC and MSR into decode "state"
 374                     m.next = "INSN_START" # move to "start"
 375
 376             # waiting for instruction bus (stays there until not busy)
 377             with m.State("INSN_START"):
 378                 comb += core_ivalid_i.eq(1) # instruction is valid
 379                 comb += core_issue_i.eq(1)  # and issued
 380                 sync += pc_changed.eq(0)
 381
 382                 m.next = "INSN_ACTIVE" # move to "wait completion"
 383
 384             # instruction started: must wait till it finishes
 385             with m.State("INSN_ACTIVE"):
 386                 with m.If(insn_type != MicrOp.OP_NOP):
 387                     comb += core_ivalid_i.eq(1) # instruction is valid
 388                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 389                     sync += pc_changed.eq(1)
 390                 with m.If(~core_busy_o): # instruction done!
 391                     # ok here we are not reading the branch unit.  TODO
 392                     # this just blithely overwrites whatever pipeline
 393                     # updated the PC
 394                     with m.If(~pc_changed):
 395                         comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 396                         comb += self.state_w_pc.data_i.eq(nia)
 397                     sync += core.e.eq(0)
 398                     sync += core.raw_insn_i.eq(0)
 399                     sync += core.bigendian_i.eq(0)
 400                     m.next = "INSN_FETCH"  # back to fetch
 401
 402         # this bit doesn't have to be in the FSM: connect up to read
 403         # regfiles on demand from DMI
 404         with m.If(d_reg.req): # request for regfile access being made
 405             # TODO: error-check this
 406             # XXX should this be combinatorial?  sync better?
 407             if intrf.unary:
 408                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 409             else:
 410                 comb += self.int_r.addr.eq(d_reg.addr)
 411                 comb += self.int_r.ren.eq(1)
 412         d_reg_delay  = Signal()
 413         sync += d_reg_delay.eq(d_reg.req)
 414         with m.If(d_reg_delay):
 415             # data arrives one clock later
 416             comb += d_reg.data.eq(self.int_r.data_o)
 417             comb += d_reg.ack.eq(1)
 418
 419         # sigh same thing for CR debug
 420         with m.If(d_cr.req): # request for regfile access being made
 421             comb += self.cr_r.ren.eq(0b11111111) # enable all
 422         d_cr_delay  = Signal()
 423         sync += d_cr_delay.eq(d_cr.req)
 424         with m.If(d_cr_delay):
 425             # data arrives one clock later
 426             comb += d_cr.data.eq(self.cr_r.data_o)
 427             comb += d_cr.ack.eq(1)
 428
 429         # aaand XER...
 430         with m.If(d_xer.req): # request for regfile access being made
 431             comb += self.xer_r.ren.eq(0b111111) # enable all
 432         d_xer_delay  = Signal()
 433         sync += d_xer_delay.eq(d_xer.req)
 434         with m.If(d_xer_delay):
 435             # data arrives one clock later
 436             comb += d_xer.data.eq(self.xer_r.data_o)
 437             comb += d_xer.ack.eq(1)
 438
 439         # DEC and TB inc/dec FSM
 440         self.tb_dec_fsm(m, cur_state.dec)
 441
 442         return m
 443
 444     def tb_dec_fsm(self, m, spr_dec):
 445         """tb_dec_fsm
 446
 447         this is a FSM for updating either dec or tb.  it runs alternately
 448         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 449         value to DEC, however the regfile has "passthrough" on it so this
 450         *should* be ok.
 451
 452         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 453         """
 454
 455         comb, sync = m.d.comb, m.d.sync
 456         fast_rf = self.core.regs.rf['fast']
 457         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 458         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 459
 460         with m.FSM() as fsm:
 461
 462             # initiates read of current DEC
 463             with m.State("DEC_READ"):
 464                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 465                 comb += fast_r_dectb.ren.eq(1)
 466                 m.next = "DEC_WRITE"
 467
 468             # waits for DEC read to arrive (1 cycle), updates with new value
 469             with m.State("DEC_WRITE"):
 470                 new_dec = Signal(64)
 471                 # TODO: MSR.LPCR 32-bit decrement mode
 472                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 473                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 474                 comb += fast_w_dectb.wen.eq(1)
 475                 comb += fast_w_dectb.data_i.eq(new_dec)
 476                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 477                 m.next = "TB_READ"
 478
 479             # initiates read of current TB
 480             with m.State("TB_READ"):
 481                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 482                 comb += fast_r_dectb.ren.eq(1)
 483                 m.next = "TB_WRITE"
 484
 485             # waits for read TB to arrive, initiates write of current TB
 486             with m.State("TB_WRITE"):
 487                 new_tb = Signal(64)
 488                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 489                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 490                 comb += fast_w_dectb.wen.eq(1)
 491                 comb += fast_w_dectb.data_i.eq(new_tb)
 492                 m.next = "DEC_READ"
 493
 494         return m
 495
 496     def __iter__(self):
 497         yield from self.pc_i.ports()
 498         yield self.pc_o
 499         yield self.memerr_o
 500         yield from self.core.ports()
 501         yield from self.imem.ports()
 502         yield self.core_bigendian_i
 503         yield self.busy_o
 504
 505     def ports(self):
 506         return list(self)
 507
 508     def external_ports(self):
 509         ports = self.pc_i.ports()
 510         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 511                 ]
 512
 513         if self.jtag_en:
 514             ports += list(self.jtag.external_ports())
 515         else:
 516             # don't add DMI if JTAG is enabled
 517             ports += list(self.dbg.dmi.ports())
 518
 519         ports += list(self.imem.ibus.fields.values())
 520         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 521
 522         if self.xics:
 523             ports += list(self.xics_icp.bus.fields.values())
 524             ports += list(self.xics_ics.bus.fields.values())
 525             ports.append(self.int_level_i)
 526
 527         if self.gpio:
 528             ports += list(self.simple_gpio.bus.fields.values())
 529             ports.append(self.gpio_o)
 530
 531         return ports
 532
 533     def ports(self):
 534         return list(self)
 535
 536
 537 class TestIssuer(Elaboratable):
 538     def __init__(self, pspec):
 539         self.ti = TestIssuerInternal(pspec)
 540
 541         self.pll = DummyPLL()
 542
 543         # PLL direct clock or not
 544         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 545         if self.pll_en:
 546             self.pll_18_o = Signal(reset_less=True)
 547
 548     def elaborate(self, platform):
 549         m = Module()
 550         comb = m.d.comb
 551
 552         # TestIssuer runs at direct clock
 553         m.submodules.ti = ti = self.ti
 554         cd_int = ClockDomain("coresync")
 555
 556         if self.pll_en:
 557             # ClockSelect runs at PLL output internal clock rate
 558             m.submodules.pll = pll = self.pll
 559
 560             # add clock domains from PLL
 561             cd_pll = ClockDomain("pllclk")
 562             m.domains += cd_pll
 563
 564             # PLL clock established.  has the side-effect of running clklsel
 565             # at the PLL's speed (see DomainRenamer("pllclk") above)
 566             pllclk = ClockSignal("pllclk")
 567             comb += pllclk.eq(pll.clk_pll_o)
 568
 569             # wire up external 24mhz to PLL
 570             comb += pll.clk_24_i.eq(ClockSignal())
 571
 572             # output 18 mhz PLL test signal
 573             comb += self.pll_18_o.eq(pll.pll_18_o)
 574
 575             # now wire up ResetSignals.  don't mind them being in this domain
 576             pll_rst = ResetSignal("pllclk")
 577             comb += pll_rst.eq(ResetSignal())
 578
 579         # internal clock is set to selector clock-out.  has the side-effect of
 580         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 581         intclk = ClockSignal("coresync")
 582         if self.pll_en:
 583             comb += intclk.eq(pll.clk_pll_o)
 584         else:
 585             comb += intclk.eq(ClockSignal())
 586
 587         return m
 588
 589     def ports(self):
 590         return list(self.ti.ports()) + list(self.pll.ports()) + \
 591                [ClockSignal(), ResetSignal()]
 592
 593     def external_ports(self):
 594         ports = self.ti.external_ports()
 595         ports.append(ClockSignal())
 596         ports.append(ResetSignal())
 597         if self.pll_en:
 598             ports.append(self.pll.clk_sel_i)
 599             ports.append(self.pll_18_o)
 600             ports.append(self.pll.pll_lck_o)
 601         return ports
 602
 603
 604 if __name__ == '__main__':
 605     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 606              'spr': 1,
 607              'div': 1,
 608              'mul': 1,
 609              'shiftrot': 1
 610             }
 611     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 612                          imem_ifacetype='bare_wb',
 613                          addr_wid=48,
 614                          mask_wid=8,
 615                          reg_wid=64,
 616                          units=units)
 617     dut = TestIssuer(pspec)
 618     vl = main(dut, ports=dut.ports(), name="test_issuer")
 619
 620     if len(sys.argv) == 1:
 621         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 622         with open("test_issuer.il", "w") as f:
 623             f.write(vl)