3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from soc
.decoder
.power_decoder
import create_pdecode
25 from soc
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
26 from soc
.decoder
.decode2execute1
import IssuerDecode2ToOperand
27 from soc
.decoder
.decode2execute1
import Data
28 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
29 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
30 from soc
.simple
.core
import NonProductionCore
31 from soc
.config
.test
.test_loadstore
import TestMemPspec
32 from soc
.config
.ifetch
import ConfigFetchUnit
33 from soc
.decoder
.power_enums
import MicrOp
34 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
35 from soc
.debug
.jtag
import JTAG
36 from soc
.config
.pinouts
import get_pinspecs
37 from soc
.config
.state
import CoreState
38 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
39 from soc
.bus
.simple_gpio
import SimpleGPIO
40 from soc
.clock
.select
import ClockSelect
41 from soc
.clock
.dummypll
import DummyPLL
44 from nmutil
.util
import rising_edge
46 def get_insn(f_instr_o
, pc
):
47 if f_instr_o
.width
== 32:
50 # 64-bit: bit 2 of pc decides which word to select
51 return f_instr_o
.word_select(pc
[2], 32)
54 class TestIssuerInternal(Elaboratable
):
55 """TestIssuer - reads instructions from TestMemory and issues them
57 efficiency and speed is not the main goal here: functional correctness is.
59 def __init__(self
, pspec
):
61 # JTAG interface. add this right at the start because if it's
62 # added it *modifies* the pspec, by adding enable/disable signals
63 # for parts of the rest of the core
64 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
66 subset
= {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
68 self
.jtag
= JTAG(get_pinspecs(subset
=subset
))
69 # add signals to pspec to enable/disable icache and dcache
70 # (or data and intstruction wishbone if icache/dcache not included)
71 # https://bugs.libre-soc.org/show_bug.cgi?id=520
72 # TODO: do we actually care if these are not domain-synchronised?
73 # honestly probably not.
74 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
75 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
77 # add interrupt controller?
78 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
80 self
.xics_icp
= XICS_ICP()
81 self
.xics_ics
= XICS_ICS()
82 self
.int_level_i
= self
.xics_ics
.int_level_i
84 # add GPIO peripheral?
85 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
87 self
.simple_gpio
= SimpleGPIO()
88 self
.gpio_o
= self
.simple_gpio
.gpio_o
90 # main instruction core25
91 self
.core
= core
= NonProductionCore(pspec
)
93 # instruction decoder. goes into Trap Record
94 pdecode
= create_pdecode()
95 self
.cur_state
= CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
96 self
.pdecode2
= PowerDecode2(pdecode
, state
=self
.cur_state
,
97 opkls
=IssuerDecode2ToOperand
)
98 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
100 # Test Instruction memory
101 self
.imem
= ConfigFetchUnit(pspec
).fu
102 # one-row cache of instruction read
103 self
.iline
= Signal(64) # one instruction line
104 self
.iprev_adr
= Signal(64) # previous address: if different, do read
107 self
.dbg
= CoreDebug()
109 # instruction go/monitor
110 self
.pc_o
= Signal(64, reset_less
=True)
111 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
112 self
.core_bigendian_i
= Signal()
113 self
.busy_o
= Signal(reset_less
=True)
114 self
.memerr_o
= Signal(reset_less
=True)
116 # FAST regfile read /write ports for PC, MSR, DEC/TB, SVSTATE
117 staterf
= self
.core
.regs
.rf
['state']
118 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
119 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
120 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
121 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
122 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
124 # DMI interface access
125 intrf
= self
.core
.regs
.rf
['int']
126 crrf
= self
.core
.regs
.rf
['cr']
127 xerrf
= self
.core
.regs
.rf
['xer']
128 self
.int_r
= intrf
.r_ports
['dmi'] # INT read
129 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR read
130 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER read
132 # hack method of keeping an eye on whether branch/trap set the PC
133 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
134 self
.state_nia
.wen
.name
= 'state_nia_wen'
136 def elaborate(self
, platform
):
138 comb
, sync
= m
.d
.comb
, m
.d
.sync
140 m
.submodules
.core
= core
= DomainRenamer("coresync")(self
.core
)
141 m
.submodules
.imem
= imem
= self
.imem
142 m
.submodules
.dbg
= dbg
= self
.dbg
144 m
.submodules
.jtag
= jtag
= self
.jtag
145 # TODO: UART2GDB mux, here, from external pin
146 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
147 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
149 cur_state
= self
.cur_state
151 # XICS interrupt handler
153 m
.submodules
.xics_icp
= icp
= self
.xics_icp
154 m
.submodules
.xics_ics
= ics
= self
.xics_ics
155 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
156 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
158 # GPIO test peripheral
160 m
.submodules
.simple_gpio
= simple_gpio
= self
.simple_gpio
162 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
163 # XXX causes litex ECP5 test to get wrong idea about input and output
164 # (but works with verilator sim *sigh*)
165 #if self.gpio and self.xics:
166 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
168 # instruction decoder
169 pdecode
= create_pdecode()
170 m
.submodules
.dec2
= pdecode2
= self
.pdecode2
171 m
.submodules
.svp64
= svp64
= self
.svp64
174 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
175 intrf
= self
.core
.regs
.rf
['int']
177 # clock delay power-on reset
178 cd_por
= ClockDomain(reset_less
=True)
179 cd_sync
= ClockDomain()
180 core_sync
= ClockDomain("coresync")
181 m
.domains
+= cd_por
, cd_sync
, core_sync
183 ti_rst
= Signal(reset_less
=True)
184 delay
= Signal(range(4), reset
=3)
185 with m
.If(delay
!= 0):
186 m
.d
.por
+= delay
.eq(delay
- 1)
187 comb
+= cd_por
.clk
.eq(ClockSignal())
189 # power-on reset delay
190 core_rst
= ResetSignal("coresync")
191 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
192 comb
+= core_rst
.eq(ti_rst
)
194 # busy/halted signals from core
195 comb
+= self
.busy_o
.eq(core
.busy_o
)
196 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
198 # temporary hack: says "go" immediately for both address gen and ST
200 ldst
= core
.fus
.fus
['ldst0']
201 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
202 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
) # link addr-go direct to rel
203 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
205 # PC and instruction from I-Memory
206 pc_changed
= Signal() # note write to PC
207 comb
+= self
.pc_o
.eq(cur_state
.pc
)
210 # address of the next instruction, in the absence of a branch
211 # depends on the instruction size
212 nia
= Signal(64, reset_less
=True)
215 pc
= Signal(64, reset_less
=True)
216 pc_ok_delay
= Signal()
217 sync
+= pc_ok_delay
.eq(~self
.pc_i
.ok
)
218 with m
.If(self
.pc_i
.ok
):
219 # incoming override (start from pc_i)
220 comb
+= pc
.eq(self
.pc_i
.data
)
222 # otherwise read StateRegs regfile for PC...
223 comb
+= self
.state_r_pc
.ren
.eq(1<<StateRegs
.PC
)
224 # ... but on a 1-clock delay
225 with m
.If(pc_ok_delay
):
226 comb
+= pc
.eq(self
.state_r_pc
.data_o
)
228 # don't write pc every cycle
229 comb
+= self
.state_w_pc
.wen
.eq(0)
230 comb
+= self
.state_w_pc
.data_i
.eq(0)
232 # don't read msr or svstate every cycle
233 comb
+= self
.state_r_sv
.ren
.eq(0)
234 comb
+= self
.state_r_msr
.ren
.eq(0)
235 msr_read
= Signal(reset
=1)
236 sv_read
= Signal(reset
=1)
238 # connect up debug signals
239 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
240 comb
+= dbg
.terminate_i
.eq(core
.core_terminate_o
)
241 comb
+= dbg
.state
.pc
.eq(pc
)
242 #comb += dbg.state.pc.eq(cur_state.pc)
243 comb
+= dbg
.state
.msr
.eq(cur_state
.msr
)
246 core_busy_o
= core
.busy_o
# core is busy
247 core_ivalid_i
= core
.ivalid_i
# instruction is valid
248 core_issue_i
= core
.issue_i
# instruction is issued
249 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
251 insn_type
= core
.e
.do
.insn_type
253 # handshake signals between fetch and decode/execute
254 # fetch FSM can run as soon as the PC is valid
255 fetch_pc_valid_i
= Signal()
256 fetch_pc_ready_o
= Signal()
257 # when done, deliver the instruction to the next FSM
258 fetch_insn_o
= Signal(32, reset_less
=True)
259 fetch_insn_valid_o
= Signal()
260 fetch_insn_ready_i
= Signal()
262 # actually use a nmigen FSM for the first time (w00t)
263 # this FSM is perhaps unusual in that it detects conditions
264 # then "holds" information, combinatorially, for the core
265 # (as opposed to using sync - which would be on a clock's delay)
266 # this includes the actual opcode, valid flags and so on.
268 # this FSM performs fetch of raw instruction data, partial-decodes
269 # it 32-bit at a time to detect SVP64 prefixes, and will optionally
270 # read a 2nd 32-bit quantity if that occurs.
272 with m
.FSM(name
='fetch_fsm'):
275 with m
.State("IDLE"):
276 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
277 comb
+= fetch_pc_ready_o
.eq(1)
278 with m
.If(fetch_pc_valid_i
):
279 # instruction allowed to go: start by reading the PC
280 # capture the PC and also drop it into Insn Memory
281 # we have joined a pair of combinatorial memory
282 # lookups together. this is Generally Bad.
283 comb
+= self
.imem
.a_pc_i
.eq(pc
)
284 comb
+= self
.imem
.a_valid_i
.eq(1)
285 comb
+= self
.imem
.f_valid_i
.eq(1)
286 sync
+= cur_state
.pc
.eq(pc
)
288 # initiate read of MSR/SVSTATE. arrives one clock later
289 comb
+= self
.state_r_msr
.ren
.eq(1 << StateRegs
.MSR
)
290 comb
+= self
.state_r_sv
.ren
.eq(1 << StateRegs
.SVSTATE
)
291 sync
+= msr_read
.eq(0)
292 sync
+= sv_read
.eq(0)
294 m
.next
= "INSN_READ" # move to "wait for bus" phase
296 comb
+= core
.core_stopped_i
.eq(1)
297 comb
+= dbg
.core_stopped_i
.eq(1)
299 # dummy pause to find out why simulation is not keeping up
300 with m
.State("INSN_READ"):
301 # one cycle later, msr/sv read arrives. valid only once.
302 with m
.If(~msr_read
):
303 sync
+= msr_read
.eq(1) # yeah don't read it again
304 sync
+= cur_state
.msr
.eq(self
.state_r_msr
.data_o
)
306 sync
+= sv_read
.eq(1) # yeah don't read it again
307 sync
+= cur_state
.svstate
.eq(self
.state_r_sv
.data_o
)
308 with m
.If(self
.imem
.f_busy_o
): # zzz...
309 # busy: stay in wait-read
310 comb
+= self
.imem
.a_valid_i
.eq(1)
311 comb
+= self
.imem
.f_valid_i
.eq(1)
313 # not busy: instruction fetched
314 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
315 # decode the SVP64 prefix, if any
316 comb
+= svp64
.raw_opcode_in
.eq(insn
)
317 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
318 # pass the decoded prefix (if any) to PowerDecoder2
319 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
320 # calculate the address of the following instruction
321 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
322 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
323 with m
.If(~svp64
.is_svp64_mode
):
324 # with no prefix, store the instruction
325 # and hand it directly to the next FSM
326 sync
+= fetch_insn_o
.eq(insn
)
327 m
.next
= "INSN_READY"
329 # fetch the rest of the instruction from memory
330 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
331 comb
+= self
.imem
.a_valid_i
.eq(1)
332 comb
+= self
.imem
.f_valid_i
.eq(1)
333 m
.next
= "INSN_READ2"
335 with m
.State("INSN_READ2"):
336 with m
.If(self
.imem
.f_busy_o
): # zzz...
337 # busy: stay in wait-read
338 comb
+= self
.imem
.a_valid_i
.eq(1)
339 comb
+= self
.imem
.f_valid_i
.eq(1)
341 # not busy: instruction fetched
342 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
343 sync
+= fetch_insn_o
.eq(insn
)
344 m
.next
= "INSN_READY"
346 with m
.State("INSN_READY"):
347 # hand over the instruction, to be decoded
348 comb
+= fetch_insn_valid_o
.eq(1)
349 with m
.If(fetch_insn_ready_i
):
352 # decode / issue / execute FSM. this interacts with the "fetch" FSM
353 # through fetch_pc_ready/valid (incoming) and fetch_insn_ready/valid
354 # (outgoing). SVP64 RM prefixes have already been set up by the
355 # "fetch" phase, so execute is fairly straightforward.
359 # go fetch the instruction at the current PC
360 # at this point, there is no instruction running, that
361 # could inadvertently update the PC.
362 with m
.State("INSN_FETCH"):
363 comb
+= fetch_pc_valid_i
.eq(1)
364 with m
.If(fetch_pc_ready_o
):
367 # decode the instruction when it arrives
368 with m
.State("INSN_WAIT"):
369 comb
+= fetch_insn_ready_i
.eq(1)
370 with m
.If(fetch_insn_valid_o
):
371 # decode the instruction
372 # TODO, before issuing new instruction first
373 # check if it's SVP64. (svp64.is_svp64_mode set)
374 # if yes, record the svp64_rm, put that into
375 # pdecode2.sv_rm, then read another 32 bits (INSN_FETCH2?)
376 comb
+= dec_opcode_i
.eq(fetch_insn_o
) # actual opcode
377 sync
+= core
.e
.eq(pdecode2
.e
)
378 sync
+= core
.state
.eq(cur_state
)
379 sync
+= core
.raw_insn_i
.eq(dec_opcode_i
)
380 sync
+= core
.bigendian_i
.eq(self
.core_bigendian_i
)
381 sync
+= ilatch
.eq(insn
) # latch current insn
382 # also drop PC and MSR into decode "state"
383 m
.next
= "INSN_START" # move to "start"
385 # waiting for instruction bus (stays there until not busy)
386 with m
.State("INSN_START"):
387 comb
+= core_ivalid_i
.eq(1) # instruction is valid
388 comb
+= core_issue_i
.eq(1) # and issued
389 sync
+= pc_changed
.eq(0)
391 m
.next
= "INSN_ACTIVE" # move to "wait completion"
393 # instruction started: must wait till it finishes
394 with m
.State("INSN_ACTIVE"):
395 with m
.If(insn_type
!= MicrOp
.OP_NOP
):
396 comb
+= core_ivalid_i
.eq(1) # instruction is valid
397 with m
.If(self
.state_nia
.wen
& (1<<StateRegs
.PC
)):
398 sync
+= pc_changed
.eq(1)
399 with m
.If(~core_busy_o
): # instruction done!
400 # ok here we are not reading the branch unit. TODO
401 # this just blithely overwrites whatever pipeline
403 with m
.If(~pc_changed
):
404 comb
+= self
.state_w_pc
.wen
.eq(1<<StateRegs
.PC
)
405 comb
+= self
.state_w_pc
.data_i
.eq(nia
)
407 sync
+= core
.raw_insn_i
.eq(0)
408 sync
+= core
.bigendian_i
.eq(0)
409 m
.next
= "INSN_FETCH" # back to fetch
411 # this bit doesn't have to be in the FSM: connect up to read
412 # regfiles on demand from DMI
413 with m
.If(d_reg
.req
): # request for regfile access being made
414 # TODO: error-check this
415 # XXX should this be combinatorial? sync better?
417 comb
+= self
.int_r
.ren
.eq(1<<d_reg
.addr
)
419 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
420 comb
+= self
.int_r
.ren
.eq(1)
421 d_reg_delay
= Signal()
422 sync
+= d_reg_delay
.eq(d_reg
.req
)
423 with m
.If(d_reg_delay
):
424 # data arrives one clock later
425 comb
+= d_reg
.data
.eq(self
.int_r
.data_o
)
426 comb
+= d_reg
.ack
.eq(1)
428 # sigh same thing for CR debug
429 with m
.If(d_cr
.req
): # request for regfile access being made
430 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
431 d_cr_delay
= Signal()
432 sync
+= d_cr_delay
.eq(d_cr
.req
)
433 with m
.If(d_cr_delay
):
434 # data arrives one clock later
435 comb
+= d_cr
.data
.eq(self
.cr_r
.data_o
)
436 comb
+= d_cr
.ack
.eq(1)
439 with m
.If(d_xer
.req
): # request for regfile access being made
440 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
441 d_xer_delay
= Signal()
442 sync
+= d_xer_delay
.eq(d_xer
.req
)
443 with m
.If(d_xer_delay
):
444 # data arrives one clock later
445 comb
+= d_xer
.data
.eq(self
.xer_r
.data_o
)
446 comb
+= d_xer
.ack
.eq(1)
448 # DEC and TB inc/dec FSM
449 self
.tb_dec_fsm(m
, cur_state
.dec
)
453 def tb_dec_fsm(self
, m
, spr_dec
):
456 this is a FSM for updating either dec or tb. it runs alternately
457 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
458 value to DEC, however the regfile has "passthrough" on it so this
461 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
464 comb
, sync
= m
.d
.comb
, m
.d
.sync
465 fast_rf
= self
.core
.regs
.rf
['fast']
466 fast_r_dectb
= fast_rf
.r_ports
['issue'] # DEC/TB
467 fast_w_dectb
= fast_rf
.w_ports
['issue'] # DEC/TB
471 # initiates read of current DEC
472 with m
.State("DEC_READ"):
473 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.DEC
)
474 comb
+= fast_r_dectb
.ren
.eq(1)
477 # waits for DEC read to arrive (1 cycle), updates with new value
478 with m
.State("DEC_WRITE"):
480 # TODO: MSR.LPCR 32-bit decrement mode
481 comb
+= new_dec
.eq(fast_r_dectb
.data_o
- 1)
482 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.DEC
)
483 comb
+= fast_w_dectb
.wen
.eq(1)
484 comb
+= fast_w_dectb
.data_i
.eq(new_dec
)
485 sync
+= spr_dec
.eq(new_dec
) # copy into cur_state for decoder
488 # initiates read of current TB
489 with m
.State("TB_READ"):
490 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.TB
)
491 comb
+= fast_r_dectb
.ren
.eq(1)
494 # waits for read TB to arrive, initiates write of current TB
495 with m
.State("TB_WRITE"):
497 comb
+= new_tb
.eq(fast_r_dectb
.data_o
+ 1)
498 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.TB
)
499 comb
+= fast_w_dectb
.wen
.eq(1)
500 comb
+= fast_w_dectb
.data_i
.eq(new_tb
)
506 yield from self
.pc_i
.ports()
509 yield from self
.core
.ports()
510 yield from self
.imem
.ports()
511 yield self
.core_bigendian_i
517 def external_ports(self
):
518 ports
= self
.pc_i
.ports()
519 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
523 ports
+= list(self
.jtag
.external_ports())
525 # don't add DMI if JTAG is enabled
526 ports
+= list(self
.dbg
.dmi
.ports())
528 ports
+= list(self
.imem
.ibus
.fields
.values())
529 ports
+= list(self
.core
.l0
.cmpi
.lsmem
.lsi
.slavebus
.fields
.values())
532 ports
+= list(self
.xics_icp
.bus
.fields
.values())
533 ports
+= list(self
.xics_ics
.bus
.fields
.values())
534 ports
.append(self
.int_level_i
)
537 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
538 ports
.append(self
.gpio_o
)
546 class TestIssuer(Elaboratable
):
547 def __init__(self
, pspec
):
548 self
.ti
= TestIssuerInternal(pspec
)
550 self
.pll
= DummyPLL()
552 # PLL direct clock or not
553 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
555 self
.pll_18_o
= Signal(reset_less
=True)
557 def elaborate(self
, platform
):
561 # TestIssuer runs at direct clock
562 m
.submodules
.ti
= ti
= self
.ti
563 cd_int
= ClockDomain("coresync")
566 # ClockSelect runs at PLL output internal clock rate
567 m
.submodules
.pll
= pll
= self
.pll
569 # add clock domains from PLL
570 cd_pll
= ClockDomain("pllclk")
573 # PLL clock established. has the side-effect of running clklsel
574 # at the PLL's speed (see DomainRenamer("pllclk") above)
575 pllclk
= ClockSignal("pllclk")
576 comb
+= pllclk
.eq(pll
.clk_pll_o
)
578 # wire up external 24mhz to PLL
579 comb
+= pll
.clk_24_i
.eq(ClockSignal())
581 # output 18 mhz PLL test signal
582 comb
+= self
.pll_18_o
.eq(pll
.pll_18_o
)
584 # now wire up ResetSignals. don't mind them being in this domain
585 pll_rst
= ResetSignal("pllclk")
586 comb
+= pll_rst
.eq(ResetSignal())
588 # internal clock is set to selector clock-out. has the side-effect of
589 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
590 intclk
= ClockSignal("coresync")
592 comb
+= intclk
.eq(pll
.clk_pll_o
)
594 comb
+= intclk
.eq(ClockSignal())
599 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
600 [ClockSignal(), ResetSignal()]
602 def external_ports(self
):
603 ports
= self
.ti
.external_ports()
604 ports
.append(ClockSignal())
605 ports
.append(ResetSignal())
607 ports
.append(self
.pll
.clk_sel_i
)
608 ports
.append(self
.pll_18_o
)
609 ports
.append(self
.pll
.pll_lck_o
)
613 if __name__
== '__main__':
614 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
620 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
621 imem_ifacetype
='bare_wb',
626 dut
= TestIssuer(pspec
)
627 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
629 if len(sys
.argv
) == 1:
630 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
631 with
open("test_issuer.il", "w") as f
: