3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from soc
.decoder
.power_decoder
import create_pdecode
25 from soc
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
26 from soc
.decoder
.decode2execute1
import IssuerDecode2ToOperand
27 from soc
.decoder
.decode2execute1
import Data
28 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
29 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
30 from soc
.simple
.core
import NonProductionCore
31 from soc
.config
.test
.test_loadstore
import TestMemPspec
32 from soc
.config
.ifetch
import ConfigFetchUnit
33 from soc
.decoder
.power_enums
import MicrOp
34 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
35 from soc
.debug
.jtag
import JTAG
36 from soc
.config
.pinouts
import get_pinspecs
37 from soc
.config
.state
import CoreState
38 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
39 from soc
.bus
.simple_gpio
import SimpleGPIO
40 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
41 from soc
.clock
.select
import ClockSelect
42 from soc
.clock
.dummypll
import DummyPLL
43 from soc
.sv
.svstate
import SVSTATERec
46 from nmutil
.util
import rising_edge
48 def get_insn(f_instr_o
, pc
):
49 if f_instr_o
.width
== 32:
52 # 64-bit: bit 2 of pc decides which word to select
53 return f_instr_o
.word_select(pc
[2], 32)
55 # gets state input or reads from state regfile
56 def state_get(m
, state_i
, name
, regfile
, regnum
):
60 res
= Signal(64, reset_less
=True, name
=name
)
61 res_ok_delay
= Signal(name
="%s_ok_delay" % name
)
62 sync
+= res_ok_delay
.eq(~state_i
.ok
)
63 with m
.If(state_i
.ok
):
64 # incoming override (start from pc_i)
65 comb
+= res
.eq(state_i
.data
)
67 # otherwise read StateRegs regfile for PC...
68 comb
+= regfile
.ren
.eq(1<<regnum
)
69 # ... but on a 1-clock delay
70 with m
.If(res_ok_delay
):
71 comb
+= res
.eq(regfile
.data_o
)
74 def get_predint(m
, mask
):
75 """decode SVP64 predicate integer mask field to reg number and invert
76 this is identical to the equivalent function in ISACaller except that
77 it doesn't read the INT directly, it just decodes "what needs to be done"
78 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
84 with m
.Case(SVP64PredInt
.ALWAYS
.value
):
87 with m
.Case(SVP64PredInt
.R3_UNARY
.value
):
90 with m
.Case(SVP64PredInt
.R3
.value
):
92 with m
.Case(SVP64PredInt
.R3_N
.value
):
95 with m
.Case(SVP64PredInt
.R10
.value
):
96 comb
+= regread
.eq(10)
97 with m
.Case(SVP64PredInt
.R10_N
.value
):
98 comb
+= regread
.eq(10)
100 with m
.Case(SVP64PredInt
.R30
.value
):
101 comb
+= regread
.eq(30)
102 with m
.Case(SVP64PredInt
.R30_N
.value
):
103 comb
+= regread
.eq(30)
105 return regread
, invert
, unary
107 def get_predcr(m
, mask
):
108 """decode SVP64 predicate CR to reg number field and invert status
109 this is identical to _get_predcr in ISACaller
114 with m
.Case(SVP64PredCR
.LT
.value
):
117 with m
.Case(SVP64PredCR
.GE
.value
):
120 with m
.Case(SVP64PredCR
.GT
.value
):
123 with m
.Case(SVP64PredCR
.LE
.value
):
126 with m
.Case(SVP64PredCR
.EQ
.value
):
129 with m
.Case(SVP64PredCR
.NE
.value
):
132 with m
.Case(SVP64PredCR
.SO
.value
):
135 with m
.Case(SVP64PredCR
.NS
.value
):
141 class TestIssuerInternal(Elaboratable
):
142 """TestIssuer - reads instructions from TestMemory and issues them
144 efficiency and speed is not the main goal here: functional correctness is.
146 def __init__(self
, pspec
):
148 # test is SVP64 is to be enabled
149 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
151 # JTAG interface. add this right at the start because if it's
152 # added it *modifies* the pspec, by adding enable/disable signals
153 # for parts of the rest of the core
154 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
156 subset
= {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
158 self
.jtag
= JTAG(get_pinspecs(subset
=subset
))
159 # add signals to pspec to enable/disable icache and dcache
160 # (or data and intstruction wishbone if icache/dcache not included)
161 # https://bugs.libre-soc.org/show_bug.cgi?id=520
162 # TODO: do we actually care if these are not domain-synchronised?
163 # honestly probably not.
164 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
165 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
166 self
.wb_sram_en
= self
.jtag
.wb_sram_en
168 self
.wb_sram_en
= Const(1)
170 # add 4k sram blocks?
171 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
172 pspec
.sram4x4kblock
== True)
176 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
,
179 # add interrupt controller?
180 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
182 self
.xics_icp
= XICS_ICP()
183 self
.xics_ics
= XICS_ICS()
184 self
.int_level_i
= self
.xics_ics
.int_level_i
186 # add GPIO peripheral?
187 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
189 self
.simple_gpio
= SimpleGPIO()
190 self
.gpio_o
= self
.simple_gpio
.gpio_o
192 # main instruction core. suitable for prototyping / demo only
193 self
.core
= core
= NonProductionCore(pspec
)
195 # instruction decoder. goes into Trap Record
196 pdecode
= create_pdecode()
197 self
.cur_state
= CoreState("cur") # current state (MSR/PC/SVSTATE)
198 self
.pdecode2
= PowerDecode2(pdecode
, state
=self
.cur_state
,
199 opkls
=IssuerDecode2ToOperand
,
200 svp64_en
=self
.svp64_en
)
202 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
204 # Test Instruction memory
205 self
.imem
= ConfigFetchUnit(pspec
).fu
208 self
.dbg
= CoreDebug()
210 # instruction go/monitor
211 self
.pc_o
= Signal(64, reset_less
=True)
212 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
213 self
.svstate_i
= Data(32, "svstate_i") # ditto
214 self
.core_bigendian_i
= Signal() # TODO: set based on MSR.LE
215 self
.busy_o
= Signal(reset_less
=True)
216 self
.memerr_o
= Signal(reset_less
=True)
218 # STATE regfile read /write ports for PC, MSR, SVSTATE
219 staterf
= self
.core
.regs
.rf
['state']
220 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
221 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
222 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
223 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
224 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
226 # DMI interface access
227 intrf
= self
.core
.regs
.rf
['int']
228 crrf
= self
.core
.regs
.rf
['cr']
229 xerrf
= self
.core
.regs
.rf
['xer']
230 self
.int_r
= intrf
.r_ports
['dmi'] # INT read
231 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR read
232 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER read
235 self
.int_pred
= intrf
.r_ports
['pred'] # INT predicate read
236 self
.cr_pred
= crrf
.r_ports
['cr_pred'] # CR predicate read
238 # hack method of keeping an eye on whether branch/trap set the PC
239 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
240 self
.state_nia
.wen
.name
= 'state_nia_wen'
242 # pulse to synchronize the simulator at instruction end
243 self
.insn_done
= Signal()
246 # store copies of predicate masks
247 self
.srcmask
= Signal(64)
248 self
.dstmask
= Signal(64)
250 def fetch_fsm(self
, m
, core
, pc
, svstate
, nia
, is_svp64_mode
,
251 fetch_pc_ready_o
, fetch_pc_valid_i
,
252 fetch_insn_valid_o
, fetch_insn_ready_i
):
254 this FSM performs fetch of raw instruction data, partial-decodes
255 it 32-bit at a time to detect SVP64 prefixes, and will optionally
256 read a 2nd 32-bit quantity if that occurs.
260 pdecode2
= self
.pdecode2
261 cur_state
= self
.cur_state
262 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
264 msr_read
= Signal(reset
=1)
266 with m
.FSM(name
='fetch_fsm'):
269 with m
.State("IDLE"):
270 comb
+= fetch_pc_ready_o
.eq(1)
271 with m
.If(fetch_pc_valid_i
):
272 # instruction allowed to go: start by reading the PC
273 # capture the PC and also drop it into Insn Memory
274 # we have joined a pair of combinatorial memory
275 # lookups together. this is Generally Bad.
276 comb
+= self
.imem
.a_pc_i
.eq(pc
)
277 comb
+= self
.imem
.a_valid_i
.eq(1)
278 comb
+= self
.imem
.f_valid_i
.eq(1)
279 sync
+= cur_state
.pc
.eq(pc
)
280 sync
+= cur_state
.svstate
.eq(svstate
) # and svstate
282 # initiate read of MSR. arrives one clock later
283 comb
+= self
.state_r_msr
.ren
.eq(1 << StateRegs
.MSR
)
284 sync
+= msr_read
.eq(0)
286 m
.next
= "INSN_READ" # move to "wait for bus" phase
288 # dummy pause to find out why simulation is not keeping up
289 with m
.State("INSN_READ"):
290 # one cycle later, msr/sv read arrives. valid only once.
291 with m
.If(~msr_read
):
292 sync
+= msr_read
.eq(1) # yeah don't read it again
293 sync
+= cur_state
.msr
.eq(self
.state_r_msr
.data_o
)
294 with m
.If(self
.imem
.f_busy_o
): # zzz...
295 # busy: stay in wait-read
296 comb
+= self
.imem
.a_valid_i
.eq(1)
297 comb
+= self
.imem
.f_valid_i
.eq(1)
299 # not busy: instruction fetched
300 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
303 # decode the SVP64 prefix, if any
304 comb
+= svp64
.raw_opcode_in
.eq(insn
)
305 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
306 # pass the decoded prefix (if any) to PowerDecoder2
307 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
308 # remember whether this is a prefixed instruction, so
309 # the FSM can readily loop when VL==0
310 sync
+= is_svp64_mode
.eq(svp64
.is_svp64_mode
)
311 # calculate the address of the following instruction
312 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
313 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
314 with m
.If(~svp64
.is_svp64_mode
):
315 # with no prefix, store the instruction
316 # and hand it directly to the next FSM
317 sync
+= dec_opcode_i
.eq(insn
)
318 m
.next
= "INSN_READY"
320 # fetch the rest of the instruction from memory
321 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
322 comb
+= self
.imem
.a_valid_i
.eq(1)
323 comb
+= self
.imem
.f_valid_i
.eq(1)
324 m
.next
= "INSN_READ2"
326 # not SVP64 - 32-bit only
327 sync
+= nia
.eq(cur_state
.pc
+ 4)
328 sync
+= dec_opcode_i
.eq(insn
)
329 m
.next
= "INSN_READY"
331 with m
.State("INSN_READ2"):
332 with m
.If(self
.imem
.f_busy_o
): # zzz...
333 # busy: stay in wait-read
334 comb
+= self
.imem
.a_valid_i
.eq(1)
335 comb
+= self
.imem
.f_valid_i
.eq(1)
337 # not busy: instruction fetched
338 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
339 sync
+= dec_opcode_i
.eq(insn
)
340 m
.next
= "INSN_READY"
341 # TODO: probably can start looking at pdecode2.rm_dec
342 # here (or maybe even in INSN_READ state, if svp64_mode
343 # detected, in order to trigger - and wait for - the
345 pmode
= pdecode2
.rm_dec
.predmode
347 if pmode != SVP64PredMode.ALWAYS.value:
348 fire predicate loading FSM and wait before
351 sync += self.srcmask.eq(-1) # set to all 1s
352 sync += self.dstmask.eq(-1) # set to all 1s
353 m.next = "INSN_READY"
356 with m
.State("INSN_READY"):
357 # hand over the instruction, to be decoded
358 comb
+= fetch_insn_valid_o
.eq(1)
359 with m
.If(fetch_insn_ready_i
):
362 def fetch_predicate_fsm(self
, m
, core
, TODO
):
363 """fetch_predicate_fsm - obtains (constructs in the case of CR)
364 src/dest predicate masks
366 https://bugs.libre-soc.org/show_bug.cgi?id=617
367 the predicates can be read here, by using IntRegs r_ports['pred']
368 or CRRegs r_ports['pred']. in the case of CRs it will have to
369 be done through multiple reads, extracting one relevant at a time.
370 later, a faster way would be to use the 32-bit-wide CR port but
371 this is more complex decoding, here. equivalent code used in
372 ISACaller is "from soc.decoder.isa.caller import get_predcr"
376 pdecode2
= self
.pdecode2
377 rm_dec
= pdecode2
.rm_dec
# SVP64RMModeDecode
378 predmode
= rm_dec
.predmode
379 srcpred
, dstpred
= rm_dec
.srcpred
, rm_dec
.dstpred
380 cr_pred
, int_pred
= self
.cr_pred
, self
.int_pred
# read regfiles
381 # if predmode == INT:
382 # INT-src sregread, sinvert, sunary = get_predint(m, srcpred)
383 # INT-dst dregread, dinvert, dunary = get_predint(m, dstpred)
384 # TODO read INT-src and INT-dst into self.srcmask+dstmask
385 # elif predmode == CR:
386 # CR-src sidx, sinvert = get_predcr(m, srcpred)
387 # CR-dst didx, dinvert = get_predcr(m, dstpred)
388 # TODO read CR-src and CR-dst into self.srcmask+dstmask with loop
390 # sync += self.srcmask.eq(-1) # set to all 1s
391 # sync += self.dstmask.eq(-1) # set to all 1s
393 def issue_fsm(self
, m
, core
, pc_changed
, sv_changed
, nia
,
394 dbg
, core_rst
, is_svp64_mode
,
395 fetch_pc_ready_o
, fetch_pc_valid_i
,
396 fetch_insn_valid_o
, fetch_insn_ready_i
,
397 exec_insn_valid_i
, exec_insn_ready_o
,
398 exec_pc_valid_o
, exec_pc_ready_i
):
401 decode / issue FSM. this interacts with the "fetch" FSM
402 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
403 (outgoing). also interacts with the "execute" FSM
404 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
406 SVP64 RM prefixes have already been set up by the
407 "fetch" phase, so execute is fairly straightforward.
412 pdecode2
= self
.pdecode2
413 cur_state
= self
.cur_state
416 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
418 # for updating svstate (things like srcstep etc.)
419 update_svstate
= Signal() # set this (below) if updating
420 new_svstate
= SVSTATERec("new_svstate")
421 comb
+= new_svstate
.eq(cur_state
.svstate
)
423 # precalculate srcstep+1 and dststep+1
424 cur_srcstep
= cur_state
.svstate
.srcstep
425 cur_dststep
= cur_state
.svstate
.dststep
426 next_srcstep
= Signal
.like(cur_srcstep
)
427 next_dststep
= Signal
.like(cur_dststep
)
428 comb
+= next_srcstep
.eq(cur_state
.svstate
.srcstep
+1)
429 comb
+= next_dststep
.eq(cur_state
.svstate
.dststep
+1)
431 with m
.FSM(name
="issue_fsm"):
433 # sync with the "fetch" phase which is reading the instruction
434 # at this point, there is no instruction running, that
435 # could inadvertently update the PC.
436 with m
.State("ISSUE_START"):
437 # wait on "core stop" release, before next fetch
438 # need to do this here, in case we are in a VL==0 loop
439 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
440 comb
+= fetch_pc_valid_i
.eq(1) # tell fetch to start
441 with m
.If(fetch_pc_ready_o
): # fetch acknowledged us
444 # tell core it's stopped, and acknowledge debug handshake
445 comb
+= core
.core_stopped_i
.eq(1)
446 comb
+= dbg
.core_stopped_i
.eq(1)
447 # while stopped, allow updating the PC and SVSTATE
448 with m
.If(self
.pc_i
.ok
):
449 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
450 comb
+= self
.state_w_pc
.data_i
.eq(self
.pc_i
.data
)
451 sync
+= pc_changed
.eq(1)
452 with m
.If(self
.svstate_i
.ok
):
453 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
454 comb
+= update_svstate
.eq(1)
455 sync
+= sv_changed
.eq(1)
457 # decode the instruction when it arrives
458 with m
.State("INSN_WAIT"):
459 comb
+= fetch_insn_ready_i
.eq(1)
460 with m
.If(fetch_insn_valid_o
):
461 # decode the instruction
462 sync
+= core
.e
.eq(pdecode2
.e
)
463 sync
+= core
.state
.eq(cur_state
)
464 sync
+= core
.raw_insn_i
.eq(dec_opcode_i
)
465 sync
+= core
.bigendian_i
.eq(self
.core_bigendian_i
)
466 # set RA_OR_ZERO detection in satellite decoders
467 sync
+= core
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
468 # loop into ISSUE_START if it's a SVP64 instruction
469 # and VL == 0. this because VL==0 is a for-loop
470 # from 0 to 0 i.e. always, always a NOP.
471 cur_vl
= cur_state
.svstate
.vl
472 with m
.If(is_svp64_mode
& (cur_vl
== 0)):
473 # update the PC before fetching the next instruction
474 # since we are in a VL==0 loop, no instruction was
475 # executed that we could be overwriting
476 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
477 comb
+= self
.state_w_pc
.data_i
.eq(nia
)
478 comb
+= self
.insn_done
.eq(1)
479 m
.next
= "ISSUE_START"
481 m
.next
= "INSN_EXECUTE" # move to "execute"
483 # handshake with execution FSM, move to "wait" once acknowledged
484 with m
.State("INSN_EXECUTE"):
485 # with m.If(is_svp64_mode):
486 # TODO advance src/dst step to "skip" over predicated-out
487 # from self.srcmask and self.dstmask
488 # https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
489 # but still without exceeding VL in either case
490 # IMPORTANT: when changing src/dest step, have to
491 # jump to m.next = "DECODE_SV" to deal with the change in
494 with m
.If(is_svp64_mode
):
496 pred_src_zero
= pdecode2
.rm_dec
.pred_sz
497 pred_dst_zero
= pdecode2
.rm_dec
.pred_dz
500 if not pred_src_zero:
501 if (((1<<cur_srcstep) & self.srcmask) == 0) and
503 comb += update_svstate.eq(1)
504 comb += new_svstate.srcstep.eq(next_srcstep)
505 sync += sv_changed.eq(1)
507 if not pred_dst_zero:
508 if (((1<<cur_dststep) & self.dstmask) == 0) and
510 comb += new_svstate.dststep.eq(next_dststep)
511 comb += update_svstate.eq(1)
512 sync += sv_changed.eq(1)
518 comb
+= exec_insn_valid_i
.eq(1) # trigger execute
519 with m
.If(exec_insn_ready_o
): # execute acknowledged us
520 m
.next
= "EXECUTE_WAIT"
522 with m
.State("EXECUTE_WAIT"):
523 # wait on "core stop" release, at instruction end
524 # need to do this here, in case we are in a VL>1 loop
525 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
526 comb
+= exec_pc_ready_i
.eq(1)
527 with m
.If(exec_pc_valid_o
):
529 # was this the last loop iteration?
531 cur_vl
= cur_state
.svstate
.vl
532 comb
+= is_last
.eq(next_srcstep
== cur_vl
)
534 # if either PC or SVSTATE were changed by the previous
535 # instruction, go directly back to Fetch, without
536 # updating either PC or SVSTATE
537 with m
.If(pc_changed | sv_changed
):
538 m
.next
= "ISSUE_START"
540 # also return to Fetch, when no output was a vector
541 # (regardless of SRCSTEP and VL), or when the last
542 # instruction was really the last one of the VL loop
543 with m
.Elif((~pdecode2
.loop_continue
) | is_last
):
544 # before going back to fetch, update the PC state
545 # register with the NIA.
546 # ok here we are not reading the branch unit.
547 # TODO: this just blithely overwrites whatever
548 # pipeline updated the PC
549 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
550 comb
+= self
.state_w_pc
.data_i
.eq(nia
)
551 # reset SRCSTEP before returning to Fetch
552 with m
.If(pdecode2
.loop_continue
):
553 comb
+= new_svstate
.srcstep
.eq(0)
554 comb
+= new_svstate
.dststep
.eq(0)
555 comb
+= update_svstate
.eq(1)
556 m
.next
= "ISSUE_START"
558 # returning to Execute? then, first update SRCSTEP
560 comb
+= new_svstate
.srcstep
.eq(next_srcstep
)
561 comb
+= new_svstate
.dststep
.eq(next_dststep
)
562 comb
+= update_svstate
.eq(1)
566 comb
+= core
.core_stopped_i
.eq(1)
567 comb
+= dbg
.core_stopped_i
.eq(1)
568 # while stopped, allow updating the PC and SVSTATE
569 with m
.If(self
.pc_i
.ok
):
570 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
571 comb
+= self
.state_w_pc
.data_i
.eq(self
.pc_i
.data
)
572 sync
+= pc_changed
.eq(1)
573 with m
.If(self
.svstate_i
.ok
):
574 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
575 comb
+= update_svstate
.eq(1)
576 sync
+= sv_changed
.eq(1)
578 # need to decode the instruction again, after updating SRCSTEP
579 # in the previous state.
580 # mostly a copy of INSN_WAIT, but without the actual wait
581 with m
.State("DECODE_SV"):
582 # decode the instruction
583 sync
+= core
.e
.eq(pdecode2
.e
)
584 sync
+= core
.state
.eq(cur_state
)
585 sync
+= core
.bigendian_i
.eq(self
.core_bigendian_i
)
586 sync
+= core
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
587 m
.next
= "INSN_EXECUTE" # move to "execute"
589 # check if svstate needs updating: if so, write it to State Regfile
590 with m
.If(update_svstate
):
591 comb
+= self
.state_w_sv
.wen
.eq(1<<StateRegs
.SVSTATE
)
592 comb
+= self
.state_w_sv
.data_i
.eq(new_svstate
)
593 sync
+= cur_state
.svstate
.eq(new_svstate
) # for next clock
595 def execute_fsm(self
, m
, core
, pc_changed
, sv_changed
,
596 exec_insn_valid_i
, exec_insn_ready_o
,
597 exec_pc_valid_o
, exec_pc_ready_i
):
600 execute FSM. this interacts with the "issue" FSM
601 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
602 (outgoing). SVP64 RM prefixes have already been set up by the
603 "issue" phase, so execute is fairly straightforward.
608 pdecode2
= self
.pdecode2
611 core_busy_o
= core
.busy_o
# core is busy
612 core_ivalid_i
= core
.ivalid_i
# instruction is valid
613 core_issue_i
= core
.issue_i
# instruction is issued
614 insn_type
= core
.e
.do
.insn_type
# instruction MicroOp type
616 with m
.FSM(name
="exec_fsm"):
618 # waiting for instruction bus (stays there until not busy)
619 with m
.State("INSN_START"):
620 comb
+= exec_insn_ready_o
.eq(1)
621 with m
.If(exec_insn_valid_i
):
622 comb
+= core_ivalid_i
.eq(1) # instruction is valid
623 comb
+= core_issue_i
.eq(1) # and issued
624 sync
+= sv_changed
.eq(0)
625 sync
+= pc_changed
.eq(0)
626 m
.next
= "INSN_ACTIVE" # move to "wait completion"
628 # instruction started: must wait till it finishes
629 with m
.State("INSN_ACTIVE"):
630 with m
.If(insn_type
!= MicrOp
.OP_NOP
):
631 comb
+= core_ivalid_i
.eq(1) # instruction is valid
632 # note changes to PC and SVSTATE
633 with m
.If(self
.state_nia
.wen
& (1<<StateRegs
.SVSTATE
)):
634 sync
+= sv_changed
.eq(1)
635 with m
.If(self
.state_nia
.wen
& (1<<StateRegs
.PC
)):
636 sync
+= pc_changed
.eq(1)
637 with m
.If(~core_busy_o
): # instruction done!
638 comb
+= exec_pc_valid_o
.eq(1)
639 with m
.If(exec_pc_ready_i
):
640 comb
+= self
.insn_done
.eq(1)
641 m
.next
= "INSN_START" # back to fetch
643 def setup_peripherals(self
, m
):
644 comb
, sync
= m
.d
.comb
, m
.d
.sync
646 m
.submodules
.core
= core
= DomainRenamer("coresync")(self
.core
)
647 m
.submodules
.imem
= imem
= self
.imem
648 m
.submodules
.dbg
= dbg
= self
.dbg
650 m
.submodules
.jtag
= jtag
= self
.jtag
651 # TODO: UART2GDB mux, here, from external pin
652 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
653 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
655 cur_state
= self
.cur_state
657 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
659 for i
, sram
in enumerate(self
.sram4k
):
660 m
.submodules
["sram4k_%d" % i
] = sram
661 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
663 # XICS interrupt handler
665 m
.submodules
.xics_icp
= icp
= self
.xics_icp
666 m
.submodules
.xics_ics
= ics
= self
.xics_ics
667 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
668 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
670 # GPIO test peripheral
672 m
.submodules
.simple_gpio
= simple_gpio
= self
.simple_gpio
674 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
675 # XXX causes litex ECP5 test to get wrong idea about input and output
676 # (but works with verilator sim *sigh*)
677 #if self.gpio and self.xics:
678 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
680 # instruction decoder
681 pdecode
= create_pdecode()
682 m
.submodules
.dec2
= pdecode2
= self
.pdecode2
684 m
.submodules
.svp64
= svp64
= self
.svp64
687 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
688 intrf
= self
.core
.regs
.rf
['int']
690 # clock delay power-on reset
691 cd_por
= ClockDomain(reset_less
=True)
692 cd_sync
= ClockDomain()
693 core_sync
= ClockDomain("coresync")
694 m
.domains
+= cd_por
, cd_sync
, core_sync
696 ti_rst
= Signal(reset_less
=True)
697 delay
= Signal(range(4), reset
=3)
698 with m
.If(delay
!= 0):
699 m
.d
.por
+= delay
.eq(delay
- 1)
700 comb
+= cd_por
.clk
.eq(ClockSignal())
702 # power-on reset delay
703 core_rst
= ResetSignal("coresync")
704 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
705 comb
+= core_rst
.eq(ti_rst
)
707 # busy/halted signals from core
708 comb
+= self
.busy_o
.eq(core
.busy_o
)
709 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
711 # temporary hack: says "go" immediately for both address gen and ST
713 ldst
= core
.fus
.fus
['ldst0']
714 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
715 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
) # link addr-go direct to rel
716 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
720 def elaborate(self
, platform
):
723 comb
, sync
= m
.d
.comb
, m
.d
.sync
724 cur_state
= self
.cur_state
725 pdecode2
= self
.pdecode2
729 # set up peripherals and core
730 core_rst
= self
.setup_peripherals(m
)
732 # PC and instruction from I-Memory
733 comb
+= self
.pc_o
.eq(cur_state
.pc
)
734 pc_changed
= Signal() # note write to PC
735 sv_changed
= Signal() # note write to SVSTATE
737 # read state either from incoming override or from regfile
738 # TODO: really should be doing MSR in the same way
739 pc
= state_get(m
, self
.pc_i
, "pc", # read PC
740 self
.state_r_pc
, StateRegs
.PC
)
741 svstate
= state_get(m
, self
.svstate_i
, "svstate", # read SVSTATE
742 self
.state_r_sv
, StateRegs
.SVSTATE
)
744 # don't write pc every cycle
745 comb
+= self
.state_w_pc
.wen
.eq(0)
746 comb
+= self
.state_w_pc
.data_i
.eq(0)
748 # don't read msr every cycle
749 comb
+= self
.state_r_msr
.ren
.eq(0)
751 # address of the next instruction, in the absence of a branch
752 # depends on the instruction size
753 nia
= Signal(64, reset_less
=True)
755 # connect up debug signals
756 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
757 comb
+= dbg
.terminate_i
.eq(core
.core_terminate_o
)
758 comb
+= dbg
.state
.pc
.eq(pc
)
759 comb
+= dbg
.state
.svstate
.eq(svstate
)
760 comb
+= dbg
.state
.msr
.eq(cur_state
.msr
)
762 # pass the prefix mode from Fetch to Issue, so the latter can loop
764 is_svp64_mode
= Signal()
766 # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
767 # these are the handshake signals between fetch and decode/execute
769 # fetch FSM can run as soon as the PC is valid
770 fetch_pc_valid_i
= Signal() # Execute tells Fetch "start next read"
771 fetch_pc_ready_o
= Signal() # Fetch Tells SVSTATE "proceed"
773 # fetch FSM hands over the instruction to be decoded / issued
774 fetch_insn_valid_o
= Signal()
775 fetch_insn_ready_i
= Signal()
777 # issue FSM delivers the instruction to the be executed
778 exec_insn_valid_i
= Signal()
779 exec_insn_ready_o
= Signal()
781 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
782 exec_pc_valid_o
= Signal()
783 exec_pc_ready_i
= Signal()
785 # the FSMs here are perhaps unusual in that they detect conditions
786 # then "hold" information, combinatorially, for the core
787 # (as opposed to using sync - which would be on a clock's delay)
788 # this includes the actual opcode, valid flags and so on.
790 # Fetch, then Issue, then Execute. Issue is where the VL for-loop
791 # lives. the ready/valid signalling is used to communicate between
794 self
.fetch_fsm(m
, core
, pc
, svstate
, nia
, is_svp64_mode
,
795 fetch_pc_ready_o
, fetch_pc_valid_i
,
796 fetch_insn_valid_o
, fetch_insn_ready_i
)
798 self
.issue_fsm(m
, core
, pc_changed
, sv_changed
, nia
,
799 dbg
, core_rst
, is_svp64_mode
,
800 fetch_pc_ready_o
, fetch_pc_valid_i
,
801 fetch_insn_valid_o
, fetch_insn_ready_i
,
802 exec_insn_valid_i
, exec_insn_ready_o
,
803 exec_pc_valid_o
, exec_pc_ready_i
)
805 self
.execute_fsm(m
, core
, pc_changed
, sv_changed
,
806 exec_insn_valid_i
, exec_insn_ready_o
,
807 exec_pc_valid_o
, exec_pc_ready_i
)
809 # this bit doesn't have to be in the FSM: connect up to read
810 # regfiles on demand from DMI
813 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
814 # (which uses that in PowerDecoder2 to raise 0x900 exception)
815 self
.tb_dec_fsm(m
, cur_state
.dec
)
819 def do_dmi(self
, m
, dbg
):
822 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
823 intrf
= self
.core
.regs
.rf
['int']
825 with m
.If(d_reg
.req
): # request for regfile access being made
826 # TODO: error-check this
827 # XXX should this be combinatorial? sync better?
829 comb
+= self
.int_r
.ren
.eq(1<<d_reg
.addr
)
831 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
832 comb
+= self
.int_r
.ren
.eq(1)
833 d_reg_delay
= Signal()
834 sync
+= d_reg_delay
.eq(d_reg
.req
)
835 with m
.If(d_reg_delay
):
836 # data arrives one clock later
837 comb
+= d_reg
.data
.eq(self
.int_r
.data_o
)
838 comb
+= d_reg
.ack
.eq(1)
840 # sigh same thing for CR debug
841 with m
.If(d_cr
.req
): # request for regfile access being made
842 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
843 d_cr_delay
= Signal()
844 sync
+= d_cr_delay
.eq(d_cr
.req
)
845 with m
.If(d_cr_delay
):
846 # data arrives one clock later
847 comb
+= d_cr
.data
.eq(self
.cr_r
.data_o
)
848 comb
+= d_cr
.ack
.eq(1)
851 with m
.If(d_xer
.req
): # request for regfile access being made
852 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
853 d_xer_delay
= Signal()
854 sync
+= d_xer_delay
.eq(d_xer
.req
)
855 with m
.If(d_xer_delay
):
856 # data arrives one clock later
857 comb
+= d_xer
.data
.eq(self
.xer_r
.data_o
)
858 comb
+= d_xer
.ack
.eq(1)
860 def tb_dec_fsm(self
, m
, spr_dec
):
863 this is a FSM for updating either dec or tb. it runs alternately
864 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
865 value to DEC, however the regfile has "passthrough" on it so this
868 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
871 comb
, sync
= m
.d
.comb
, m
.d
.sync
872 fast_rf
= self
.core
.regs
.rf
['fast']
873 fast_r_dectb
= fast_rf
.r_ports
['issue'] # DEC/TB
874 fast_w_dectb
= fast_rf
.w_ports
['issue'] # DEC/TB
878 # initiates read of current DEC
879 with m
.State("DEC_READ"):
880 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.DEC
)
881 comb
+= fast_r_dectb
.ren
.eq(1)
884 # waits for DEC read to arrive (1 cycle), updates with new value
885 with m
.State("DEC_WRITE"):
887 # TODO: MSR.LPCR 32-bit decrement mode
888 comb
+= new_dec
.eq(fast_r_dectb
.data_o
- 1)
889 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.DEC
)
890 comb
+= fast_w_dectb
.wen
.eq(1)
891 comb
+= fast_w_dectb
.data_i
.eq(new_dec
)
892 sync
+= spr_dec
.eq(new_dec
) # copy into cur_state for decoder
895 # initiates read of current TB
896 with m
.State("TB_READ"):
897 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.TB
)
898 comb
+= fast_r_dectb
.ren
.eq(1)
901 # waits for read TB to arrive, initiates write of current TB
902 with m
.State("TB_WRITE"):
904 comb
+= new_tb
.eq(fast_r_dectb
.data_o
+ 1)
905 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.TB
)
906 comb
+= fast_w_dectb
.wen
.eq(1)
907 comb
+= fast_w_dectb
.data_i
.eq(new_tb
)
913 yield from self
.pc_i
.ports()
916 yield from self
.core
.ports()
917 yield from self
.imem
.ports()
918 yield self
.core_bigendian_i
924 def external_ports(self
):
925 ports
= self
.pc_i
.ports()
926 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
930 ports
+= list(self
.jtag
.external_ports())
932 # don't add DMI if JTAG is enabled
933 ports
+= list(self
.dbg
.dmi
.ports())
935 ports
+= list(self
.imem
.ibus
.fields
.values())
936 ports
+= list(self
.core
.l0
.cmpi
.lsmem
.lsi
.slavebus
.fields
.values())
939 for sram
in self
.sram4k
:
940 ports
+= list(sram
.bus
.fields
.values())
943 ports
+= list(self
.xics_icp
.bus
.fields
.values())
944 ports
+= list(self
.xics_ics
.bus
.fields
.values())
945 ports
.append(self
.int_level_i
)
948 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
949 ports
.append(self
.gpio_o
)
957 class TestIssuer(Elaboratable
):
958 def __init__(self
, pspec
):
959 self
.ti
= TestIssuerInternal(pspec
)
961 self
.pll
= DummyPLL()
963 # PLL direct clock or not
964 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
966 self
.pll_18_o
= Signal(reset_less
=True)
968 def elaborate(self
, platform
):
972 # TestIssuer runs at direct clock
973 m
.submodules
.ti
= ti
= self
.ti
974 cd_int
= ClockDomain("coresync")
977 # ClockSelect runs at PLL output internal clock rate
978 m
.submodules
.pll
= pll
= self
.pll
980 # add clock domains from PLL
981 cd_pll
= ClockDomain("pllclk")
984 # PLL clock established. has the side-effect of running clklsel
985 # at the PLL's speed (see DomainRenamer("pllclk") above)
986 pllclk
= ClockSignal("pllclk")
987 comb
+= pllclk
.eq(pll
.clk_pll_o
)
989 # wire up external 24mhz to PLL
990 comb
+= pll
.clk_24_i
.eq(ClockSignal())
992 # output 18 mhz PLL test signal
993 comb
+= self
.pll_18_o
.eq(pll
.pll_18_o
)
995 # now wire up ResetSignals. don't mind them being in this domain
996 pll_rst
= ResetSignal("pllclk")
997 comb
+= pll_rst
.eq(ResetSignal())
999 # internal clock is set to selector clock-out. has the side-effect of
1000 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1001 intclk
= ClockSignal("coresync")
1003 comb
+= intclk
.eq(pll
.clk_pll_o
)
1005 comb
+= intclk
.eq(ClockSignal())
1010 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
1011 [ClockSignal(), ResetSignal()]
1013 def external_ports(self
):
1014 ports
= self
.ti
.external_ports()
1015 ports
.append(ClockSignal())
1016 ports
.append(ResetSignal())
1018 ports
.append(self
.pll
.clk_sel_i
)
1019 ports
.append(self
.pll_18_o
)
1020 ports
.append(self
.pll
.pll_lck_o
)
1024 if __name__
== '__main__':
1025 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1031 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
1032 imem_ifacetype
='bare_wb',
1037 dut
= TestIssuer(pspec
)
1038 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
1040 if len(sys
.argv
) == 1:
1041 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
1042 with
open("test_issuer.il", "w") as f
: