src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.clock.select import ClockSelect
  41 from soc.clock.dummypll import DummyPLL
  42
  43
  44 from nmutil.util import rising_edge
  45
  46 def get_insn(f_instr_o, pc):
  47     if f_instr_o.width == 32:
  48         return f_instr_o
  49     else:
  50         # 64-bit: bit 2 of pc decides which word to select
  51         return f_instr_o.word_select(pc[2], 32)
  52
  53
  54 class TestIssuerInternal(Elaboratable):
  55     """TestIssuer - reads instructions from TestMemory and issues them
  56
  57     efficiency and speed is not the main goal here: functional correctness is.
  58     """
  59     def __init__(self, pspec):
  60
  61         # JTAG interface.  add this right at the start because if it's
  62         # added it *modifies* the pspec, by adding enable/disable signals
  63         # for parts of the rest of the core
  64         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  65         if self.jtag_en:
  66             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  67                       'pwm', 'sd0', 'sdr'}
  68             self.jtag = JTAG(get_pinspecs(subset=subset))
  69             # add signals to pspec to enable/disable icache and dcache
  70             # (or data and intstruction wishbone if icache/dcache not included)
  71             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  72             # TODO: do we actually care if these are not domain-synchronised?
  73             # honestly probably not.
  74             pspec.wb_icache_en = self.jtag.wb_icache_en
  75             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  76
  77         # add interrupt controller?
  78         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  79         if self.xics:
  80             self.xics_icp = XICS_ICP()
  81             self.xics_ics = XICS_ICS()
  82             self.int_level_i = self.xics_ics.int_level_i
  83
  84         # add GPIO peripheral?
  85         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
  86         if self.gpio:
  87             self.simple_gpio = SimpleGPIO()
  88             self.gpio_o = self.simple_gpio.gpio_o
  89
  90         # main instruction core25
  91         self.core = core = NonProductionCore(pspec)
  92
  93         # instruction decoder.  goes into Trap Record
  94         pdecode = create_pdecode()
  95         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
  96         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
  97                                      opkls=IssuerDecode2ToOperand)
  98         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
  99
 100         # Test Instruction memory
 101         self.imem = ConfigFetchUnit(pspec).fu
 102         # one-row cache of instruction read
 103         self.iline = Signal(64) # one instruction line
 104         self.iprev_adr = Signal(64) # previous address: if different, do read
 105
 106         # DMI interface
 107         self.dbg = CoreDebug()
 108
 109         # instruction go/monitor
 110         self.pc_o = Signal(64, reset_less=True)
 111         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 112         self.core_bigendian_i = Signal()
 113         self.busy_o = Signal(reset_less=True)
 114         self.memerr_o = Signal(reset_less=True)
 115
 116         # STATE regfile read /write ports for PC, MSR, SVSTATE
 117         staterf = self.core.regs.rf['state']
 118         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 119         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 120         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 121         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 122         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 123
 124         # DMI interface access
 125         intrf = self.core.regs.rf['int']
 126         crrf = self.core.regs.rf['cr']
 127         xerrf = self.core.regs.rf['xer']
 128         self.int_r = intrf.r_ports['dmi'] # INT read
 129         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 130         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 131
 132         # hack method of keeping an eye on whether branch/trap set the PC
 133         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 134         self.state_nia.wen.name = 'state_nia_wen'
 135
 136     def elaborate(self, platform):
 137         m = Module()
 138         comb, sync = m.d.comb, m.d.sync
 139
 140         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 141         m.submodules.imem = imem = self.imem
 142         m.submodules.dbg = dbg = self.dbg
 143         if self.jtag_en:
 144             m.submodules.jtag = jtag = self.jtag
 145             # TODO: UART2GDB mux, here, from external pin
 146             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 147             sync += dbg.dmi.connect_to(jtag.dmi)
 148
 149         cur_state = self.cur_state
 150
 151         # XICS interrupt handler
 152         if self.xics:
 153             m.submodules.xics_icp = icp = self.xics_icp
 154             m.submodules.xics_ics = ics = self.xics_ics
 155             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 156             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 157
 158         # GPIO test peripheral
 159         if self.gpio:
 160             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 161
 162         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 163         # XXX causes litex ECP5 test to get wrong idea about input and output
 164         # (but works with verilator sim *sigh*)
 165         #if self.gpio and self.xics:
 166         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 167
 168         # instruction decoder
 169         pdecode = create_pdecode()
 170         m.submodules.dec2 = pdecode2 = self.pdecode2
 171         m.submodules.svp64 = svp64 = self.svp64
 172
 173         # convenience
 174         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 175         intrf = self.core.regs.rf['int']
 176
 177         # clock delay power-on reset
 178         cd_por  = ClockDomain(reset_less=True)
 179         cd_sync = ClockDomain()
 180         core_sync = ClockDomain("coresync")
 181         m.domains += cd_por, cd_sync, core_sync
 182
 183         ti_rst = Signal(reset_less=True)
 184         delay = Signal(range(4), reset=3)
 185         with m.If(delay != 0):
 186             m.d.por += delay.eq(delay - 1)
 187         comb += cd_por.clk.eq(ClockSignal())
 188
 189         # power-on reset delay
 190         core_rst = ResetSignal("coresync")
 191         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 192         comb += core_rst.eq(ti_rst)
 193
 194         # busy/halted signals from core
 195         comb += self.busy_o.eq(core.busy_o)
 196         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 197
 198         # temporary hack: says "go" immediately for both address gen and ST
 199         l0 = core.l0
 200         ldst = core.fus.fus['ldst0']
 201         st_go_edge = rising_edge(m, ldst.st.rel_o)
 202         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 203         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 204
 205         # PC and instruction from I-Memory
 206         pc_changed = Signal() # note write to PC
 207         comb += self.pc_o.eq(cur_state.pc)
 208         ilatch = Signal(32)
 209
 210         # address of the next instruction, in the absence of a branch
 211         # depends on the instruction size
 212         nia = Signal(64, reset_less=True)
 213
 214         # read the PC
 215         pc = Signal(64, reset_less=True)
 216         pc_ok_delay = Signal()
 217         sync += pc_ok_delay.eq(~self.pc_i.ok)
 218         with m.If(self.pc_i.ok):
 219             # incoming override (start from pc_i)
 220             comb += pc.eq(self.pc_i.data)
 221         with m.Else():
 222             # otherwise read StateRegs regfile for PC...
 223             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 224         # ... but on a 1-clock delay
 225         with m.If(pc_ok_delay):
 226             comb += pc.eq(self.state_r_pc.data_o)
 227
 228         # don't write pc every cycle
 229         comb += self.state_w_pc.wen.eq(0)
 230         comb += self.state_w_pc.data_i.eq(0)
 231
 232         # don't read msr or svstate every cycle
 233         comb += self.state_r_sv.ren.eq(0)
 234         comb += self.state_r_msr.ren.eq(0)
 235         msr_read = Signal(reset=1)
 236         sv_read = Signal(reset=1)
 237
 238         # connect up debug signals
 239         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 240         comb += dbg.terminate_i.eq(core.core_terminate_o)
 241         comb += dbg.state.pc.eq(pc)
 242         #comb += dbg.state.pc.eq(cur_state.pc)
 243         comb += dbg.state.msr.eq(cur_state.msr)
 244
 245         # temporaries
 246         core_busy_o = core.busy_o                 # core is busy
 247         core_ivalid_i = core.ivalid_i             # instruction is valid
 248         core_issue_i = core.issue_i               # instruction is issued
 249         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 250         insn_type = core.e.do.insn_type           # instruction MicroOp type
 251
 252         # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
 253         # these are the handshake signals between fetch and decode/execute
 254
 255         # fetch FSM can run as soon as the PC is valid
 256         fetch_pc_valid_i = Signal()
 257         fetch_pc_ready_o = Signal()
 258         # when done, deliver the instruction to the next FSM
 259         fetch_insn_valid_o = Signal()
 260         fetch_insn_ready_i = Signal()
 261
 262         # latches copy of raw fetched instruction
 263         fetch_insn_o = Signal(32, reset_less=True)
 264
 265         # actually use a nmigen FSM for the first time (w00t)
 266         # this FSM is perhaps unusual in that it detects conditions
 267         # then "holds" information, combinatorially, for the core
 268         # (as opposed to using sync - which would be on a clock's delay)
 269         # this includes the actual opcode, valid flags and so on.
 270
 271         # this FSM performs fetch of raw instruction data, partial-decodes
 272         # it 32-bit at a time to detect SVP64 prefixes, and will optionally
 273         # read a 2nd 32-bit quantity if that occurs.
 274
 275         with m.FSM(name='fetch_fsm'):
 276
 277             # waiting (zzz)
 278             with m.State("IDLE"):
 279                 with m.If(~dbg.core_stop_o & ~core_rst):
 280                     comb += fetch_pc_ready_o.eq(1)
 281                     with m.If(fetch_pc_valid_i):
 282                         # instruction allowed to go: start by reading the PC
 283                         # capture the PC and also drop it into Insn Memory
 284                         # we have joined a pair of combinatorial memory
 285                         # lookups together.  this is Generally Bad.
 286                         comb += self.imem.a_pc_i.eq(pc)
 287                         comb += self.imem.a_valid_i.eq(1)
 288                         comb += self.imem.f_valid_i.eq(1)
 289                         sync += cur_state.pc.eq(pc)
 290
 291                         # initiate read of MSR/SVSTATE. arrives one clock later
 292                         comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 293                         comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 294                         sync += msr_read.eq(0)
 295                         sync += sv_read.eq(0)
 296
 297                         m.next = "INSN_READ"  # move to "wait for bus" phase
 298                 with m.Else():
 299                     comb += core.core_stopped_i.eq(1)
 300                     comb += dbg.core_stopped_i.eq(1)
 301
 302             # dummy pause to find out why simulation is not keeping up
 303             with m.State("INSN_READ"):
 304                 # one cycle later, msr/sv read arrives.  valid only once.
 305                 with m.If(~msr_read):
 306                     sync += msr_read.eq(1) # yeah don't read it again
 307                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 308                 with m.If(~sv_read):
 309                     sync += sv_read.eq(1) # yeah don't read it again
 310                     sync += cur_state.svstate.eq(self.state_r_sv.data_o)
 311                 with m.If(self.imem.f_busy_o): # zzz...
 312                     # busy: stay in wait-read
 313                     comb += self.imem.a_valid_i.eq(1)
 314                     comb += self.imem.f_valid_i.eq(1)
 315                 with m.Else():
 316                     # not busy: instruction fetched
 317                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 318                     # decode the SVP64 prefix, if any
 319                     comb += svp64.raw_opcode_in.eq(insn)
 320                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 321                     # pass the decoded prefix (if any) to PowerDecoder2
 322                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 323                     # calculate the address of the following instruction
 324                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 325                     sync += nia.eq(cur_state.pc + insn_size)
 326                     with m.If(~svp64.is_svp64_mode):
 327                         # with no prefix, store the instruction
 328                         # and hand it directly to the next FSM
 329                         sync += fetch_insn_o.eq(insn)
 330                         m.next = "INSN_READY"
 331                     with m.Else():
 332                         # fetch the rest of the instruction from memory
 333                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 334                         comb += self.imem.a_valid_i.eq(1)
 335                         comb += self.imem.f_valid_i.eq(1)
 336                         m.next = "INSN_READ2"
 337
 338             with m.State("INSN_READ2"):
 339                 with m.If(self.imem.f_busy_o):  # zzz...
 340                     # busy: stay in wait-read
 341                     comb += self.imem.a_valid_i.eq(1)
 342                     comb += self.imem.f_valid_i.eq(1)
 343                 with m.Else():
 344                     # not busy: instruction fetched
 345                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 346                     sync += fetch_insn_o.eq(insn)
 347                     m.next = "INSN_READY"
 348
 349             with m.State("INSN_READY"):
 350                 # hand over the instruction, to be decoded
 351                 comb += fetch_insn_valid_o.eq(1)
 352                 with m.If(fetch_insn_ready_i):
 353                     m.next = "IDLE"
 354
 355         # decode / issue / execute FSM.  this interacts with the "fetch" FSM
 356         # through fetch_pc_ready/valid (incoming) and fetch_insn_ready/valid
 357         # (outgoing).  SVP64 RM prefixes have already been set up by the
 358         # "fetch" phase, so execute is fairly straightforward.
 359
 360         with m.FSM():
 361
 362             # go fetch the instruction at the current PC
 363             # at this point, there is no instruction running, that
 364             # could inadvertently update the PC.
 365             with m.State("INSN_FETCH"):
 366                 comb += fetch_pc_valid_i.eq(1)
 367                 with m.If(fetch_pc_ready_o):
 368                     m.next = "INSN_WAIT"
 369
 370             # decode the instruction when it arrives
 371             with m.State("INSN_WAIT"):
 372                 comb += fetch_insn_ready_i.eq(1)
 373                 with m.If(fetch_insn_valid_o):
 374                     # decode the instruction
 375                     # TODO, before issuing new instruction first
 376                     # check if it's SVP64. (svp64.is_svp64_mode set)
 377                     # if yes, record the svp64_rm, put that into
 378                     # pdecode2.sv_rm, then read another 32 bits (INSN_FETCH2?)
 379                     comb += dec_opcode_i.eq(fetch_insn_o)  # actual opcode
 380                     sync += core.e.eq(pdecode2.e)
 381                     sync += core.state.eq(cur_state)
 382                     sync += core.raw_insn_i.eq(dec_opcode_i)
 383                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 384                     sync += ilatch.eq(insn) # latch current insn
 385                     # also drop PC and MSR into decode "state"
 386                     m.next = "INSN_START" # move to "start"
 387
 388             # waiting for instruction bus (stays there until not busy)
 389             with m.State("INSN_START"):
 390                 comb += core_ivalid_i.eq(1) # instruction is valid
 391                 comb += core_issue_i.eq(1)  # and issued
 392                 sync += pc_changed.eq(0)
 393
 394                 m.next = "INSN_ACTIVE" # move to "wait completion"
 395
 396             # instruction started: must wait till it finishes
 397             with m.State("INSN_ACTIVE"):
 398                 with m.If(insn_type != MicrOp.OP_NOP):
 399                     comb += core_ivalid_i.eq(1) # instruction is valid
 400                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 401                     sync += pc_changed.eq(1)
 402                 with m.If(~core_busy_o): # instruction done!
 403                     # ok here we are not reading the branch unit.  TODO
 404                     # this just blithely overwrites whatever pipeline
 405                     # updated the PC
 406                     with m.If(~pc_changed):
 407                         comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 408                         comb += self.state_w_pc.data_i.eq(nia)
 409                     sync += core.e.eq(0)
 410                     sync += core.raw_insn_i.eq(0)
 411                     sync += core.bigendian_i.eq(0)
 412                     m.next = "INSN_FETCH"  # back to fetch
 413
 414         # this bit doesn't have to be in the FSM: connect up to read
 415         # regfiles on demand from DMI
 416         with m.If(d_reg.req): # request for regfile access being made
 417             # TODO: error-check this
 418             # XXX should this be combinatorial?  sync better?
 419             if intrf.unary:
 420                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 421             else:
 422                 comb += self.int_r.addr.eq(d_reg.addr)
 423                 comb += self.int_r.ren.eq(1)
 424         d_reg_delay  = Signal()
 425         sync += d_reg_delay.eq(d_reg.req)
 426         with m.If(d_reg_delay):
 427             # data arrives one clock later
 428             comb += d_reg.data.eq(self.int_r.data_o)
 429             comb += d_reg.ack.eq(1)
 430
 431         # sigh same thing for CR debug
 432         with m.If(d_cr.req): # request for regfile access being made
 433             comb += self.cr_r.ren.eq(0b11111111) # enable all
 434         d_cr_delay  = Signal()
 435         sync += d_cr_delay.eq(d_cr.req)
 436         with m.If(d_cr_delay):
 437             # data arrives one clock later
 438             comb += d_cr.data.eq(self.cr_r.data_o)
 439             comb += d_cr.ack.eq(1)
 440
 441         # aaand XER...
 442         with m.If(d_xer.req): # request for regfile access being made
 443             comb += self.xer_r.ren.eq(0b111111) # enable all
 444         d_xer_delay  = Signal()
 445         sync += d_xer_delay.eq(d_xer.req)
 446         with m.If(d_xer_delay):
 447             # data arrives one clock later
 448             comb += d_xer.data.eq(self.xer_r.data_o)
 449             comb += d_xer.ack.eq(1)
 450
 451         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 452         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 453         self.tb_dec_fsm(m, cur_state.dec)
 454
 455         return m
 456
 457     def tb_dec_fsm(self, m, spr_dec):
 458         """tb_dec_fsm
 459
 460         this is a FSM for updating either dec or tb.  it runs alternately
 461         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 462         value to DEC, however the regfile has "passthrough" on it so this
 463         *should* be ok.
 464
 465         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 466         """
 467
 468         comb, sync = m.d.comb, m.d.sync
 469         fast_rf = self.core.regs.rf['fast']
 470         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 471         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 472
 473         with m.FSM() as fsm:
 474
 475             # initiates read of current DEC
 476             with m.State("DEC_READ"):
 477                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 478                 comb += fast_r_dectb.ren.eq(1)
 479                 m.next = "DEC_WRITE"
 480
 481             # waits for DEC read to arrive (1 cycle), updates with new value
 482             with m.State("DEC_WRITE"):
 483                 new_dec = Signal(64)
 484                 # TODO: MSR.LPCR 32-bit decrement mode
 485                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 486                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 487                 comb += fast_w_dectb.wen.eq(1)
 488                 comb += fast_w_dectb.data_i.eq(new_dec)
 489                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 490                 m.next = "TB_READ"
 491
 492             # initiates read of current TB
 493             with m.State("TB_READ"):
 494                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 495                 comb += fast_r_dectb.ren.eq(1)
 496                 m.next = "TB_WRITE"
 497
 498             # waits for read TB to arrive, initiates write of current TB
 499             with m.State("TB_WRITE"):
 500                 new_tb = Signal(64)
 501                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 502                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 503                 comb += fast_w_dectb.wen.eq(1)
 504                 comb += fast_w_dectb.data_i.eq(new_tb)
 505                 m.next = "DEC_READ"
 506
 507         return m
 508
 509     def __iter__(self):
 510         yield from self.pc_i.ports()
 511         yield self.pc_o
 512         yield self.memerr_o
 513         yield from self.core.ports()
 514         yield from self.imem.ports()
 515         yield self.core_bigendian_i
 516         yield self.busy_o
 517
 518     def ports(self):
 519         return list(self)
 520
 521     def external_ports(self):
 522         ports = self.pc_i.ports()
 523         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 524                 ]
 525
 526         if self.jtag_en:
 527             ports += list(self.jtag.external_ports())
 528         else:
 529             # don't add DMI if JTAG is enabled
 530             ports += list(self.dbg.dmi.ports())
 531
 532         ports += list(self.imem.ibus.fields.values())
 533         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 534
 535         if self.xics:
 536             ports += list(self.xics_icp.bus.fields.values())
 537             ports += list(self.xics_ics.bus.fields.values())
 538             ports.append(self.int_level_i)
 539
 540         if self.gpio:
 541             ports += list(self.simple_gpio.bus.fields.values())
 542             ports.append(self.gpio_o)
 543
 544         return ports
 545
 546     def ports(self):
 547         return list(self)
 548
 549
 550 class TestIssuer(Elaboratable):
 551     def __init__(self, pspec):
 552         self.ti = TestIssuerInternal(pspec)
 553
 554         self.pll = DummyPLL()
 555
 556         # PLL direct clock or not
 557         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 558         if self.pll_en:
 559             self.pll_18_o = Signal(reset_less=True)
 560
 561     def elaborate(self, platform):
 562         m = Module()
 563         comb = m.d.comb
 564
 565         # TestIssuer runs at direct clock
 566         m.submodules.ti = ti = self.ti
 567         cd_int = ClockDomain("coresync")
 568
 569         if self.pll_en:
 570             # ClockSelect runs at PLL output internal clock rate
 571             m.submodules.pll = pll = self.pll
 572
 573             # add clock domains from PLL
 574             cd_pll = ClockDomain("pllclk")
 575             m.domains += cd_pll
 576
 577             # PLL clock established.  has the side-effect of running clklsel
 578             # at the PLL's speed (see DomainRenamer("pllclk") above)
 579             pllclk = ClockSignal("pllclk")
 580             comb += pllclk.eq(pll.clk_pll_o)
 581
 582             # wire up external 24mhz to PLL
 583             comb += pll.clk_24_i.eq(ClockSignal())
 584
 585             # output 18 mhz PLL test signal
 586             comb += self.pll_18_o.eq(pll.pll_18_o)
 587
 588             # now wire up ResetSignals.  don't mind them being in this domain
 589             pll_rst = ResetSignal("pllclk")
 590             comb += pll_rst.eq(ResetSignal())
 591
 592         # internal clock is set to selector clock-out.  has the side-effect of
 593         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 594         intclk = ClockSignal("coresync")
 595         if self.pll_en:
 596             comb += intclk.eq(pll.clk_pll_o)
 597         else:
 598             comb += intclk.eq(ClockSignal())
 599
 600         return m
 601
 602     def ports(self):
 603         return list(self.ti.ports()) + list(self.pll.ports()) + \
 604                [ClockSignal(), ResetSignal()]
 605
 606     def external_ports(self):
 607         ports = self.ti.external_ports()
 608         ports.append(ClockSignal())
 609         ports.append(ResetSignal())
 610         if self.pll_en:
 611             ports.append(self.pll.clk_sel_i)
 612             ports.append(self.pll_18_o)
 613             ports.append(self.pll.pll_lck_o)
 614         return ports
 615
 616
 617 if __name__ == '__main__':
 618     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 619              'spr': 1,
 620              'div': 1,
 621              'mul': 1,
 622              'shiftrot': 1
 623             }
 624     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 625                          imem_ifacetype='bare_wb',
 626                          addr_wid=48,
 627                          mask_wid=8,
 628                          reg_wid=64,
 629                          units=units)
 630     dut = TestIssuer(pspec)
 631     vl = main(dut, ports=dut.ports(), name="test_issuer")
 632
 633     if len(sys.argv) == 1:
 634         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 635         with open("test_issuer.il", "w") as f:
 636             f.write(vl)