3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from soc
.decoder
.power_decoder
import create_pdecode
25 from soc
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
26 from soc
.decoder
.decode2execute1
import IssuerDecode2ToOperand
27 from soc
.decoder
.decode2execute1
import Data
28 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
29 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
30 from soc
.simple
.core
import NonProductionCore
31 from soc
.config
.test
.test_loadstore
import TestMemPspec
32 from soc
.config
.ifetch
import ConfigFetchUnit
33 from soc
.decoder
.power_enums
import MicrOp
34 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
35 from soc
.debug
.jtag
import JTAG
36 from soc
.config
.pinouts
import get_pinspecs
37 from soc
.config
.state
import CoreState
38 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
39 from soc
.bus
.simple_gpio
import SimpleGPIO
40 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
41 from soc
.clock
.select
import ClockSelect
42 from soc
.clock
.dummypll
import DummyPLL
43 from soc
.sv
.svstate
import SVSTATERec
46 from nmutil
.util
import rising_edge
48 def get_insn(f_instr_o
, pc
):
49 if f_instr_o
.width
== 32:
52 # 64-bit: bit 2 of pc decides which word to select
53 return f_instr_o
.word_select(pc
[2], 32)
56 class TestIssuerInternal(Elaboratable
):
57 """TestIssuer - reads instructions from TestMemory and issues them
59 efficiency and speed is not the main goal here: functional correctness is.
61 def __init__(self
, pspec
):
63 # JTAG interface. add this right at the start because if it's
64 # added it *modifies* the pspec, by adding enable/disable signals
65 # for parts of the rest of the core
66 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
68 subset
= {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
70 self
.jtag
= JTAG(get_pinspecs(subset
=subset
))
71 # add signals to pspec to enable/disable icache and dcache
72 # (or data and intstruction wishbone if icache/dcache not included)
73 # https://bugs.libre-soc.org/show_bug.cgi?id=520
74 # TODO: do we actually care if these are not domain-synchronised?
75 # honestly probably not.
76 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
77 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
78 self
.wb_sram_en
= self
.jtag
.wb_sram_en
80 self
.wb_sram_en
= Const(1)
83 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
84 pspec
.sram4x4kblock
== True)
88 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
))
90 # add interrupt controller?
91 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
93 self
.xics_icp
= XICS_ICP()
94 self
.xics_ics
= XICS_ICS()
95 self
.int_level_i
= self
.xics_ics
.int_level_i
97 # add GPIO peripheral?
98 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
100 self
.simple_gpio
= SimpleGPIO()
101 self
.gpio_o
= self
.simple_gpio
.gpio_o
103 # main instruction core25
104 self
.core
= core
= NonProductionCore(pspec
)
106 # instruction decoder. goes into Trap Record
107 pdecode
= create_pdecode()
108 self
.cur_state
= CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
109 self
.pdecode2
= PowerDecode2(pdecode
, state
=self
.cur_state
,
110 opkls
=IssuerDecode2ToOperand
)
111 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
113 # Test Instruction memory
114 self
.imem
= ConfigFetchUnit(pspec
).fu
115 # one-row cache of instruction read
116 self
.iline
= Signal(64) # one instruction line
117 self
.iprev_adr
= Signal(64) # previous address: if different, do read
120 self
.dbg
= CoreDebug()
122 # instruction go/monitor
123 self
.pc_o
= Signal(64, reset_less
=True)
124 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
125 self
.core_bigendian_i
= Signal()
126 self
.busy_o
= Signal(reset_less
=True)
127 self
.memerr_o
= Signal(reset_less
=True)
129 # STATE regfile read /write ports for PC, MSR, SVSTATE
130 staterf
= self
.core
.regs
.rf
['state']
131 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
132 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
133 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
134 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
135 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
137 # DMI interface access
138 intrf
= self
.core
.regs
.rf
['int']
139 crrf
= self
.core
.regs
.rf
['cr']
140 xerrf
= self
.core
.regs
.rf
['xer']
141 self
.int_r
= intrf
.r_ports
['dmi'] # INT read
142 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR read
143 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER read
145 # hack method of keeping an eye on whether branch/trap set the PC
146 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
147 self
.state_nia
.wen
.name
= 'state_nia_wen'
149 def fetch_fsm(self
, m
, core
, dbg
, pc
, pc_changed
, insn_done
,
151 fetch_pc_ready_o
, fetch_pc_valid_i
,
152 exec_insn_valid_o
, exec_insn_ready_i
,
155 this FSM performs fetch of raw instruction data, partial-decodes
156 it 32-bit at a time to detect SVP64 prefixes, and will optionally
157 read a 2nd 32-bit quantity if that occurs.
161 pdecode2
= self
.pdecode2
164 msr_read
= Signal(reset
=1)
165 sv_read
= Signal(reset
=1)
167 # address of the next instruction, in the absence of a branch
168 # depends on the instruction size
169 nia
= Signal(64, reset_less
=True)
171 with m
.FSM(name
='fetch_fsm'):
174 with m
.State("IDLE"):
175 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
176 comb
+= fetch_pc_ready_o
.eq(1)
177 with m
.If(fetch_pc_valid_i
):
178 # instruction allowed to go: start by reading the PC
179 # capture the PC and also drop it into Insn Memory
180 # we have joined a pair of combinatorial memory
181 # lookups together. this is Generally Bad.
182 comb
+= self
.imem
.a_pc_i
.eq(pc
)
183 comb
+= self
.imem
.a_valid_i
.eq(1)
184 comb
+= self
.imem
.f_valid_i
.eq(1)
185 sync
+= cur_state
.pc
.eq(pc
)
187 # initiate read of MSR/SVSTATE. arrives one clock later
188 comb
+= self
.state_r_msr
.ren
.eq(1 << StateRegs
.MSR
)
189 comb
+= self
.state_r_sv
.ren
.eq(1 << StateRegs
.SVSTATE
)
190 sync
+= msr_read
.eq(0)
191 sync
+= sv_read
.eq(0)
193 m
.next
= "INSN_READ" # move to "wait for bus" phase
195 comb
+= core
.core_stopped_i
.eq(1)
196 comb
+= dbg
.core_stopped_i
.eq(1)
198 # dummy pause to find out why simulation is not keeping up
199 with m
.State("INSN_READ"):
200 # one cycle later, msr/sv read arrives. valid only once.
201 with m
.If(~msr_read
):
202 sync
+= msr_read
.eq(1) # yeah don't read it again
203 sync
+= cur_state
.msr
.eq(self
.state_r_msr
.data_o
)
205 sync
+= sv_read
.eq(1) # yeah don't read it again
206 sync
+= cur_state
.svstate
.eq(self
.state_r_sv
.data_o
)
207 with m
.If(self
.imem
.f_busy_o
): # zzz...
208 # busy: stay in wait-read
209 comb
+= self
.imem
.a_valid_i
.eq(1)
210 comb
+= self
.imem
.f_valid_i
.eq(1)
212 # not busy: instruction fetched
213 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
214 # decode the SVP64 prefix, if any
215 comb
+= svp64
.raw_opcode_in
.eq(insn
)
216 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
217 # pass the decoded prefix (if any) to PowerDecoder2
218 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
219 # calculate the address of the following instruction
220 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
221 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
222 with m
.If(~svp64
.is_svp64_mode
):
223 # with no prefix, store the instruction
224 # and hand it directly to the next FSM
225 sync
+= fetch_insn_o
.eq(insn
)
226 m
.next
= "INSN_READY"
228 # fetch the rest of the instruction from memory
229 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
230 comb
+= self
.imem
.a_valid_i
.eq(1)
231 comb
+= self
.imem
.f_valid_i
.eq(1)
232 m
.next
= "INSN_READ2"
234 with m
.State("INSN_READ2"):
235 with m
.If(self
.imem
.f_busy_o
): # zzz...
236 # busy: stay in wait-read
237 comb
+= self
.imem
.a_valid_i
.eq(1)
238 comb
+= self
.imem
.f_valid_i
.eq(1)
240 # not busy: instruction fetched
241 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
242 sync
+= fetch_insn_o
.eq(insn
)
243 m
.next
= "INSN_READY"
245 with m
.State("INSN_READY"):
246 # hand over the instruction, to be decoded
247 comb
+= exec_insn_valid_o
.eq(1)
248 with m
.If(exec_insn_ready_i
):
251 # code-morph: moving the actual PC-setting out of "execute"
252 # so that it's easier to move this into an "issue" FSM.
254 # ok here we are not reading the branch unit. TODO
255 # this just blithely overwrites whatever pipeline
257 core_busy_o
= core
.busy_o
# core is busy
258 with m
.If(insn_done
& (~pc_changed
) & (~core_busy_o
)):
259 comb
+= self
.state_w_pc
.wen
.eq(1<<StateRegs
.PC
)
260 comb
+= self
.state_w_pc
.data_i
.eq(nia
)
262 def execute_fsm(self
, m
, core
, insn_done
, pc_changed
,
263 cur_state
, fetch_insn_o
,
264 fetch_pc_ready_o
, fetch_pc_valid_i
,
265 exec_insn_valid_o
, exec_insn_ready_i
):
268 decode / issue / execute FSM. this interacts with the "fetch" FSM
269 through fetch_pc_ready/valid (incoming) and exec_insn_ready/valid
270 (outgoing). SVP64 RM prefixes have already been set up by the
271 "fetch" phase, so execute is fairly straightforward.
276 pdecode2
= self
.pdecode2
280 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
281 core_busy_o
= core
.busy_o
# core is busy
282 core_ivalid_i
= core
.ivalid_i
# instruction is valid
283 core_issue_i
= core
.issue_i
# instruction is issued
284 insn_type
= core
.e
.do
.insn_type
# instruction MicroOp type
288 # go fetch the instruction at the current PC
289 # at this point, there is no instruction running, that
290 # could inadvertently update the PC.
291 with m
.State("INSN_FETCH"):
292 comb
+= fetch_pc_valid_i
.eq(1)
293 with m
.If(fetch_pc_ready_o
):
296 # decode the instruction when it arrives
297 with m
.State("INSN_WAIT"):
298 comb
+= exec_insn_ready_i
.eq(1)
299 with m
.If(exec_insn_valid_o
):
300 # decode the instruction
301 comb
+= dec_opcode_i
.eq(fetch_insn_o
) # actual opcode
302 sync
+= core
.e
.eq(pdecode2
.e
)
303 sync
+= core
.state
.eq(cur_state
)
304 sync
+= core
.raw_insn_i
.eq(dec_opcode_i
)
305 sync
+= core
.bigendian_i
.eq(self
.core_bigendian_i
)
306 # also drop PC and MSR into decode "state"
307 m
.next
= "INSN_START" # move to "start"
309 # waiting for instruction bus (stays there until not busy)
310 with m
.State("INSN_START"):
311 comb
+= core_ivalid_i
.eq(1) # instruction is valid
312 comb
+= core_issue_i
.eq(1) # and issued
314 m
.next
= "INSN_ACTIVE" # move to "wait completion"
316 # instruction started: must wait till it finishes
317 with m
.State("INSN_ACTIVE"):
318 with m
.If(insn_type
!= MicrOp
.OP_NOP
):
319 comb
+= core_ivalid_i
.eq(1) # instruction is valid
320 with m
.If(self
.state_nia
.wen
& (1<<StateRegs
.PC
)):
321 sync
+= pc_changed
.eq(1)
322 with m
.If(~core_busy_o
): # instruction done!
323 comb
+= insn_done
.eq(1)
325 sync
+= core
.raw_insn_i
.eq(0)
326 sync
+= core
.bigendian_i
.eq(0)
327 sync
+= pc_changed
.eq(0)
328 m
.next
= "INSN_FETCH" # back to fetch
330 def elaborate(self
, platform
):
332 comb
, sync
= m
.d
.comb
, m
.d
.sync
334 m
.submodules
.core
= core
= DomainRenamer("coresync")(self
.core
)
335 m
.submodules
.imem
= imem
= self
.imem
336 m
.submodules
.dbg
= dbg
= self
.dbg
338 m
.submodules
.jtag
= jtag
= self
.jtag
339 # TODO: UART2GDB mux, here, from external pin
340 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
341 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
343 cur_state
= self
.cur_state
345 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
347 for i
, sram
in enumerate(self
.sram4k
):
348 m
.submodules
["sram4k_%d" % i
] = sram
349 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
351 # XICS interrupt handler
353 m
.submodules
.xics_icp
= icp
= self
.xics_icp
354 m
.submodules
.xics_ics
= ics
= self
.xics_ics
355 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
356 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
358 # GPIO test peripheral
360 m
.submodules
.simple_gpio
= simple_gpio
= self
.simple_gpio
362 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
363 # XXX causes litex ECP5 test to get wrong idea about input and output
364 # (but works with verilator sim *sigh*)
365 #if self.gpio and self.xics:
366 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
368 # instruction decoder
369 pdecode
= create_pdecode()
370 m
.submodules
.dec2
= pdecode2
= self
.pdecode2
371 m
.submodules
.svp64
= svp64
= self
.svp64
374 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
375 intrf
= self
.core
.regs
.rf
['int']
377 # clock delay power-on reset
378 cd_por
= ClockDomain(reset_less
=True)
379 cd_sync
= ClockDomain()
380 core_sync
= ClockDomain("coresync")
381 m
.domains
+= cd_por
, cd_sync
, core_sync
383 ti_rst
= Signal(reset_less
=True)
384 delay
= Signal(range(4), reset
=3)
385 with m
.If(delay
!= 0):
386 m
.d
.por
+= delay
.eq(delay
- 1)
387 comb
+= cd_por
.clk
.eq(ClockSignal())
389 # power-on reset delay
390 core_rst
= ResetSignal("coresync")
391 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
392 comb
+= core_rst
.eq(ti_rst
)
394 # busy/halted signals from core
395 comb
+= self
.busy_o
.eq(core
.busy_o
)
396 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
398 # temporary hack: says "go" immediately for both address gen and ST
400 ldst
= core
.fus
.fus
['ldst0']
401 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
402 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
) # link addr-go direct to rel
403 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
405 # PC and instruction from I-Memory
406 comb
+= self
.pc_o
.eq(cur_state
.pc
)
407 pc_changed
= Signal() # note write to PC
408 insn_done
= Signal() # fires just once
411 pc
= Signal(64, reset_less
=True)
412 pc_ok_delay
= Signal()
413 sync
+= pc_ok_delay
.eq(~self
.pc_i
.ok
)
414 with m
.If(self
.pc_i
.ok
):
415 # incoming override (start from pc_i)
416 comb
+= pc
.eq(self
.pc_i
.data
)
418 # otherwise read StateRegs regfile for PC...
419 comb
+= self
.state_r_pc
.ren
.eq(1<<StateRegs
.PC
)
420 # ... but on a 1-clock delay
421 with m
.If(pc_ok_delay
):
422 comb
+= pc
.eq(self
.state_r_pc
.data_o
)
424 # don't write pc every cycle
425 comb
+= self
.state_w_pc
.wen
.eq(0)
426 comb
+= self
.state_w_pc
.data_i
.eq(0)
428 # don't read msr or svstate every cycle
429 comb
+= self
.state_r_sv
.ren
.eq(0)
430 comb
+= self
.state_r_msr
.ren
.eq(0)
432 # connect up debug signals
433 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
434 comb
+= dbg
.terminate_i
.eq(core
.core_terminate_o
)
435 comb
+= dbg
.state
.pc
.eq(pc
)
436 #comb += dbg.state.pc.eq(cur_state.pc)
437 comb
+= dbg
.state
.msr
.eq(cur_state
.msr
)
439 # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
440 # these are the handshake signals between fetch and decode/execute
442 # fetch FSM can run as soon as the PC is valid
443 fetch_pc_valid_i
= Signal() # Execute tells Fetch "start next read"
444 fetch_pc_ready_o
= Signal() # Fetch Tells SVSTATE "proceed"
446 # SVSTATE FSM TODO. actually, an "Issue" FSM that happens to do SVSTATE
447 fetch_to_sv_ready_i
= Signal()
448 fetch_to_sv_valid_o
= Signal()
450 sv_to_exec_ready_i
= Signal()
451 sv_to_exec_valid_o
= Signal()
453 # when done, deliver the instruction to the next FSM
454 exec_insn_valid_o
= Signal()
455 exec_insn_ready_i
= Signal() # Execute acknowledges SVSTATE
457 # latches copy of raw fetched instruction
458 fetch_insn_o
= Signal(32, reset_less
=True)
460 # actually use a nmigen FSM for the first time (w00t)
461 # this FSM is perhaps unusual in that it detects conditions
462 # then "holds" information, combinatorially, for the core
463 # (as opposed to using sync - which would be on a clock's delay)
464 # this includes the actual opcode, valid flags and so on.
466 self
.fetch_fsm(m
, core
, dbg
, pc
, pc_changed
, insn_done
,
468 fetch_pc_ready_o
, fetch_pc_valid_i
,
469 exec_insn_valid_o
, exec_insn_ready_i
,
472 # TODO: an SVSTATE-based for-loop FSM that goes in between
473 # fetch pc/insn ready/valid and advances SVSTATE.srcstep
474 # until it reaches VL-1 or PowerDecoder2.no_out_vec is True.
476 self
.execute_fsm(m
, core
, insn_done
, pc_changed
,
477 cur_state
, fetch_insn_o
,
478 fetch_pc_ready_o
, fetch_pc_valid_i
,
479 exec_insn_valid_o
, exec_insn_ready_i
)
481 # for updating svstate (things like srcstep etc.)
482 update_svstate
= Signal() # TODO: move this somewhere above
483 new_svstate
= SVSTATERec("new_svstate") # and move this as well
484 # check if svstate needs updating: if so, write it to State Regfile
485 with m
.If(update_svstate
):
486 comb
+= self
.state_w_sv
.wen
.eq(1<<StateRegs
.SVSTATE
)
487 comb
+= self
.state_w_sv
.data_i
.eq(new_svstate
)
489 # this bit doesn't have to be in the FSM: connect up to read
490 # regfiles on demand from DMI
491 with m
.If(d_reg
.req
): # request for regfile access being made
492 # TODO: error-check this
493 # XXX should this be combinatorial? sync better?
495 comb
+= self
.int_r
.ren
.eq(1<<d_reg
.addr
)
497 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
498 comb
+= self
.int_r
.ren
.eq(1)
499 d_reg_delay
= Signal()
500 sync
+= d_reg_delay
.eq(d_reg
.req
)
501 with m
.If(d_reg_delay
):
502 # data arrives one clock later
503 comb
+= d_reg
.data
.eq(self
.int_r
.data_o
)
504 comb
+= d_reg
.ack
.eq(1)
506 # sigh same thing for CR debug
507 with m
.If(d_cr
.req
): # request for regfile access being made
508 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
509 d_cr_delay
= Signal()
510 sync
+= d_cr_delay
.eq(d_cr
.req
)
511 with m
.If(d_cr_delay
):
512 # data arrives one clock later
513 comb
+= d_cr
.data
.eq(self
.cr_r
.data_o
)
514 comb
+= d_cr
.ack
.eq(1)
517 with m
.If(d_xer
.req
): # request for regfile access being made
518 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
519 d_xer_delay
= Signal()
520 sync
+= d_xer_delay
.eq(d_xer
.req
)
521 with m
.If(d_xer_delay
):
522 # data arrives one clock later
523 comb
+= d_xer
.data
.eq(self
.xer_r
.data_o
)
524 comb
+= d_xer
.ack
.eq(1)
526 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
527 # (which uses that in PowerDecoder2 to raise 0x900 exception)
528 self
.tb_dec_fsm(m
, cur_state
.dec
)
532 def tb_dec_fsm(self
, m
, spr_dec
):
535 this is a FSM for updating either dec or tb. it runs alternately
536 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
537 value to DEC, however the regfile has "passthrough" on it so this
540 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
543 comb
, sync
= m
.d
.comb
, m
.d
.sync
544 fast_rf
= self
.core
.regs
.rf
['fast']
545 fast_r_dectb
= fast_rf
.r_ports
['issue'] # DEC/TB
546 fast_w_dectb
= fast_rf
.w_ports
['issue'] # DEC/TB
550 # initiates read of current DEC
551 with m
.State("DEC_READ"):
552 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.DEC
)
553 comb
+= fast_r_dectb
.ren
.eq(1)
556 # waits for DEC read to arrive (1 cycle), updates with new value
557 with m
.State("DEC_WRITE"):
559 # TODO: MSR.LPCR 32-bit decrement mode
560 comb
+= new_dec
.eq(fast_r_dectb
.data_o
- 1)
561 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.DEC
)
562 comb
+= fast_w_dectb
.wen
.eq(1)
563 comb
+= fast_w_dectb
.data_i
.eq(new_dec
)
564 sync
+= spr_dec
.eq(new_dec
) # copy into cur_state for decoder
567 # initiates read of current TB
568 with m
.State("TB_READ"):
569 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.TB
)
570 comb
+= fast_r_dectb
.ren
.eq(1)
573 # waits for read TB to arrive, initiates write of current TB
574 with m
.State("TB_WRITE"):
576 comb
+= new_tb
.eq(fast_r_dectb
.data_o
+ 1)
577 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.TB
)
578 comb
+= fast_w_dectb
.wen
.eq(1)
579 comb
+= fast_w_dectb
.data_i
.eq(new_tb
)
585 yield from self
.pc_i
.ports()
588 yield from self
.core
.ports()
589 yield from self
.imem
.ports()
590 yield self
.core_bigendian_i
596 def external_ports(self
):
597 ports
= self
.pc_i
.ports()
598 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
602 ports
+= list(self
.jtag
.external_ports())
604 # don't add DMI if JTAG is enabled
605 ports
+= list(self
.dbg
.dmi
.ports())
607 ports
+= list(self
.imem
.ibus
.fields
.values())
608 ports
+= list(self
.core
.l0
.cmpi
.lsmem
.lsi
.slavebus
.fields
.values())
611 for sram
in self
.sram4k
:
612 ports
+= list(sram
.bus
.fields
.values())
615 ports
+= list(self
.xics_icp
.bus
.fields
.values())
616 ports
+= list(self
.xics_ics
.bus
.fields
.values())
617 ports
.append(self
.int_level_i
)
620 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
621 ports
.append(self
.gpio_o
)
629 class TestIssuer(Elaboratable
):
630 def __init__(self
, pspec
):
631 self
.ti
= TestIssuerInternal(pspec
)
633 self
.pll
= DummyPLL()
635 # PLL direct clock or not
636 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
638 self
.pll_18_o
= Signal(reset_less
=True)
640 def elaborate(self
, platform
):
644 # TestIssuer runs at direct clock
645 m
.submodules
.ti
= ti
= self
.ti
646 cd_int
= ClockDomain("coresync")
649 # ClockSelect runs at PLL output internal clock rate
650 m
.submodules
.pll
= pll
= self
.pll
652 # add clock domains from PLL
653 cd_pll
= ClockDomain("pllclk")
656 # PLL clock established. has the side-effect of running clklsel
657 # at the PLL's speed (see DomainRenamer("pllclk") above)
658 pllclk
= ClockSignal("pllclk")
659 comb
+= pllclk
.eq(pll
.clk_pll_o
)
661 # wire up external 24mhz to PLL
662 comb
+= pll
.clk_24_i
.eq(ClockSignal())
664 # output 18 mhz PLL test signal
665 comb
+= self
.pll_18_o
.eq(pll
.pll_18_o
)
667 # now wire up ResetSignals. don't mind them being in this domain
668 pll_rst
= ResetSignal("pllclk")
669 comb
+= pll_rst
.eq(ResetSignal())
671 # internal clock is set to selector clock-out. has the side-effect of
672 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
673 intclk
= ClockSignal("coresync")
675 comb
+= intclk
.eq(pll
.clk_pll_o
)
677 comb
+= intclk
.eq(ClockSignal())
682 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
683 [ClockSignal(), ResetSignal()]
685 def external_ports(self
):
686 ports
= self
.ti
.external_ports()
687 ports
.append(ClockSignal())
688 ports
.append(ResetSignal())
690 ports
.append(self
.pll
.clk_sel_i
)
691 ports
.append(self
.pll_18_o
)
692 ports
.append(self
.pll
.pll_lck_o
)
696 if __name__
== '__main__':
697 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
703 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
704 imem_ifacetype
='bare_wb',
709 dut
= TestIssuer(pspec
)
710 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
712 if len(sys
.argv
) == 1:
713 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
714 with
open("test_issuer.il", "w") as f
: