src/soc/simple/issuer_verilog.py

   1 """simple core issuer verilog generator
   2 """
   3
   4 import argparse
   5 from nmigen.cli import verilog
   6
   7 from soc.config.test.test_loadstore import TestMemPspec
   8 from soc.simple.issuer import TestIssuer
   9
  10
  11 if __name__ == '__main__':
  12     parser = argparse.ArgumentParser(description="Simple core issuer " \
  13                                      "verilog generator")
  14     parser.add_argument("output_filename")
  15     parser.add_argument("--enable-xics", action="store_true",
  16                         help="Disable interrupts",
  17                         default=True)
  18     parser.add_argument("--use-pll", action="store_true", help="Enable pll",
  19                         default=False)
  20     parser.add_argument("--enable-testgpio", action="store_true",
  21                         help="Disable gpio pins",
  22                         default=False)
  23     parser.add_argument("--debug", default="jtag", help="Select debug " \
  24                         "interface [jtag | dmi] [default jtag]")
  25
  26     args = parser.parse_args()
  27
  28     print(args)
  29
  30     units = {'alu': 1,
  31              'cr': 1, 'branch': 1, 'trap': 1,
  32              'logical': 1,
  33              'spr': 1,
  34              'div': 1,
  35              'mul': 1,
  36              'shiftrot': 1
  37             }
  38     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
  39                          imem_ifacetype='bare_wb',
  40                          addr_wid=48,
  41                          mask_wid=8,
  42                          # must leave at 64
  43                          reg_wid=64,
  44                          # set to 32 for instruction-memory width=32
  45                          imem_reg_wid=64,
  46                          # set to 32 to make data wishbone bus 32-bit
  47                          #wb_data_wid=32,
  48                          xics=args.enable_xics, # XICS interrupt controller
  49                          #nocore=True,          # to help test coriolis2 ioring
  50                          use_pll=args.use_pll,  # bypass PLL
  51                          gpio=args.enable_testgpio, # for test purposes
  52                          debug=args.debug,      # set to jtag or dmi
  53                          units=units)
  54
  55     dut = TestIssuer(pspec)
  56
  57     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")
  58     with open(args.output_filename, "w") as f:
  59         f.write(vl)