1 """simple core test, runs instructions from a TestMemory
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
14 # here is the logic which takes test cases and "executes" them.
15 # in this instance (TestRunner) its job is to instantiate both
16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
17 # simulator. it's also responsible for performing the single
18 # step and comparison.
19 from soc
.simple
.test
.test_runner
import TestRunner
22 #src/openpower/test/runner.py:class TestRunnerBase(FHDLTestCase):
25 from openpower
.test
.mmu
.mmu_cases
import MMUTestCase
26 from openpower
.test
.mmu
.mmu_rom_cases
import MMUTestCaseROM
, default_mem
27 from openpower
.test
.ldst
.ldst_cases
import LDSTTestCase
28 from openpower
.test
.ldst
.ldst_exc_cases
import LDSTExceptionTestCase
29 #from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
30 from soc
.experiment
.test
import pagetables
33 from openpower
.simulator
.program
import Program
34 from openpower
.endian
import bigendian
35 from openpower
.test
.common
import TestAccumulatorBase
37 from openpower
.consts
import MSR
39 from soc
.experiment
.test
import pagetables
42 class MMUTestCase(TestAccumulatorBase
):
44 def cse_first_vm_enabled(self
):
50 initial_regs
= [0] * 32
51 initial_regs
[2] = 0xc0000000005fc190
52 initial_regs
[6] = 0x0101
54 # memory same as microwatt test
55 initial_mem
= pagetables
.microwatt_linux_5_7_boot
57 # set virtual and non-privileged
58 # msr: 8000000000000011
59 initial_msr
= 0 << MSR
.PR
# must set "problem" state
60 initial_msr |
= 1 << MSR
.LE
# little-endian
61 initial_msr |
= 1 << MSR
.SF
# 64-bit
62 initial_msr |
= 1 << MSR
.DR
# set "virtual" state for data
64 # set PRTBL to 0xe000000
65 initial_sprs
= {720: 0xe000000, # PRTBL
69 print("MMUTEST: initial_msr=",initial_msr
)
70 self
.add_case(Program(lst
, bigendian
), initial_regs
,
71 initial_mem
=initial_mem
,
72 initial_sprs
=initial_sprs
,
73 initial_msr
=initial_msr
)
76 def case_first_vm_enabled_2(self
):
82 initial_regs
= [0] * 32
83 initial_regs
[2] = 0xc000000000598000
84 initial_regs
[6] = 0x0101
86 # memory same as microwatt test
87 initial_mem
= pagetables
.microwatt_linux_5_7_boot
89 # set virtual and non-privileged
90 # msr: 8000000000000011
91 initial_msr
= 0 << MSR
.PR
# must set "problem" state
92 initial_msr |
= 1 << MSR
.LE
# little-endian
93 initial_msr |
= 1 << MSR
.SF
# 64-bit
94 initial_msr |
= 1 << MSR
.DR
# set "virtual" state for data
96 # set PRTBL to 0xe000000
97 initial_sprs
= {720: 0xe00000c, # PRTBL
101 print("MMUTEST: initial_msr=",initial_msr
)
102 self
.add_case(Program(lst
, bigendian
), initial_regs
,
103 initial_mem
=initial_mem
,
104 initial_sprs
=initial_sprs
,
105 initial_msr
=initial_msr
)
108 if __name__
== "__main__":
110 if len(sys
.argv
) == 2:
111 if sys
.argv
[1] == 'nosvp64':
115 print ("SVP64 test mode enabled", svp64
)
117 unittest
.main(exit
=False)
118 suite
= unittest
.TestSuite()
120 # MMU/DCache integration tests
121 suite
.addTest(TestRunner(MMUTestCase().test_data
, svp64
=svp64
,
123 rom
=pagetables
.microwatt_linux_5_7_boot
))
125 runner
= unittest
.TextTestRunner()