src/soc/simple/test/test_runner.py

   1 """TestRunner class, runs TestIssuer instructions
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6  * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
   7 """
   8 from nmigen import Module, Signal, Cat, ClockSignal
   9 from nmigen.hdl.xfrm import ResetInserter
  10 from copy import copy
  11
  12 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  13 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  14 from nmutil.sim_tmp_alternative import Simulator, Settle
  15
  16 from nmutil.formaltest import FHDLTestCase
  17 from nmutil.gtkw import write_gtkw
  18 from nmigen.cli import rtlil
  19 from openpower.decoder.isa.caller import special_sprs, SVP64State
  20 from openpower.decoder.isa.all import ISA
  21 from openpower.endian import bigendian
  22
  23 from openpower.decoder.power_decoder import create_pdecode
  24 from openpower.decoder.power_decoder2 import PowerDecode2
  25 from soc.regfile.regfiles import StateRegs
  26
  27 from soc.simple.issuer import TestIssuerInternal
  28
  29 from soc.config.test.test_loadstore import TestMemPspec
  30 from soc.simple.test.test_core import (setup_regs, check_regs, check_mem,
  31                                        wait_for_busy_clear,
  32                                        wait_for_busy_hi)
  33 from soc.fu.compunits.test.test_compunit import (setup_tst_memory,
  34                                                  check_sim_memory)
  35 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
  36 from nmutil.util import wrap
  37 from soc.experiment.test.test_mmu_dcache import wb_get
  38 from openpower.test.state import TestState, StateRunner
  39
  40
  41 def setup_i_memory(imem, startaddr, instructions):
  42     mem = imem
  43     print("insn before, init mem", mem.depth, mem.width, mem,
  44           len(instructions))
  45     for i in range(mem.depth):
  46         yield mem._array[i].eq(0)
  47     yield Settle()
  48     startaddr //= 4  # instructions are 32-bit
  49     if mem.width == 32:
  50         mask = ((1 << 32)-1)
  51         for ins in instructions:
  52             if isinstance(ins, tuple):
  53                 insn, code = ins
  54             else:
  55                 insn, code = ins, ''
  56             insn = insn & 0xffffffff
  57             yield mem._array[startaddr].eq(insn)
  58             yield Settle()
  59             if insn != 0:
  60                 print("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  61             startaddr += 1
  62             startaddr = startaddr & mask
  63         return
  64
  65     # 64 bit
  66     mask = ((1 << 64)-1)
  67     for ins in instructions:
  68         if isinstance(ins, tuple):
  69             insn, code = ins
  70         else:
  71             insn, code = ins, ''
  72         insn = insn & 0xffffffff
  73         msbs = (startaddr >> 1) & mask
  74         val = yield mem._array[msbs]
  75         if insn != 0:
  76             print("before set", hex(4*startaddr),
  77                   hex(msbs), hex(val), hex(insn))
  78         lsb = 1 if (startaddr & 1) else 0
  79         val = (val | (insn << (lsb*32)))
  80         val = val & mask
  81         yield mem._array[msbs].eq(val)
  82         yield Settle()
  83         if insn != 0:
  84             print("after  set", hex(4*startaddr), hex(msbs), hex(val))
  85             print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  86         startaddr += 1
  87         startaddr = startaddr & mask
  88
  89
  90 def set_dmi(dmi, addr, data):
  91     yield dmi.req_i.eq(1)
  92     yield dmi.addr_i.eq(addr)
  93     yield dmi.din.eq(data)
  94     yield dmi.we_i.eq(1)
  95     while True:
  96         ack = yield dmi.ack_o
  97         if ack:
  98             break
  99         yield
 100     yield
 101     yield dmi.req_i.eq(0)
 102     yield dmi.addr_i.eq(0)
 103     yield dmi.din.eq(0)
 104     yield dmi.we_i.eq(0)
 105     yield
 106
 107
 108 def get_dmi(dmi, addr):
 109     yield dmi.req_i.eq(1)
 110     yield dmi.addr_i.eq(addr)
 111     yield dmi.din.eq(0)
 112     yield dmi.we_i.eq(0)
 113     while True:
 114         ack = yield dmi.ack_o
 115         if ack:
 116             break
 117         yield
 118     yield  # wait one
 119     data = yield dmi.dout  # get data after ack valid for 1 cycle
 120     yield dmi.req_i.eq(0)
 121     yield dmi.addr_i.eq(0)
 122     yield dmi.we_i.eq(0)
 123     yield
 124     return data
 125
 126
 127 class SimRunner(StateRunner):
 128     def __init__(self, dut, m, pspec):
 129         self.dut = dut
 130
 131         regreduce_en = pspec.regreduce_en == True
 132         self.simdec2 = simdec2 = PowerDecode2(None, regreduce_en=regreduce_en)
 133         m.submodules.simdec2 = simdec2  # pain in the neck
 134
 135     def prepare_for_test(self, test):
 136         self.test = test
 137         if False:
 138             yield
 139
 140     def run_test(self, instructions, gen, insncode):
 141         """run_sim_state - runs an ISACaller simulation
 142         """
 143
 144         dut, test, simdec2 = self.dut, self.test, self.simdec2
 145         sim_states = []
 146
 147         # set up the Simulator (which must track TestIssuer exactly)
 148         sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
 149                   test.msr,
 150                   initial_insns=gen, respect_pc=True,
 151                   disassembly=insncode,
 152                   bigendian=bigendian,
 153                   initial_svstate=test.svstate)
 154
 155         # run the loop of the instructions on the current test
 156         index = sim.pc.CIA.value//4
 157         while index < len(instructions):
 158             ins, code = instructions[index]
 159
 160             print("sim instr: 0x{:X}".format(ins & 0xffffffff))
 161             print(index, code)
 162
 163             # set up simulated instruction (in simdec2)
 164             try:
 165                 yield from sim.setup_one()
 166             except KeyError:  # instruction not in imem: stop
 167                 break
 168             yield Settle()
 169
 170             # call simulated operation
 171             print("sim", code)
 172             yield from sim.execute_one()
 173             yield Settle()
 174             index = sim.pc.CIA.value//4
 175
 176             # get sim register and memory TestState, add to list
 177             state = yield from TestState("sim", sim, dut, code)
 178             sim_states.append(state)
 179
 180         return sim_states
 181
 182
 183 class HDLRunner(StateRunner):
 184     def __init__(self, dut, m, pspec):
 185         self.dut = dut
 186         self.pc_i = Signal(32)
 187         self.svstate_i = Signal(64)
 188
 189         #hard_reset = Signal(reset_less=True)
 190         self.issuer = TestIssuerInternal(pspec)
 191         # use DMI RESET command instead, this does actually work though
 192         #issuer = ResetInserter({'coresync': hard_reset,
 193         #                        'sync': hard_reset})(issuer)
 194         m.submodules.issuer = self.issuer
 195         self.dmi = self.issuer.dbg.dmi
 196
 197         comb = m.d.comb
 198         comb += self.issuer.pc_i.data.eq(self.pc_i)
 199         comb += self.issuer.svstate_i.data.eq(self.svstate_i)
 200
 201     def prepare_for_test(self, test):
 202         self.test = test
 203
 204         # set up bigendian (TODO: don't do this, use MSR)
 205         yield self.issuer.core_bigendian_i.eq(bigendian)
 206         yield Settle()
 207
 208         yield
 209         yield
 210         yield
 211         yield
 212
 213     def setup_during_test(self):
 214         yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 215         yield
 216
 217     def run_test(self, instructions):
 218         """run_hdl_state - runs a TestIssuer nmigen HDL simulation
 219         """
 220
 221         imem = self.issuer.imem._get_memory()
 222         core = self.issuer.core
 223         dmi = self.issuer.dbg.dmi
 224         pdecode2 = self.issuer.pdecode2
 225         l0 = core.l0
 226         hdl_states = []
 227
 228         # establish the TestIssuer context (mem, regs etc)
 229
 230         pc = 0  # start address
 231         counter = 0  # test to pause/start
 232
 233         yield from setup_i_memory(imem, pc, instructions)
 234         #yield from setup_tst_memory(l0, self.test.mem)
 235         yield from setup_regs(pdecode2, core, self.test)
 236
 237         # set PC and SVSTATE
 238         yield self.pc_i.eq(pc)
 239         yield self.issuer.pc_i.ok.eq(1)
 240
 241         # copy initial SVSTATE
 242         initial_svstate = copy(self.test.svstate)
 243         if isinstance(initial_svstate, int):
 244             initial_svstate = SVP64State(initial_svstate)
 245         yield self.svstate_i.eq(initial_svstate.value)
 246         yield self.issuer.svstate_i.ok.eq(1)
 247         yield
 248
 249         print("instructions", instructions)
 250
 251         # run the loop of the instructions on the current test
 252         index = (yield self.issuer.cur_state.pc) // 4
 253         while index < len(instructions):
 254             ins, code = instructions[index]
 255
 256             print("hdl instr: 0x{:X}".format(ins & 0xffffffff))
 257             print(index, code)
 258
 259             if counter == 0:
 260                 # start the core
 261                 yield
 262                 yield from set_dmi(dmi, DBGCore.CTRL,
 263                                 1<<DBGCtrl.START)
 264                 yield self.issuer.pc_i.ok.eq(0) # no change PC after this
 265                 yield self.issuer.svstate_i.ok.eq(0) # ditto
 266                 yield
 267                 yield
 268
 269             counter = counter + 1
 270
 271             # wait until executed
 272             while not (yield self.issuer.insn_done):
 273                 yield
 274
 275             yield Settle()
 276
 277             index = (yield self.issuer.cur_state.pc) // 4
 278
 279             terminated = yield self.issuer.dbg.terminated_o
 280             print("terminated", terminated)
 281
 282             if index < len(instructions):
 283                 # Get HDL mem and state
 284                 state = yield from TestState("hdl", core, self.dut,
 285                                             code)
 286                 hdl_states.append(state)
 287
 288             if index >= len(instructions):
 289                 print ("index over, send dmi stop")
 290                 # stop at end
 291                 yield from set_dmi(dmi, DBGCore.CTRL,
 292                                 1<<DBGCtrl.STOP)
 293                 yield
 294                 yield
 295
 296             terminated = yield self.issuer.dbg.terminated_o
 297             print("terminated(2)", terminated)
 298             if terminated:
 299                 break
 300
 301         return hdl_states
 302
 303     def end_test(self):
 304         yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 305         yield
 306         yield
 307
 308         # TODO, here is where the static (expected) results
 309         # can be checked: register check (TODO, memory check)
 310         # see https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
 311         # yield from check_regs(self, sim, core, test, code,
 312         #                       >>>expected_data<<<)
 313
 314         # get CR
 315         cr = yield from get_dmi(self.dmi, DBGCore.CR)
 316         print("after test %s cr value %x" % (self.test.name, cr))
 317
 318         # get XER
 319         xer = yield from get_dmi(self.dmi, DBGCore.XER)
 320         print("after test %s XER value %x" % (self.test.name, xer))
 321
 322         # test of dmi reg get
 323         for int_reg in range(32):
 324             yield from set_dmi(self.dmi, DBGCore.GSPR_IDX, int_reg)
 325             value = yield from get_dmi(self.dmi, DBGCore.GSPR_DATA)
 326
 327             print("after test %s reg %2d value %x" %
 328             (self.test.name, int_reg, value))
 329
 330         # pull a reset
 331         yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
 332         yield
 333
 334
 335 class TestRunner(FHDLTestCase):
 336     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
 337                         svp64=True, run_hdl=True, run_sim=True):
 338         super().__init__("run_all")
 339         self.test_data = tst_data
 340         self.microwatt_mmu = microwatt_mmu
 341         self.rom = rom
 342         self.svp64 = svp64
 343         self.run_hdl = run_hdl
 344         self.run_sim = run_sim
 345
 346     def run_all(self):
 347         m = Module()
 348         comb = m.d.comb
 349         if self.microwatt_mmu:
 350             ldst_ifacetype = 'test_mmu_cache_wb'
 351         else:
 352             ldst_ifacetype = 'test_bare_wb'
 353         imem_ifacetype = 'test_bare_wb'
 354
 355         pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
 356                              imem_ifacetype=imem_ifacetype,
 357                              addr_wid=48,
 358                              mask_wid=8,
 359                              imem_reg_wid=64,
 360                              # wb_data_width=32,
 361                              use_pll=False,
 362                              nocore=False,
 363                              xics=False,
 364                              gpio=False,
 365                              regreduce=True,
 366                              svp64=self.svp64,
 367                              mmu=self.microwatt_mmu,
 368                              reg_wid=64)
 369
 370         ###### SETUP PHASE #######
 371         # StateRunner.setup_for_test()
 372
 373         # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 374         if self.run_hdl:
 375             hdlrun = HDLRunner(self, m, pspec)
 376
 377         if self.run_sim:
 378             simrun = SimRunner(self, m, pspec)
 379
 380         # run core clock at same rate as test clock
 381         intclk = ClockSignal("coresync")
 382         comb += intclk.eq(ClockSignal())
 383
 384         # nmigen Simulation - everything runs around this, so it
 385         # still has to be created.
 386         sim = Simulator(m)
 387         sim.add_clock(1e-6)
 388
 389         def process():
 390
 391             ###### PREPARATION PHASE AT START OF RUNNING #######
 392             # StateRunner.setup_during_test()
 393             # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 394             # but "normalise" the APIs, make openpower-isa StateRunner
 395             # dummy "yield" functions so if they're not provided at least
 396             # there is a fallback which can be "yielded".
 397
 398             if self.run_sim:
 399                 yield from simrun.setup_during_test() # TODO, some arguments?
 400
 401             if self.run_hdl:
 402                 yield from hdlrun.setup_during_test()
 403
 404             # get each test, completely reset the core, and run it
 405
 406             for test in self.test_data:
 407
 408                 with self.subTest(test.name):
 409
 410                     ###### PREPARATION PHASE AT START OF TEST #######
 411                     # StateRunner.prepare_for_test()
 412                     # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 413
 414                     if self.run_sim:
 415                         yield from simrun.prepare_for_test(test)
 416
 417                     if self.run_hdl:
 418                         yield from hdlrun.prepare_for_test(test)
 419
 420                     print(test.name)
 421                     program = test.program
 422                     print("regs", test.regs)
 423                     print("sprs", test.sprs)
 424                     print("cr", test.cr)
 425                     print("mem", test.mem)
 426                     print("msr", test.msr)
 427                     print("assem", program.assembly)
 428                     gen = list(program.generate_instructions())
 429                     insncode = program.assembly.splitlines()
 430                     instructions = list(zip(gen, insncode))
 431
 432                     ###### RUNNING OF EACH TEST #######
 433                     # StateRunner.step_test()
 434
 435                     # Run two tests (TODO, move these to functions)
 436                     # * first the Simulator, collate a batch of results
 437                     # * then the HDL, likewise
 438                     #   (actually, the other way round because running
 439                     #    Simulator somehow modifies the test state!)
 440                     # * finally, compare all the results
 441
 442                     # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 443
 444                     ##########
 445                     # 1. HDL
 446                     ##########
 447                     if self.run_hdl:
 448                         hdl_states = yield from hdlrun.run_test(instructions)
 449
 450                     ##########
 451                     # 2. Simulator
 452                     ##########
 453
 454                     if self.run_sim:
 455                         sim_states = yield from simrun.run_test(
 456                                                           instructions, gen,
 457                                                           insncode)
 458
 459                     ###### COMPARING THE TESTS #######
 460
 461                     ###############
 462                     # 3. Compare
 463                     ###############
 464
 465                     if self.run_sim:
 466                         last_sim = copy(sim_states[-1])
 467                     elif self.run_hdl:
 468                         last_sim = copy(hdl_states[-1])
 469                     else:
 470                         last_sim = None # err what are you doing??
 471
 472                     if self.run_hdl and self.run_sim:
 473                         for simstate, hdlstate in zip(sim_states, hdl_states):
 474                             simstate.compare(hdlstate)     # register check
 475                             simstate.compare_mem(hdlstate) # memory check
 476
 477                     if self.run_hdl:
 478                         print ("hdl_states")
 479                         for state in hdl_states:
 480                             print (state)
 481
 482                     if self.run_sim:
 483                         print ("sim_states")
 484                         for state in sim_states:
 485                             print (state)
 486
 487                     # compare against expected results
 488                     if test.expected is not None:
 489                         # have to put these in manually
 490                         test.expected.to_test = test.expected
 491                         test.expected.dut = self
 492                         test.expected.state_type = "expected"
 493                         test.expected.code = 0
 494                         # do actual comparison, against last item
 495                         last_sim.compare(test.expected)
 496
 497                     if self.run_hdl and self.run_sim:
 498                         self.assertTrue(len(hdl_states) == len(sim_states),
 499                                     "number of instructions run not the same")
 500
 501                 ###### END OF A TEST #######
 502                 # StateRunner.end_test()
 503                 # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 504
 505                 if self.run_sim:
 506                     yield from simrun.end_test() # TODO, some arguments?
 507
 508                 if self.run_hdl:
 509                     yield from hdlrun.end_test()
 510
 511             ###### END OF EVERYTHING (but none needs doing, still call fn) ####
 512             # StateRunner.cleanup()
 513             # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 514
 515             if self.run_sim:
 516                 yield from simrun.cleanup() # TODO, some arguments?
 517
 518             if self.run_hdl:
 519                 yield from hdlrun.cleanup()
 520
 521         styles = {
 522             'dec': {'base': 'dec'},
 523             'bin': {'base': 'bin'},
 524             'closed': {'closed': True}
 525         }
 526
 527         traces = [
 528             'clk',
 529             ('state machines', 'closed', [
 530                 'fetch_pc_i_valid', 'fetch_pc_o_ready',
 531                 'fetch_fsm_state',
 532                 'fetch_insn_o_valid', 'fetch_insn_i_ready',
 533                 'pred_insn_i_valid', 'pred_insn_o_ready',
 534                 'fetch_predicate_state',
 535                 'pred_mask_o_valid', 'pred_mask_i_ready',
 536                 'issue_fsm_state',
 537                 'exec_insn_i_valid', 'exec_insn_o_ready',
 538                 'exec_fsm_state',
 539                 'exec_pc_o_valid', 'exec_pc_i_ready',
 540                 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
 541                 'is_last', 'dec2.no_out_vec']),
 542             {'comment': 'fetch and decode'},
 543             (None, 'dec', [
 544                 'cia[63:0]', 'nia[63:0]', 'pc[63:0]',
 545                 'cur_pc[63:0]', 'core_core_cia[63:0]']),
 546             'raw_insn_i[31:0]',
 547             'raw_opcode_in[31:0]', 'insn_type', 'dec2.dec2_exc_happened',
 548             ('svp64 decoding', 'closed', [
 549                 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
 550                 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
 551                 'dec2.sv_rm_dec.ptype_in',
 552                 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
 553                 'dstmask[63:0]', 'srcmask[63:0]',
 554                 'dregread[4:0]', 'dinvert',
 555                 'sregread[4:0]', 'sinvert',
 556                 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
 557                 'core.int.pred__ren']),
 558             ('register augmentation', 'dec', 'closed', [
 559                 {'comment': 'v3.0b registers'},
 560                 'dec2.dec_o.RT[4:0]',
 561                 'dec2.dec_a.RA[4:0]',
 562                 'dec2.dec_b.RB[4:0]',
 563                 ('Rdest', [
 564                     'dec2.o_svdec.reg_in[4:0]',
 565                     ('dec2.o_svdec.spec[2:0]', 'bin'),
 566                     'dec2.o_svdec.reg_out[6:0]']),
 567                 ('Rsrc1', [
 568                     'dec2.in1_svdec.reg_in[4:0]',
 569                     ('dec2.in1_svdec.spec[2:0]', 'bin'),
 570                     'dec2.in1_svdec.reg_out[6:0]']),
 571                 ('Rsrc1', [
 572                     'dec2.in2_svdec.reg_in[4:0]',
 573                     ('dec2.in2_svdec.spec[2:0]', 'bin'),
 574                     'dec2.in2_svdec.reg_out[6:0]']),
 575                 {'comment': 'SVP64 registers'},
 576                 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
 577             ]),
 578             {'comment': 'svp64 context'},
 579             'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
 580             'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
 581             'core_core_dststep[6:0]',
 582             {'comment': 'issue and execute'},
 583             'core.core_core_insn_type',
 584             (None, 'dec', [
 585                 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
 586             'issue_i', 'busy_o',
 587             {'comment': 'dmi'},
 588             'dbg.dmi_req_i', 'dbg.dmi_ack_o',
 589             {'comment': 'instruction memory'},
 590             'imem.sram.rdport.memory(0)[63:0]',
 591             {'comment': 'registers'},
 592             # match with soc.regfile.regfiles.IntRegs port names
 593             'core.int.rp_src1.memory(0)[63:0]',
 594             'core.int.rp_src1.memory(1)[63:0]',
 595             'core.int.rp_src1.memory(2)[63:0]',
 596             'core.int.rp_src1.memory(3)[63:0]',
 597             'core.int.rp_src1.memory(4)[63:0]',
 598             'core.int.rp_src1.memory(5)[63:0]',
 599             'core.int.rp_src1.memory(6)[63:0]',
 600             'core.int.rp_src1.memory(7)[63:0]',
 601             'core.int.rp_src1.memory(9)[63:0]',
 602             'core.int.rp_src1.memory(10)[63:0]',
 603             'core.int.rp_src1.memory(13)[63:0]'
 604         ]
 605
 606         # PortInterface module path varies depending on MMU option
 607         if self.microwatt_mmu:
 608             pi_module = 'core.ldst0'
 609         else:
 610             pi_module = 'core.fus.ldst0'
 611
 612         traces += [('ld/st port interface', {'submodule': pi_module}, [
 613             'oper_r__insn_type',
 614             'ldst_port0_is_ld_i',
 615             'ldst_port0_is_st_i',
 616             'ldst_port0_busy_o',
 617             'ldst_port0_addr_i[47:0]',
 618             'ldst_port0_addr_i_ok',
 619             'ldst_port0_addr_ok_o',
 620             'ldst_port0_exc_happened',
 621             'ldst_port0_st_data_i[63:0]',
 622             'ldst_port0_st_data_i_ok',
 623             'ldst_port0_ld_data_o[63:0]',
 624             'ldst_port0_ld_data_o_ok',
 625             'exc_o_happened',
 626             'cancel'
 627         ])]
 628
 629         if self.microwatt_mmu:
 630             traces += [
 631                 {'comment': 'microwatt_mmu'},
 632                 'core.fus.mmu0.alu_mmu0.illegal',
 633                 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
 634                 'core.fus.mmu0.alu_mmu0.mmu.state',
 635                 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
 636                 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
 637                 {'comment': 'wishbone_memory'},
 638                 'core.fus.mmu0.alu_mmu0.dcache.stb',
 639                 'core.fus.mmu0.alu_mmu0.dcache.cyc',
 640                 'core.fus.mmu0.alu_mmu0.dcache.we',
 641                 'core.fus.mmu0.alu_mmu0.dcache.ack',
 642                 'core.fus.mmu0.alu_mmu0.dcache.stall,'
 643             ]
 644
 645         write_gtkw("issuer_simulator.gtkw",
 646                    "issuer_simulator.vcd",
 647                    traces, styles, module='top.issuer')
 648
 649         # add run of instructions
 650         sim.add_sync_process(process)
 651
 652         # optionally, if a wishbone-based ROM is passed in, run that as an
 653         # extra emulated process
 654         if self.rom is not None:
 655             dcache = core.fus.fus["mmu0"].alu.dcache
 656             default_mem = self.rom
 657             sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))
 658
 659         with sim.write_vcd("issuer_simulator.vcd"):
 660             sim.run()