src/soc/simple/test/test_runner.py

   1 """TestRunner class, runs TestIssuer instructions
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6  * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
   7 """
   8 from nmigen import Module, Signal
   9 from nmigen.hdl.xfrm import ResetInserter
  10 from copy import copy
  11
  12 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  13 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  14 from nmutil.sim_tmp_alternative import Simulator, Settle
  15
  16 from openpower.decoder.isa.caller import SVP64State
  17 from openpower.decoder.isa.all import ISA
  18 from openpower.endian import bigendian
  19
  20 from soc.simple.issuer import TestIssuerInternal
  21
  22 from soc.config.test.test_loadstore import TestMemPspec
  23 from soc.simple.test.test_core import (setup_regs, check_regs, check_mem,
  24                                        wait_for_busy_clear,
  25                                        wait_for_busy_hi)
  26 from soc.fu.compunits.test.test_compunit import (setup_tst_memory,
  27                                                  check_sim_memory)
  28 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
  29 from nmutil.util import wrap
  30 from soc.experiment.test.test_mmu_dcache import wb_get
  31 from openpower.test.state import TestState, StateRunner
  32 from openpower.test.runner import TestRunnerBase
  33
  34
  35 def setup_i_memory(imem, startaddr, instructions):
  36     mem = imem
  37     print("insn before, init mem", mem.depth, mem.width, mem,
  38           len(instructions))
  39     for i in range(mem.depth):
  40         yield mem._array[i].eq(0)
  41     yield Settle()
  42     startaddr //= 4  # instructions are 32-bit
  43     if mem.width == 32:
  44         mask = ((1 << 32)-1)
  45         for ins in instructions:
  46             if isinstance(ins, tuple):
  47                 insn, code = ins
  48             else:
  49                 insn, code = ins, ''
  50             insn = insn & 0xffffffff
  51             yield mem._array[startaddr].eq(insn)
  52             yield Settle()
  53             if insn != 0:
  54                 print("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  55             startaddr += 1
  56             startaddr = startaddr & mask
  57         return
  58
  59     # 64 bit
  60     mask = ((1 << 64)-1)
  61     for ins in instructions:
  62         if isinstance(ins, tuple):
  63             insn, code = ins
  64         else:
  65             insn, code = ins, ''
  66         insn = insn & 0xffffffff
  67         msbs = (startaddr >> 1) & mask
  68         val = yield mem._array[msbs]
  69         if insn != 0:
  70             print("before set", hex(4*startaddr),
  71                   hex(msbs), hex(val), hex(insn))
  72         lsb = 1 if (startaddr & 1) else 0
  73         val = (val | (insn << (lsb*32)))
  74         val = val & mask
  75         yield mem._array[msbs].eq(val)
  76         yield Settle()
  77         if insn != 0:
  78             print("after  set", hex(4*startaddr), hex(msbs), hex(val))
  79             print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  80         startaddr += 1
  81         startaddr = startaddr & mask
  82
  83
  84 def set_dmi(dmi, addr, data):
  85     yield dmi.req_i.eq(1)
  86     yield dmi.addr_i.eq(addr)
  87     yield dmi.din.eq(data)
  88     yield dmi.we_i.eq(1)
  89     while True:
  90         ack = yield dmi.ack_o
  91         if ack:
  92             break
  93         yield
  94     yield
  95     yield dmi.req_i.eq(0)
  96     yield dmi.addr_i.eq(0)
  97     yield dmi.din.eq(0)
  98     yield dmi.we_i.eq(0)
  99     yield
 100
 101
 102 def get_dmi(dmi, addr):
 103     yield dmi.req_i.eq(1)
 104     yield dmi.addr_i.eq(addr)
 105     yield dmi.din.eq(0)
 106     yield dmi.we_i.eq(0)
 107     while True:
 108         ack = yield dmi.ack_o
 109         if ack:
 110             break
 111         yield
 112     yield  # wait one
 113     data = yield dmi.dout  # get data after ack valid for 1 cycle
 114     yield dmi.req_i.eq(0)
 115     yield dmi.addr_i.eq(0)
 116     yield dmi.we_i.eq(0)
 117     yield
 118     return data
 119
 120
 121 class HDLRunner(StateRunner):
 122     """HDLRunner:  Implements methods for the setup, preparation, and
 123     running of tests using nmigen HDL simulation.
 124     """
 125     def __init__(self, dut, m, pspec):
 126         super().__init__("hdl", HDLRunner)
 127
 128         self.dut = dut
 129         self.pc_i = Signal(32)
 130         self.svstate_i = Signal(64)
 131
 132         #hard_reset = Signal(reset_less=True)
 133         self.issuer = TestIssuerInternal(pspec)
 134         # use DMI RESET command instead, this does actually work though
 135         #issuer = ResetInserter({'coresync': hard_reset,
 136         #                        'sync': hard_reset})(issuer)
 137         m.submodules.issuer = self.issuer
 138         self.dmi = self.issuer.dbg.dmi
 139
 140         comb = m.d.comb
 141         comb += self.issuer.pc_i.data.eq(self.pc_i)
 142         comb += self.issuer.svstate_i.data.eq(self.svstate_i)
 143
 144     def prepare_for_test(self, test):
 145         self.test = test
 146
 147         # set up bigendian (TODO: don't do this, use MSR)
 148         yield self.issuer.core_bigendian_i.eq(bigendian)
 149         yield Settle()
 150
 151         yield
 152         yield
 153         yield
 154         yield
 155
 156     def setup_during_test(self):
 157         yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 158         yield
 159
 160     def run_test(self, instructions):
 161         """run_hdl_state - runs a TestIssuer nmigen HDL simulation
 162         """
 163
 164         imem = self.issuer.imem._get_memory()
 165         core = self.issuer.core
 166         dmi = self.issuer.dbg.dmi
 167         pdecode2 = self.issuer.pdecode2
 168         l0 = core.l0
 169         hdl_states = []
 170
 171         # establish the TestIssuer context (mem, regs etc)
 172
 173         pc = 0  # start address
 174         counter = 0  # test to pause/start
 175
 176         yield from setup_i_memory(imem, pc, instructions)
 177         yield from setup_tst_memory(l0, self.test.mem)
 178         yield from setup_regs(pdecode2, core, self.test)
 179
 180         # set PC and SVSTATE
 181         yield self.pc_i.eq(pc)
 182         yield self.issuer.pc_i.ok.eq(1)
 183
 184         # copy initial SVSTATE
 185         initial_svstate = copy(self.test.svstate)
 186         if isinstance(initial_svstate, int):
 187             initial_svstate = SVP64State(initial_svstate)
 188         yield self.svstate_i.eq(initial_svstate.value)
 189         yield self.issuer.svstate_i.ok.eq(1)
 190         yield
 191
 192         print("instructions", instructions)
 193
 194         # run the loop of the instructions on the current test
 195         index = (yield self.issuer.cur_state.pc) // 4
 196         while index < len(instructions):
 197             ins, code = instructions[index]
 198
 199             print("hdl instr: 0x{:X}".format(ins & 0xffffffff))
 200             print(index, code)
 201
 202             if counter == 0:
 203                 # start the core
 204                 yield
 205                 yield from set_dmi(dmi, DBGCore.CTRL,
 206                                 1<<DBGCtrl.START)
 207                 yield self.issuer.pc_i.ok.eq(0) # no change PC after this
 208                 yield self.issuer.svstate_i.ok.eq(0) # ditto
 209                 yield
 210                 yield
 211
 212             counter = counter + 1
 213
 214             # wait until executed
 215             while not (yield self.issuer.insn_done):
 216                 yield
 217
 218             yield Settle()
 219
 220             index = (yield self.issuer.cur_state.pc) // 4
 221
 222             terminated = yield self.issuer.dbg.terminated_o
 223             print("terminated", terminated)
 224
 225             if index < len(instructions):
 226                 # Get HDL mem and state
 227                 state = yield from TestState("hdl", core, self.dut,
 228                                             code)
 229                 hdl_states.append(state)
 230
 231             if index >= len(instructions):
 232                 print ("index over, send dmi stop")
 233                 # stop at end
 234                 yield from set_dmi(dmi, DBGCore.CTRL,
 235                                 1<<DBGCtrl.STOP)
 236                 yield
 237                 yield
 238
 239             terminated = yield self.issuer.dbg.terminated_o
 240             print("terminated(2)", terminated)
 241             if terminated:
 242                 break
 243
 244         return hdl_states
 245
 246     def end_test(self):
 247         yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 248         yield
 249         yield
 250
 251         # TODO, here is where the static (expected) results
 252         # can be checked: register check (TODO, memory check)
 253         # see https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
 254         # yield from check_regs(self, sim, core, test, code,
 255         #                       >>>expected_data<<<)
 256
 257         # get CR
 258         cr = yield from get_dmi(self.dmi, DBGCore.CR)
 259         print("after test %s cr value %x" % (self.test.name, cr))
 260
 261         # get XER
 262         xer = yield from get_dmi(self.dmi, DBGCore.XER)
 263         print("after test %s XER value %x" % (self.test.name, xer))
 264
 265         # test of dmi reg get
 266         for int_reg in range(32):
 267             yield from set_dmi(self.dmi, DBGCore.GSPR_IDX, int_reg)
 268             value = yield from get_dmi(self.dmi, DBGCore.GSPR_DATA)
 269
 270             print("after test %s reg %2d value %x" %
 271             (self.test.name, int_reg, value))
 272
 273         # pull a reset
 274         yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
 275         yield
 276
 277
 278 class TestRunner(TestRunnerBase):
 279     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
 280                         svp64=True, run_hdl=True, run_sim=True):
 281         if run_hdl:
 282             run_hdl = HDLRunner
 283         super().__init__(tst_data, microwatt_mmu=microwatt_mmu,
 284                         rom=rom,
 285                         svp64=svp64, run_hdl=run_hdl, run_sim=run_sim)
 286