src/soc/simple/test/test_runner.py

   1 """TestRunner class, runs TestIssuer instructions
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat, ClockSignal
   8
   9 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  10 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  11 from nmutil.sim_tmp_alternative import Simulator, Settle
  12
  13 from nmutil.formaltest import FHDLTestCase
  14 from nmutil.gtkw import write_gtkw
  15 from nmigen.cli import rtlil
  16 from soc.decoder.isa.caller import special_sprs, SVP64State
  17 from soc.decoder.isa.all import ISA
  18 from soc.config.endian import bigendian
  19
  20 from soc.decoder.power_decoder import create_pdecode
  21 from soc.decoder.power_decoder2 import PowerDecode2
  22 from soc.regfile.regfiles import StateRegs
  23
  24 from soc.simple.issuer import TestIssuerInternal
  25
  26 from soc.config.test.test_loadstore import TestMemPspec
  27 from soc.simple.test.test_core import (setup_regs, check_regs,
  28                                        wait_for_busy_clear,
  29                                        wait_for_busy_hi)
  30 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  31                                                  check_sim_memory)
  32 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
  33 from nmutil.util import wrap
  34 from soc.experiment.test.test_mmu_dcache import wb_get
  35
  36
  37 def setup_i_memory(imem, startaddr, instructions):
  38     mem = imem
  39     print("insn before, init mem", mem.depth, mem.width, mem,
  40           len(instructions))
  41     for i in range(mem.depth):
  42         yield mem._array[i].eq(0)
  43     yield Settle()
  44     startaddr //= 4  # instructions are 32-bit
  45     if mem.width == 32:
  46         mask = ((1 << 32)-1)
  47         for ins in instructions:
  48             if isinstance(ins, tuple):
  49                 insn, code = ins
  50             else:
  51                 insn, code = ins, ''
  52             insn = insn & 0xffffffff
  53             yield mem._array[startaddr].eq(insn)
  54             yield Settle()
  55             if insn != 0:
  56                 print("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  57             startaddr += 1
  58             startaddr = startaddr & mask
  59         return
  60
  61     # 64 bit
  62     mask = ((1 << 64)-1)
  63     for ins in instructions:
  64         if isinstance(ins, tuple):
  65             insn, code = ins
  66         else:
  67             insn, code = ins, ''
  68         insn = insn & 0xffffffff
  69         msbs = (startaddr >> 1) & mask
  70         val = yield mem._array[msbs]
  71         if insn != 0:
  72             print("before set", hex(4*startaddr),
  73                   hex(msbs), hex(val), hex(insn))
  74         lsb = 1 if (startaddr & 1) else 0
  75         val = (val | (insn << (lsb*32)))
  76         val = val & mask
  77         yield mem._array[msbs].eq(val)
  78         yield Settle()
  79         if insn != 0:
  80             print("after  set", hex(4*startaddr), hex(msbs), hex(val))
  81             print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  82         startaddr += 1
  83         startaddr = startaddr & mask
  84
  85
  86 def set_dmi(dmi, addr, data):
  87     yield dmi.req_i.eq(1)
  88     yield dmi.addr_i.eq(addr)
  89     yield dmi.din.eq(data)
  90     yield dmi.we_i.eq(1)
  91     while True:
  92         ack = yield dmi.ack_o
  93         if ack:
  94             break
  95         yield
  96     yield
  97     yield dmi.req_i.eq(0)
  98     yield dmi.addr_i.eq(0)
  99     yield dmi.din.eq(0)
 100     yield dmi.we_i.eq(0)
 101     yield
 102
 103
 104 def get_dmi(dmi, addr):
 105     yield dmi.req_i.eq(1)
 106     yield dmi.addr_i.eq(addr)
 107     yield dmi.din.eq(0)
 108     yield dmi.we_i.eq(0)
 109     while True:
 110         ack = yield dmi.ack_o
 111         if ack:
 112             break
 113         yield
 114     yield  # wait one
 115     data = yield dmi.dout  # get data after ack valid for 1 cycle
 116     yield dmi.req_i.eq(0)
 117     yield dmi.addr_i.eq(0)
 118     yield dmi.we_i.eq(0)
 119     yield
 120     return data
 121
 122
 123 class TestRunner(FHDLTestCase):
 124     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
 125                         svp64=True):
 126         super().__init__("run_all")
 127         self.test_data = tst_data
 128         self.microwatt_mmu = microwatt_mmu
 129         self.rom = rom
 130         self.svp64 = svp64
 131
 132     def run_all(self):
 133         m = Module()
 134         comb = m.d.comb
 135         pc_i = Signal(32)
 136         svstate_i = Signal(32)
 137
 138         pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
 139                              imem_ifacetype='test_bare_wb',
 140                              addr_wid=48,
 141                              mask_wid=8,
 142                              imem_reg_wid=64,
 143                              # wb_data_width=32,
 144                              use_pll=False,
 145                              nocore=False,
 146                              xics=False,
 147                              gpio=False,
 148                              svp64=self.svp64,
 149                              mmu=self.microwatt_mmu,
 150                              reg_wid=64)
 151         m.submodules.issuer = issuer = TestIssuerInternal(pspec)
 152         imem = issuer.imem._get_memory()
 153         core = issuer.core
 154         dmi = issuer.dbg.dmi
 155         pdecode2 = issuer.pdecode2
 156         l0 = core.l0
 157
 158         # copy of the decoder for simulator
 159         simdec = create_pdecode()
 160         simdec2 = PowerDecode2(simdec)
 161         m.submodules.simdec2 = simdec2  # pain in the neck
 162
 163         # run core clock at same rate as test clock
 164         intclk = ClockSignal("coresync")
 165         comb += intclk.eq(ClockSignal())
 166
 167         comb += issuer.pc_i.data.eq(pc_i)
 168         comb += issuer.svstate_i.data.eq(svstate_i)
 169
 170         # nmigen Simulation
 171         sim = Simulator(m)
 172         sim.add_clock(1e-6)
 173
 174         def process():
 175
 176             # start in stopped
 177             yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 178             yield
 179             yield
 180
 181             # get each test, completely reset the core, and run it
 182
 183             for test in self.test_data:
 184
 185                 # pull a reset
 186                 # yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
 187
 188                 # set up bigendian (TODO: don't do this, use MSR)
 189                 yield issuer.core_bigendian_i.eq(bigendian)
 190                 yield Settle()
 191
 192                 yield
 193                 yield
 194                 yield
 195                 yield
 196
 197                 print(test.name)
 198                 program = test.program
 199                 self.subTest(test.name)
 200                 print("regs", test.regs)
 201                 print("sprs", test.sprs)
 202                 print("cr", test.cr)
 203                 print("mem", test.mem)
 204                 print("msr", test.msr)
 205                 print("assem", program.assembly)
 206                 gen = list(program.generate_instructions())
 207                 insncode = program.assembly.splitlines()
 208                 instructions = list(zip(gen, insncode))
 209
 210                 # set up the Simulator (which must track TestIssuer exactly)
 211                 sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
 212                           test.msr,
 213                           initial_insns=gen, respect_pc=True,
 214                           disassembly=insncode,
 215                           bigendian=bigendian,
 216                           initial_svstate=test.svstate)
 217
 218                 # establish the TestIssuer context (mem, regs etc)
 219
 220                 pc = 0  # start address
 221                 counter = 0  # test to pause/start
 222
 223                 yield from setup_i_memory(imem, pc, instructions)
 224                 yield from setup_test_memory(l0, sim)
 225                 yield from setup_regs(pdecode2, core, test)
 226
 227                 # set PC and SVSTATE
 228                 yield pc_i.eq(pc)
 229                 yield issuer.pc_i.ok.eq(1)
 230
 231                 initial_svstate = test.svstate
 232                 if isinstance(initial_svstate, int):
 233                     initial_svstate = SVP64State(initial_svstate)
 234                 yield svstate_i.eq(initial_svstate.spr.value)
 235                 yield issuer.svstate_i.ok.eq(1)
 236                 yield
 237
 238                 print("instructions", instructions)
 239
 240                 # run the loop of the instructions on the current test
 241                 index = sim.pc.CIA.value//4
 242                 while index < len(instructions):
 243                     ins, code = instructions[index]
 244
 245                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 246                     print(index, code)
 247
 248                     if counter == 0:
 249                         # start the core
 250                         yield
 251                         yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.START)
 252                         yield issuer.pc_i.ok.eq(0)  # no change PC after this
 253                         yield issuer.svstate_i.ok.eq(0) # ditto
 254                         yield
 255                         yield
 256
 257                     counter = counter + 1
 258
 259                     # wait until executed
 260                     yield from wait_for_busy_hi(core)
 261                     yield from wait_for_busy_clear(core)
 262
 263                     # set up simulated instruction (in simdec2)
 264                     try:
 265                         yield from sim.setup_one()
 266                     except KeyError:  # indicates instruction not in imem: stop
 267                         break
 268                     yield Settle()
 269
 270                     # call simulated operation
 271                     print("sim", code)
 272                     yield from sim.execute_one()
 273                     yield Settle()
 274                     index = sim.pc.CIA.value//4
 275
 276                     terminated = yield issuer.dbg.terminated_o
 277                     print("terminated", terminated)
 278
 279                     if index >= len(instructions):
 280                         print ("index over, send dmi stop")
 281                         # stop at end
 282                         yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 283                         yield
 284                         yield
 285
 286                     # wait one cycle for registers to settle
 287                     yield
 288
 289                     # register check
 290                     yield from check_regs(self, sim, core, test, code)
 291
 292                     # Memory check
 293                     yield from check_sim_memory(self, l0, sim, code)
 294
 295                     terminated = yield issuer.dbg.terminated_o
 296                     print("terminated(2)", terminated)
 297                     if terminated:
 298                         break
 299
 300                 # stop at end
 301                 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 302                 yield
 303                 yield
 304
 305                 # get CR
 306                 cr = yield from get_dmi(dmi, DBGCore.CR)
 307                 print("after test %s cr value %x" % (test.name, cr))
 308
 309                 # get XER
 310                 xer = yield from get_dmi(dmi, DBGCore.XER)
 311                 print("after test %s XER value %x" % (test.name, xer))
 312
 313                 # test of dmi reg get
 314                 for int_reg in range(32):
 315                     yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg)
 316                     value = yield from get_dmi(dmi, DBGCore.GSPR_DATA)
 317
 318                     print("after test %s reg %2d value %x" %
 319                           (test.name, int_reg, value))
 320
 321         styles = {
 322             'dec': {'base': 'dec'},
 323             'bin': {'base': 'bin'},
 324             'closed': {'closed': True}
 325         }
 326
 327         traces = [
 328             'clk',
 329             {'comment': 'state machines'},
 330             'fetch_pc_valid_i', 'fetch_pc_ready_o',
 331             'fetch_fsm_state',
 332             'fetch_insn_valid_o', 'fetch_insn_ready_i',
 333             'issue_fsm_state',
 334             'exec_insn_valid_i', 'exec_insn_ready_o',
 335             'exec_fsm_state',
 336             'exec_pc_valid_o', 'exec_pc_ready_i',
 337             {'comment': 'fetch and decode'},
 338             'cia[63:0]', 'nia[63:0]', 'pc[63:0]', 'raw_insn_i[31:0]',
 339             'raw_opcode_in[31:0]', 'insn_type',
 340             {'comment': 'svp64 decoding'},
 341             'svp64_rm[23:0]',
 342             ('dec2.extra[8:0]', 'bin'),
 343             ('register augmentation', 'dec', 'closed', [
 344                 {'comment': 'v3.0b registers'},
 345                 'dec2.dec_o.RT[4:0]',
 346                 'dec2.dec_a.RA[4:0]',
 347                 'dec2.dec_b.RB[4:0]',
 348                 ('Rdest', [
 349                     'dec2.o_svdec.reg_in[4:0]',
 350                     ('dec2.o_svdec.spec[2:0]', 'bin'),
 351                     'dec2.o_svdec.reg_out[6:0]']),
 352                 ('Rsrc1', [
 353                     'dec2.in1_svdec.reg_in[4:0]',
 354                     ('dec2.in1_svdec.spec[2:0]', 'bin'),
 355                     'dec2.in1_svdec.reg_out[6:0]']),
 356                 ('Rsrc1', [
 357                     'dec2.in2_svdec.reg_in[4:0]',
 358                     ('dec2.in2_svdec.spec[2:0]', 'bin'),
 359                     'dec2.in2_svdec.reg_out[6:0]']),
 360                 {'comment': 'SVP64 registers'},
 361                 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
 362             ]),
 363             {'comment': 'svp64 context'},
 364             'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
 365             'core_core_srcstep[6:0]', 'core_core_dststep[6:0]',
 366             {'comment': 'issue and execute'},
 367             'core.core_core_insn_type',
 368             (None, 'dec', [
 369                 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
 370             'issue_i', 'busy_o',
 371             {'comment': 'dmi'},
 372             'dbg.dmi_req_i', 'dbg.dmi_ack_o',
 373             {'comment': 'instruction memory'},
 374             'imem.sram.rdport.memory(0)[63:0]',
 375             {'comment': 'registers'},
 376             'core.int.rp_src1.memory(0)[63:0]',
 377             'core.int.rp_src1.memory(1)[63:0]',
 378             'core.int.rp_src1.memory(2)[63:0]',
 379             'core.int.rp_src1.memory(3)[63:0]',
 380             'core.int.rp_src1.memory(4)[63:0]',
 381             'core.int.rp_src1.memory(5)[63:0]',
 382             'core.int.rp_src1.memory(6)[63:0]',
 383             'core.int.rp_src1.memory(7)[63:0]',
 384             'core.int.rp_src1.memory(9)[63:0]',
 385             'core.int.rp_src1.memory(10)[63:0]',
 386             'core.int.rp_src1.memory(13)[63:0]',
 387         ]
 388
 389         if self.microwatt_mmu:
 390             traces += [
 391                 {'comment': 'microwatt_mmu'},
 392                 'core.fus.mmu0.alu_mmu0.illegal',
 393                 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
 394                 'core.fus.mmu0.alu_mmu0.mmu.state',
 395                 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
 396                 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
 397                 {'comment': 'wishbone_memory'},
 398                 'core.fus.mmu0.alu_mmu0.dcache.stb',
 399                 'core.fus.mmu0.alu_mmu0.dcache.cyc',
 400                 'core.fus.mmu0.alu_mmu0.dcache.we',
 401                 'core.fus.mmu0.alu_mmu0.dcache.ack',
 402                 'core.fus.mmu0.alu_mmu0.dcache.stall,'
 403             ]
 404
 405         write_gtkw("issuer_simulator.gtkw",
 406                    "issuer_simulator.vcd",
 407                    traces, styles, module='top.issuer')
 408
 409         # add run of instructions
 410         sim.add_sync_process(process)
 411
 412         # optionally, if a wishbone-based ROM is passed in, run that as an
 413         # extra emulated process
 414         if self.rom is not None:
 415             dcache = core.fus.fus["mmu0"].alu.dcache
 416             default_mem = self.rom
 417             sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))
 418
 419         with sim.write_vcd("issuer_simulator.vcd"):
 420             sim.run()