1 """TestRunner class, runs TestIssuer instructions
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
6 * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
8 from nmigen
import Module
, Signal
, Cat
, ClockSignal
9 from nmigen
.hdl
.xfrm
import ResetInserter
12 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
13 # Also, check out the cxxsim nmigen branch, and latest yosys from git
14 from nmutil
.sim_tmp_alternative
import Simulator
, Settle
16 from nmutil
.formaltest
import FHDLTestCase
17 from nmutil
.gtkw
import write_gtkw
18 from nmigen
.cli
import rtlil
19 from openpower
.decoder
.isa
.caller
import special_sprs
, SVP64State
20 from openpower
.decoder
.isa
.all
import ISA
21 from openpower
.endian
import bigendian
23 from openpower
.decoder
.power_decoder
import create_pdecode
24 from openpower
.decoder
.power_decoder2
import PowerDecode2
25 from soc
.regfile
.regfiles
import StateRegs
27 from soc
.simple
.issuer
import TestIssuerInternal
29 from soc
.config
.test
.test_loadstore
import TestMemPspec
30 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
, check_mem
,
33 from soc
.fu
.compunits
.test
.test_compunit
import (setup_tst_memory
,
35 from soc
.debug
.dmi
import DBGCore
, DBGCtrl
, DBGStat
36 from nmutil
.util
import wrap
37 from soc
.experiment
.test
.test_mmu_dcache
import wb_get
38 from openpower
.test
.state
import TestState
, StateRunner
41 def setup_i_memory(imem
, startaddr
, instructions
):
43 print("insn before, init mem", mem
.depth
, mem
.width
, mem
,
45 for i
in range(mem
.depth
):
46 yield mem
._array
[i
].eq(0)
48 startaddr
//= 4 # instructions are 32-bit
51 for ins
in instructions
:
52 if isinstance(ins
, tuple):
56 insn
= insn
& 0xffffffff
57 yield mem
._array
[startaddr
].eq(insn
)
60 print("instr: %06x 0x%x %s" % (4*startaddr
, insn
, code
))
62 startaddr
= startaddr
& mask
67 for ins
in instructions
:
68 if isinstance(ins
, tuple):
72 insn
= insn
& 0xffffffff
73 msbs
= (startaddr
>> 1) & mask
74 val
= yield mem
._array
[msbs
]
76 print("before set", hex(4*startaddr
),
77 hex(msbs
), hex(val
), hex(insn
))
78 lsb
= 1 if (startaddr
& 1) else 0
79 val
= (val |
(insn
<< (lsb
*32)))
81 yield mem
._array
[msbs
].eq(val
)
84 print("after set", hex(4*startaddr
), hex(msbs
), hex(val
))
85 print("instr: %06x 0x%x %s %08x" % (4*startaddr
, insn
, code
, val
))
87 startaddr
= startaddr
& mask
90 def set_dmi(dmi
, addr
, data
):
92 yield dmi
.addr_i
.eq(addr
)
93 yield dmi
.din
.eq(data
)
101 yield dmi
.req_i
.eq(0)
102 yield dmi
.addr_i
.eq(0)
108 def get_dmi(dmi
, addr
):
109 yield dmi
.req_i
.eq(1)
110 yield dmi
.addr_i
.eq(addr
)
114 ack
= yield dmi
.ack_o
119 data
= yield dmi
.dout
# get data after ack valid for 1 cycle
120 yield dmi
.req_i
.eq(0)
121 yield dmi
.addr_i
.eq(0)
127 def run_hdl_state(dut
, test
, issuer
, pc_i
, svstate_i
, instructions
):
128 """run_hdl_state - runs a TestIssuer nmigen HDL simulation
131 imem
= issuer
.imem
._get
_memory
()
134 pdecode2
= issuer
.pdecode2
138 # establish the TestIssuer context (mem, regs etc)
140 pc
= 0 # start address
141 counter
= 0 # test to pause/start
143 yield from setup_i_memory(imem
, pc
, instructions
)
144 yield from setup_tst_memory(l0
, test
.mem
)
145 yield from setup_regs(pdecode2
, core
, test
)
149 yield issuer
.pc_i
.ok
.eq(1)
151 # copy initial SVSTATE
152 initial_svstate
= copy(test
.svstate
)
153 if isinstance(initial_svstate
, int):
154 initial_svstate
= SVP64State(initial_svstate
)
155 yield svstate_i
.eq(initial_svstate
.value
)
156 yield issuer
.svstate_i
.ok
.eq(1)
159 print("instructions", instructions
)
161 # run the loop of the instructions on the current test
162 index
= (yield issuer
.cur_state
.pc
) // 4
163 while index
< len(instructions
):
164 ins
, code
= instructions
[index
]
166 print("hdl instr: 0x{:X}".format(ins
& 0xffffffff))
172 yield from set_dmi(dmi
, DBGCore
.CTRL
,
174 yield issuer
.pc_i
.ok
.eq(0) # no change PC after this
175 yield issuer
.svstate_i
.ok
.eq(0) # ditto
179 counter
= counter
+ 1
181 # wait until executed
182 while not (yield issuer
.insn_done
):
187 index
= (yield issuer
.cur_state
.pc
) // 4
189 terminated
= yield issuer
.dbg
.terminated_o
190 print("terminated", terminated
)
192 if index
< len(instructions
):
193 # Get HDL mem and state
194 state
= yield from TestState("hdl", core
, dut
,
196 hdl_states
.append(state
)
198 if index
>= len(instructions
):
199 print ("index over, send dmi stop")
201 yield from set_dmi(dmi
, DBGCore
.CTRL
,
206 terminated
= yield issuer
.dbg
.terminated_o
207 print("terminated(2)", terminated
)
214 def run_sim_state(dut
, test
, simdec2
, instructions
, gen
, insncode
):
215 """run_sim_state - runs an ISACaller simulation
220 # set up the Simulator (which must track TestIssuer exactly)
221 sim
= ISA(simdec2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
223 initial_insns
=gen
, respect_pc
=True,
224 disassembly
=insncode
,
226 initial_svstate
=test
.svstate
)
228 # run the loop of the instructions on the current test
229 index
= sim
.pc
.CIA
.value
//4
230 while index
< len(instructions
):
231 ins
, code
= instructions
[index
]
233 print("sim instr: 0x{:X}".format(ins
& 0xffffffff))
236 # set up simulated instruction (in simdec2)
238 yield from sim
.setup_one()
239 except KeyError: # instruction not in imem: stop
243 # call simulated operation
245 yield from sim
.execute_one()
247 index
= sim
.pc
.CIA
.value
//4
249 # get sim register and memory TestState, add to list
250 state
= yield from TestState("sim", sim
, dut
, code
)
251 sim_states
.append(state
)
256 class SimRunner(StateRunner
):
257 def __init__(self
, dut
, m
, pspec
):
260 regreduce_en
= pspec
.regreduce_en
== True
261 self
.simdec2
= simdec2
= PowerDecode2(None, regreduce_en
=regreduce_en
)
262 m
.submodules
.simdec2
= simdec2
# pain in the neck
264 def prepare_for_test(self
, test
):
267 def run_test(self
, instructions
, gen
, insncode
):
268 sim_states
= yield from run_sim_state(self
.dut
, self
.test
,
275 class HDLRunner(StateRunner
):
276 def __init__(self
, dut
, m
, pspec
):
278 #hard_reset = Signal(reset_less=True)
279 self
.issuer
= TestIssuerInternal(pspec
)
280 # use DMI RESET command instead, this does actually work though
281 #issuer = ResetInserter({'coresync': hard_reset,
282 # 'sync': hard_reset})(issuer)
283 m
.submodules
.issuer
= self
.issuer
284 self
.dmi
= self
.issuer
.dbg
.dmi
287 class TestRunner(FHDLTestCase
):
288 def __init__(self
, tst_data
, microwatt_mmu
=False, rom
=None,
289 svp64
=True, run_hdl
=True, run_sim
=True):
290 super().__init
__("run_all")
291 self
.test_data
= tst_data
292 self
.microwatt_mmu
= microwatt_mmu
295 self
.run_hdl
= run_hdl
296 self
.run_sim
= run_sim
301 if self
.microwatt_mmu
:
302 ldst_ifacetype
= 'test_mmu_cache_wb'
304 ldst_ifacetype
= 'test_bare_wb'
305 imem_ifacetype
= 'test_bare_wb'
307 pspec
= TestMemPspec(ldst_ifacetype
=ldst_ifacetype
,
308 imem_ifacetype
=imem_ifacetype
,
319 mmu
=self
.microwatt_mmu
,
322 ###### SETUP PHASE #######
323 # StateRunner.setup_for_test()
326 hdlrun
= HDLRunner(self
, m
, pspec
)
329 simrun
= SimRunner(self
, m
, pspec
)
331 # run core clock at same rate as test clock
332 intclk
= ClockSignal("coresync")
333 comb
+= intclk
.eq(ClockSignal())
338 svstate_i
= Signal(64)
340 comb
+= hdlrun
.issuer
.pc_i
.data
.eq(pc_i
)
341 comb
+= hdlrun
.issuer
.svstate_i
.data
.eq(svstate_i
)
343 # nmigen Simulation - everything runs around this, so it
344 # still has to be created.
350 ###### PREPARATION PHASE AT START OF RUNNING #######
351 # StateRunner.setup_during_test()
355 yield from set_dmi(hdlrun
.dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
358 # get each test, completely reset the core, and run it
360 for test
in self
.test_data
:
362 with self
.subTest(test
.name
):
364 ###### PREPARATION PHASE AT START OF TEST #######
365 # StateRunner.prepare_for_test()
368 simrun
.prepare_for_test(test
)
371 # set up bigendian (TODO: don't do this, use MSR)
372 yield hdlrun
.issuer
.core_bigendian_i
.eq(bigendian
)
381 program
= test
.program
382 print("regs", test
.regs
)
383 print("sprs", test
.sprs
)
385 print("mem", test
.mem
)
386 print("msr", test
.msr
)
387 print("assem", program
.assembly
)
388 gen
= list(program
.generate_instructions())
389 insncode
= program
.assembly
.splitlines()
390 instructions
= list(zip(gen
, insncode
))
392 ###### RUNNING OF EACH TEST #######
393 # StateRunner.step_test()
395 # Run two tests (TODO, move these to functions)
396 # * first the Simulator, collate a batch of results
397 # * then the HDL, likewise
398 # (actually, the other way round because running
399 # Simulator somehow modifies the test state!)
400 # * finally, compare all the results
406 hdl_states
= yield from run_hdl_state(self
, test
,
416 sim_states
= yield from simrun
.run_test(
420 ###### COMPARING THE TESTS #######
427 last_sim
= copy(sim_states
[-1])
429 last_sim
= copy(hdl_states
[-1])
431 last_sim
= None # err what are you doing??
433 if self
.run_hdl
and self
.run_sim
:
434 for simstate
, hdlstate
in zip(sim_states
, hdl_states
):
435 simstate
.compare(hdlstate
) # register check
436 simstate
.compare_mem(hdlstate
) # memory check
440 for state
in hdl_states
:
445 for state
in sim_states
:
448 # compare against expected results
449 if test
.expected
is not None:
450 # have to put these in manually
451 test
.expected
.to_test
= test
.expected
452 test
.expected
.dut
= self
453 test
.expected
.state_type
= "expected"
454 test
.expected
.code
= 0
455 # do actual comparison, against last item
456 last_sim
.compare(test
.expected
)
458 if self
.run_hdl
and self
.run_sim
:
459 self
.assertTrue(len(hdl_states
) == len(sim_states
),
460 "number of instructions run not the same")
462 ###### END OF A TEST #######
463 # StateRunner.end_test()
467 yield from set_dmi(hdlrun
.dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
471 # TODO, here is where the static (expected) results
472 # can be checked: register check (TODO, memory check)
473 # see https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
474 # yield from check_regs(self, sim, core, test, code,
475 # >>>expected_data<<<)
478 cr
= yield from get_dmi(hdlrun
.dmi
, DBGCore
.CR
)
479 print("after test %s cr value %x" % (test
.name
, cr
))
482 xer
= yield from get_dmi(hdlrun
.dmi
, DBGCore
.XER
)
483 print("after test %s XER value %x" % (test
.name
, xer
))
485 # test of dmi reg get
486 for int_reg
in range(32):
487 yield from set_dmi(hdlrun
.dmi
, DBGCore
.GSPR_IDX
, int_reg
)
488 value
= yield from get_dmi(hdlrun
.dmi
, DBGCore
.GSPR_DATA
)
490 print("after test %s reg %2d value %x" %
491 (test
.name
, int_reg
, value
))
494 yield from set_dmi(hdlrun
.dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.RESET
)
497 ###### END OF EVERYTHING (but none needs doing, still call fn) #######
498 # StateRunner.cleanup()
501 'dec': {'base': 'dec'},
502 'bin': {'base': 'bin'},
503 'closed': {'closed': True}
508 ('state machines', 'closed', [
509 'fetch_pc_i_valid', 'fetch_pc_o_ready',
511 'fetch_insn_o_valid', 'fetch_insn_i_ready',
512 'pred_insn_i_valid', 'pred_insn_o_ready',
513 'fetch_predicate_state',
514 'pred_mask_o_valid', 'pred_mask_i_ready',
516 'exec_insn_i_valid', 'exec_insn_o_ready',
518 'exec_pc_o_valid', 'exec_pc_i_ready',
519 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
520 'is_last', 'dec2.no_out_vec']),
521 {'comment': 'fetch and decode'},
523 'cia[63:0]', 'nia[63:0]', 'pc[63:0]',
524 'cur_pc[63:0]', 'core_core_cia[63:0]']),
526 'raw_opcode_in[31:0]', 'insn_type', 'dec2.dec2_exc_happened',
527 ('svp64 decoding', 'closed', [
528 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
529 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
530 'dec2.sv_rm_dec.ptype_in',
531 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
532 'dstmask[63:0]', 'srcmask[63:0]',
533 'dregread[4:0]', 'dinvert',
534 'sregread[4:0]', 'sinvert',
535 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
536 'core.int.pred__ren']),
537 ('register augmentation', 'dec', 'closed', [
538 {'comment': 'v3.0b registers'},
539 'dec2.dec_o.RT[4:0]',
540 'dec2.dec_a.RA[4:0]',
541 'dec2.dec_b.RB[4:0]',
543 'dec2.o_svdec.reg_in[4:0]',
544 ('dec2.o_svdec.spec[2:0]', 'bin'),
545 'dec2.o_svdec.reg_out[6:0]']),
547 'dec2.in1_svdec.reg_in[4:0]',
548 ('dec2.in1_svdec.spec[2:0]', 'bin'),
549 'dec2.in1_svdec.reg_out[6:0]']),
551 'dec2.in2_svdec.reg_in[4:0]',
552 ('dec2.in2_svdec.spec[2:0]', 'bin'),
553 'dec2.in2_svdec.reg_out[6:0]']),
554 {'comment': 'SVP64 registers'},
555 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
557 {'comment': 'svp64 context'},
558 'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
559 'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
560 'core_core_dststep[6:0]',
561 {'comment': 'issue and execute'},
562 'core.core_core_insn_type',
564 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
567 'dbg.dmi_req_i', 'dbg.dmi_ack_o',
568 {'comment': 'instruction memory'},
569 'imem.sram.rdport.memory(0)[63:0]',
570 {'comment': 'registers'},
571 # match with soc.regfile.regfiles.IntRegs port names
572 'core.int.rp_src1.memory(0)[63:0]',
573 'core.int.rp_src1.memory(1)[63:0]',
574 'core.int.rp_src1.memory(2)[63:0]',
575 'core.int.rp_src1.memory(3)[63:0]',
576 'core.int.rp_src1.memory(4)[63:0]',
577 'core.int.rp_src1.memory(5)[63:0]',
578 'core.int.rp_src1.memory(6)[63:0]',
579 'core.int.rp_src1.memory(7)[63:0]',
580 'core.int.rp_src1.memory(9)[63:0]',
581 'core.int.rp_src1.memory(10)[63:0]',
582 'core.int.rp_src1.memory(13)[63:0]'
585 # PortInterface module path varies depending on MMU option
586 if self
.microwatt_mmu
:
587 pi_module
= 'core.ldst0'
589 pi_module
= 'core.fus.ldst0'
591 traces
+= [('ld/st port interface', {'submodule': pi_module
}, [
593 'ldst_port0_is_ld_i',
594 'ldst_port0_is_st_i',
596 'ldst_port0_addr_i[47:0]',
597 'ldst_port0_addr_i_ok',
598 'ldst_port0_addr_ok_o',
599 'ldst_port0_exc_happened',
600 'ldst_port0_st_data_i[63:0]',
601 'ldst_port0_st_data_i_ok',
602 'ldst_port0_ld_data_o[63:0]',
603 'ldst_port0_ld_data_o_ok',
608 if self
.microwatt_mmu
:
610 {'comment': 'microwatt_mmu'},
611 'core.fus.mmu0.alu_mmu0.illegal',
612 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
613 'core.fus.mmu0.alu_mmu0.mmu.state',
614 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
615 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
616 {'comment': 'wishbone_memory'},
617 'core.fus.mmu0.alu_mmu0.dcache.stb',
618 'core.fus.mmu0.alu_mmu0.dcache.cyc',
619 'core.fus.mmu0.alu_mmu0.dcache.we',
620 'core.fus.mmu0.alu_mmu0.dcache.ack',
621 'core.fus.mmu0.alu_mmu0.dcache.stall,'
624 write_gtkw("issuer_simulator.gtkw",
625 "issuer_simulator.vcd",
626 traces
, styles
, module
='top.issuer')
628 # add run of instructions
629 sim
.add_sync_process(process
)
631 # optionally, if a wishbone-based ROM is passed in, run that as an
632 # extra emulated process
633 if self
.rom
is not None:
634 dcache
= core
.fus
.fus
["mmu0"].alu
.dcache
635 default_mem
= self
.rom
636 sim
.add_sync_process(wrap(wb_get(dcache
, default_mem
, "DCACHE")))
638 with sim
.write_vcd("issuer_simulator.vcd"):