3 This module implements the creation, inspection and comparison
4 of test states for TestIssuer HDL
8 from openpower
.decoder
.power_enums
import XER_bits
9 from openpower
.util
import log
10 from openpower
.test
.state
import (State
, state_add
, state_factory
,
12 from soc
.fu
.compunits
.test
.test_compunit
import get_l0_mem
14 class HDLState(State
):
15 def __init__(self
, core
):
19 def get_intregs(self
):
22 if self
.core
.regs
.int.unary
:
23 rval
= yield self
.core
.regs
.int.regs
[i
].reg
25 rval
= yield self
.core
.regs
.int.memory
._array
[i
]
26 self
.intregs
.append(rval
)
27 log("class hdl int regs", list(map(hex, self
.intregs
)))
32 rval
= yield self
.core
.regs
.cr
.regs
[i
].reg
33 self
.crregs
.append(rval
)
34 log("class hdl cr regs", list(map(hex, self
.crregs
)))
38 self
.xr
= self
.core
.regs
.xer
39 self
.so
= yield self
.xr
.regs
[self
.xr
.SO
].reg
40 self
.ov
= yield self
.xr
.regs
[self
.xr
.OV
].reg
41 self
.ca
= yield self
.xr
.regs
[self
.xr
.CA
].reg
42 self
.xregs
.extend((self
.so
, self
.ov
, self
.ca
))
43 log("class hdl xregs", list(map(hex, self
.xregs
)))
47 self
.state
= self
.core
.regs
.state
48 self
.pc
= yield self
.state
.r_ports
['cia'].o_data
49 self
.pcl
.append(self
.pc
)
50 log("class hdl pc", hex(self
.pc
))
53 # get the underlying HDL-simulated memory from the L0CacheBuffer
54 hdlmem
= get_l0_mem(self
.core
.l0
)
56 for i
in range(hdlmem
.depth
):
57 value
= yield hdlmem
._array
[i
] # should not really do this
58 self
.mem
.append(((i
*8), value
))
61 # add to State Factory
62 state_add('hdl', HDLState
)