src/soc/simple/test/teststate.py

   1 from openpower.decoder.power_enums import XER_bits
   2
   3
   4 class SimState:
   5     def __init__(self, sim):
   6         self.sim = sim
   7
   8     def get_intregs(self):
   9         if False:
  10             yield
  11         self.intregs = []
  12         for i in range(32):
  13             simregval = self.sim.gpr[i].asint()
  14             self.intregs.append(simregval)
  15         print("class sim int regs", list(map(hex, self.intregs)))
  16
  17     def get_crregs(self):
  18         if False:
  19             yield
  20         self.crregs = []
  21         for i in range(8):
  22             cri = self.sim.crl[7 - i].get_range().value
  23             self.crregs.append(cri)
  24         print("class sim cr regs", list(map(hex, self.crregs)))
  25
  26     def get_xregs(self):
  27         if False:
  28             yield
  29         self.xregs = []
  30         self.so = self.sim.spr['XER'][XER_bits['SO']].value
  31         self.ov = self.sim.spr['XER'][XER_bits['OV']].value
  32         self.ov32 = self.sim.spr['XER'][XER_bits['OV32']].value
  33         self.ca = self.sim.spr['XER'][XER_bits['CA']].value
  34         self.ca32 = self.sim.spr['XER'][XER_bits['CA32']].value
  35         self.ov = self.ov | (self.ov32 << 1)
  36         self.ca = self.ca | (self.ca32 << 1)
  37         self.xregs.extend((self.so, self.ov, self.ca))
  38         print("class sim xregs", list(map(hex, self.xregs)))
  39
  40     def get_pc(self):
  41         if False:
  42             yield
  43         self.pcl = []
  44         self.pc = self.sim.pc.CIA.value
  45         self.pcl.append(self.pc)
  46         print("class sim pc", hex(self.pc))
  47
  48
  49 class HDLState:
  50     def __init__(self, core):
  51         self.core = core
  52
  53     def get_intregs(self):
  54         self.intregs = []
  55         for i in range(32):
  56             if self.core.regs.int.unary:
  57                 rval = yield self.core.regs.int.regs[i].reg
  58             else:
  59                 rval = yield self.core.regs.int.memory._array[i]
  60             self.intregs.append(rval)
  61         print("class hdl int regs", list(map(hex, self.intregs)))
  62
  63     def get_crregs(self):
  64         self.crregs = []
  65         for i in range(8):
  66             rval = yield self.core.regs.cr.regs[i].reg
  67             self.crregs.append(rval)
  68         print("class hdl cr regs", list(map(hex, self.crregs)))
  69
  70     def get_xregs(self):
  71         self.xregs = []
  72         self.xr = self.core.regs.xer
  73         self.so = yield self.xr.regs[self.xr.SO].reg
  74         self.ov = yield self.xr.regs[self.xr.OV].reg
  75         self.ca = yield self.xr.regs[self.xr.CA].reg
  76         self.xregs.extend((self.so, self.ov, self.ca))
  77         print("class hdl xregs", list(map(hex, self.xregs)))
  78
  79     def get_pc(self):
  80         self.pcl = []
  81         self.state = self.core.regs.state
  82         self.pc = yield self.state.r_ports['cia'].o_data
  83         self.pcl.append(self.pc)
  84         print("class hdl pc", hex(self.pc))