src/soc/simple/test/teststate.py

   1 from openpower.decoder.power_enums import XER_bits
   2 from openpower.util import log
   3
   4
   5 class State:
   6     def get_state(self):
   7         yield from self.get_intregs()
   8         yield from self.get_crregs()
   9         yield from self.get_xregs()
  10         yield from self.get_pc()
  11
  12     def compare(self, s2):
  13         # Compare int registers
  14         for i, (self.intregs, s2.intregs) in enumerate(
  15                 zip(self.intregs, s2.intregs)):
  16             log("asserting...reg", i, self.intregs, s2.intregs)
  17             log("code, frepr(code)", self.code, repr(self.code))
  18             self.dut.assertEqual(self.intregs, s2.intregs,
  19                 "int reg %d (%s) not equal (%s) %s. got %x  expected %x" %
  20                 (i, self.state_type, s2.state_type, repr(self.code),
  21                 self.intregs, s2.intregs))
  22
  23         # CR registers
  24         for i, (self.crregs, s2.crregs) in enumerate(
  25                 zip(self.crregs, s2.crregs)):
  26             log("asserting...cr", i, self.crregs, s2.crregs)
  27             self.dut.assertEqual(self.crregs, s2.crregs,
  28                 "cr reg %d (%s) not equal (%s) %s. got %x  expected %x" %
  29                 (i, self.state_type, s2.state_type, repr(self.code),
  30                 self.crregs, s2.crregs))
  31
  32         # XER
  33         self.dut.assertEqual(self.so, s2.so, "so mismatch (%s != %s) %s" %
  34             (self.state_type, s2.state_type, repr(self.code)))
  35         self.dut.assertEqual(self.ov, s2.ov, "ov mismatch (%s != %s) %s" %
  36             (self.state_type, s2.state_type, repr(self.code)))
  37         self.dut.assertEqual(self.ca, s2.ca, "ca mismatch (%s != %s) %s" %
  38             (self.state_type, s2.state_type, repr(self.code)))
  39
  40         # pc
  41         self.dut.assertEqual(self.pc, s2.pc, "pc mismatch (%s != %s) %s" %
  42             (self.state_type, s2.state_type, repr(self.code)))
  43
  44
  45 class SimState(State):
  46     def __init__(self, sim):
  47         self.sim = sim
  48
  49     def get_intregs(self):
  50         if False:
  51             yield
  52         self.intregs = []
  53         for i in range(32):
  54             simregval = self.sim.gpr[i].asint()
  55             self.intregs.append(simregval)
  56         log("class sim int regs", list(map(hex, self.intregs)))
  57
  58     def get_crregs(self):
  59         if False:
  60             yield
  61         self.crregs = []
  62         for i in range(8):
  63             cri = self.sim.crl[7 - i].get_range().value
  64             self.crregs.append(cri)
  65         log("class sim cr regs", list(map(hex, self.crregs)))
  66
  67     def get_xregs(self):
  68         if False:
  69             yield
  70         self.xregs = []
  71         self.so = self.sim.spr['XER'][XER_bits['SO']].value
  72         self.ov = self.sim.spr['XER'][XER_bits['OV']].value
  73         self.ov32 = self.sim.spr['XER'][XER_bits['OV32']].value
  74         self.ca = self.sim.spr['XER'][XER_bits['CA']].value
  75         self.ca32 = self.sim.spr['XER'][XER_bits['CA32']].value
  76         self.ov = self.ov | (self.ov32 << 1)
  77         self.ca = self.ca | (self.ca32 << 1)
  78         self.xregs.extend((self.so, self.ov, self.ca))
  79         log("class sim xregs", list(map(hex, self.xregs)))
  80
  81     def get_pc(self):
  82         if False:
  83             yield
  84         self.pcl = []
  85         self.pc = self.sim.pc.CIA.value
  86         self.pcl.append(self.pc)
  87         log("class sim pc", hex(self.pc))
  88
  89
  90 class HDLState(State):
  91     def __init__(self, core):
  92         self.core = core
  93
  94     def get_intregs(self):
  95         self.intregs = []
  96         for i in range(32):
  97             if self.core.regs.int.unary:
  98                 rval = yield self.core.regs.int.regs[i].reg
  99             else:
 100                 rval = yield self.core.regs.int.memory._array[i]
 101             self.intregs.append(rval)
 102         log("class hdl int regs", list(map(hex, self.intregs)))
 103
 104     def get_crregs(self):
 105         self.crregs = []
 106         for i in range(8):
 107             rval = yield self.core.regs.cr.regs[i].reg
 108             self.crregs.append(rval)
 109         log("class hdl cr regs", list(map(hex, self.crregs)))
 110
 111     def get_xregs(self):
 112         self.xregs = []
 113         self.xr = self.core.regs.xer
 114         self.so = yield self.xr.regs[self.xr.SO].reg
 115         self.ov = yield self.xr.regs[self.xr.OV].reg
 116         self.ca = yield self.xr.regs[self.xr.CA].reg
 117         self.xregs.extend((self.so, self.ov, self.ca))
 118         log("class hdl xregs", list(map(hex, self.xregs)))
 119
 120     def get_pc(self):
 121         self.pcl = []
 122         self.state = self.core.regs.state
 123         self.pc = yield self.state.r_ports['cia'].o_data
 124         self.pcl.append(self.pc)
 125         log("class hdl pc", hex(self.pc))
 126
 127
 128 global state_factory
 129 state_factory = {'sim': SimState, 'hdl': HDLState}
 130
 131
 132 def TestState(state_type, to_test, dut, code):
 133     state_class = state_factory[state_type]
 134     state = state_class(to_test)
 135     state.to_test = to_test
 136     state.dut = dut
 137     state.state_type = state_type
 138     state.code = code
 139     yield from state.get_state()
 140     return state