src/soc/sv/trans/svp64.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4
   5 """SVP64 OpenPOWER v3.0B assembly translator
   6
   7 This class takes raw svp64 assembly mnemonics (aliases excluded) and
   8 creates an EXT001-encoded "svp64 prefix" followed by a v3.0B opcode.
   9
  10 It is very simple and straightforward, the only weirdness being the
  11 extraction of the register information and conversion to v3.0B numbering.
  12
  13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
  14 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
  15 """
  16
  17 import os, sys
  18 from collections import OrderedDict
  19
  20 from soc.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
  21                                     SV64P_PID_SIZE, SVP64RMFields,
  22                                     SVP64RM_EXTRA2_SPEC_SIZE,
  23                                     SVP64RM_EXTRA3_SPEC_SIZE,
  24                                     SVP64RM_MODE_SIZE, SVP64RM_SMASK_SIZE,
  25                                     SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE,
  26                                     SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE,
  27                                     SVP64RM_ELWIDTH_SIZE)
  28 from soc.decoder.pseudo.pagereader import ISA
  29 from soc.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
  30 from soc.decoder.selectable_int import SelectableInt
  31
  32
  33 # decode GPR into sv extra
  34 def  get_extra_gpr(etype, regmode, field):
  35     if regmode == 'scalar':
  36         # cut into 2-bits 5-bits SS FFFFF
  37         sv_extra = field >> 5
  38         field = field & 0b11111
  39     else:
  40         # cut into 5-bits 2-bits FFFFF SS
  41         sv_extra = field & 0b11
  42         field = field >> 2
  43     return sv_extra, field
  44
  45
  46 # decode 3-bit CR into sv extra
  47 def  get_extra_cr_3bit(etype, regmode, field):
  48     if regmode == 'scalar':
  49         # cut into 2-bits 3-bits SS FFF
  50         sv_extra = field >> 3
  51         field = field & 0b111
  52     else:
  53         # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
  54         sv_extra = field & 0b1111
  55         field = field >> 4
  56     return sv_extra, field
  57
  58
  59 # decodes SUBVL
  60 def decode_subvl(encoding):
  61     pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
  62     assert encoding in pmap, \
  63         "encoding %s for SUBVL not recognised" % encoding
  64     return pmap[encoding]
  65
  66
  67 # decodes elwidth
  68 def decode_elwidth(encoding):
  69     pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
  70     assert encoding in pmap, \
  71         "encoding %s for elwidth not recognised" % encoding
  72     return pmap[encoding]
  73
  74
  75 # decodes predicate register encoding
  76 def decode_predicate(encoding):
  77     pmap = { # integer
  78             '1<<r3': (0, 0b001),
  79             'r3'   : (0, 0b010),
  80             '~r3'   : (0, 0b011),
  81             'r10'   : (0, 0b100),
  82             '~r10'  : (0, 0b101),
  83             'r30'   : (0, 0b110),
  84             '~r30'  : (0, 0b111),
  85             # CR
  86             'lt'    : (1, 0b000),
  87             'nl'    : (1, 0b001), 'ge'    : (1, 0b001), # same value
  88             'gt'    : (1, 0b010),
  89             'ng'    : (1, 0b011), 'le'    : (1, 0b011), # same value
  90             'eq'    : (1, 0b100),
  91             'ne'    : (1, 0b101),
  92             'so'    : (1, 0b110), 'un'    : (1, 0b110), # same value
  93             'ns'    : (1, 0b111), 'nu'    : (1, 0b111), # same value
  94            }
  95     assert encoding in pmap, \
  96         "encoding %s for predicate not recognised" % encoding
  97     return pmap[encoding]
  98
  99
 100 # decodes "Mode" in similar way to BO field (supposed to, anyway)
 101 def decode_bo(encoding):
 102     pmap = { # TODO: double-check that these are the same as Branch BO
 103             'lt'    : 0b000,
 104             'nl'    : 0b001, 'ge'    : 0b001, # same value
 105             'gt'    : 0b010,
 106             'ng'    : 0b011, 'le'    : 0b011, # same value
 107             'eq'    : 0b100,
 108             'ne'    : 0b101,
 109             'so'    : 0b110, 'un'    : 0b110, # same value
 110             'ns'    : 0b111, 'nu'    : 0b111, # same value
 111            }
 112     assert encoding in pmap, \
 113         "encoding %s for BO Mode not recognised" % encoding
 114     return pmap[encoding]
 115
 116 # partial-decode fail-first mode
 117 def decode_ffirst(encoding):
 118     if encoding in ['RC1', '~RC1']:
 119         return encoding
 120     return decode_bo(encoding)
 121
 122
 123 def decode_reg(field):
 124     # decode the field number. "5.v" or "3.s" or "9"
 125     field = field.split(".")
 126     regmode = 'scalar' # default
 127     if len(field) == 2:
 128         if field[1] == 's':
 129             regmode = 'scalar'
 130         elif field[1] == 'v':
 131             regmode = 'vector'
 132     field = int(field[0]) # actual register number
 133     return field, regmode
 134
 135
 136 def decode_imm(field):
 137     ldst_imm = "(" in field and field[-1] == ')'
 138     if ldst_imm:
 139         return field[:-1].split("(")
 140     else:
 141         return None, field
 142
 143 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
 144 class SVP64Asm:
 145     def __init__(self, lst):
 146         self.lst = lst
 147         self.trans = self.translate(lst)
 148
 149     def __iter__(self):
 150         yield from self.trans
 151
 152     def translate(self, lst):
 153         isa = ISA() # reads the v3.0B pseudo-code markdown files
 154         svp64 = SVP64RM() # reads the svp64 Remap entries for registers
 155         for insn in lst:
 156             # find first space, to get opcode
 157             ls = insn.split(' ')
 158             opcode = ls[0]
 159             # now find opcode fields
 160             fields = ''.join(ls[1:]).split(',')
 161             fields = list(map(str.strip, fields))
 162             print ("opcode, fields", ls, opcode, fields)
 163
 164             # identify if is a svp64 mnemonic
 165             if not opcode.startswith('sv.'):
 166                 yield insn  # unaltered
 167                 continue
 168             opcode = opcode[3:] # strip leading "sv."
 169
 170             # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
 171             opmodes = opcode.split("/") # split at "/"
 172             v30b_op = opmodes.pop(0)    # first is the v3.0B
 173             # check instruction ends with dot
 174             rc_mode = v30b_op.endswith('.')
 175             if rc_mode:
 176                 v30b_op = v30b_op[:-1]
 177
 178             if v30b_op not in isa.instr:
 179                 raise Exception("opcode %s of '%s' not supported" % \
 180                                 (v30b_op, insn))
 181             if v30b_op not in svp64.instrs:
 182                 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
 183                                 (v30b_op, insn))
 184             v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
 185             rm = svp64.instrs[v30b_op]             # one row of the svp64 RM CSV
 186             print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
 187             print ("v3.0B regs", opcode, v30b_regs)
 188             print (rm)
 189
 190             # right.  the first thing to do is identify the ordering of
 191             # the registers, by name.  the EXTRA2/3 ordering is in
 192             # rm['0']..rm['3'] but those fields contain the names RA, BB
 193             # etc.  we have to read the pseudocode to understand which
 194             # reg is which in our instruction. sigh.
 195
 196             # first turn the svp64 rm into a "by name" dict, recording
 197             # which position in the RM EXTRA it goes into
 198             # also: record if the src or dest was a CR, for sanity-checking
 199             # (elwidth overrides on CRs are banned)
 200             decode = decode_extra(rm)
 201             dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
 202             svp64_reg_byname = {}
 203             svp64_reg_byname.update(svp64_src)
 204             svp64_reg_byname.update(svp64_dest)
 205
 206             print ("EXTRA field index, by regname", svp64_reg_byname)
 207
 208             # okaaay now we identify the field value (opcode N,N,N) with
 209             # the pseudo-code info (opcode RT, RA, RB)
 210             assert len(fields) == len(v30b_regs), \
 211                 "length of fields %s must match insn `%s`" % \
 212                         (str(v30b_regs), insn)
 213             opregfields = zip(fields, v30b_regs) # err that was easy
 214
 215             # now for each of those find its place in the EXTRA encoding
 216             extras = OrderedDict()
 217             for idx, (field, regname) in enumerate(opregfields):
 218                 extra = svp64_reg_byname.get(regname, None)
 219                 imm, regname = decode_imm(regname)
 220                 rtype = get_regtype(regname)
 221                 extras[extra] = (idx, field, regname, rtype, imm)
 222                 print ("    ", extra, extras[extra])
 223
 224             # great! got the extra fields in their associated positions:
 225             # also we know the register type. now to create the EXTRA encodings
 226             etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
 227             ptype = rm['Ptype'] # Predication type: Twin / Single
 228             extra_bits = 0
 229             v30b_newfields = []
 230             for extra_idx, (idx, field, rname, rtype, iname) in extras.items():
 231                 # is it a field we don't alter/examine?  if so just put it
 232                 # into newfields
 233                 if rtype is None:
 234                     v30b_newfields.append(field)
 235
 236                 # identify if this is a ld/st immediate(reg) thing
 237                 ldst_imm = "(" in field and field[-1] == ')'
 238                 if ldst_imm:
 239                     immed, field = field[:-1].split("(")
 240
 241                 field, regmode = decode_reg(field)
 242                 print ("    ", rtype, regmode, iname, field, end=" ")
 243
 244                 # see Mode field https://libre-soc.org/openpower/sv/svp64/
 245                 # XXX TODO: the following is a bit of a laborious repeated
 246                 # mess, which could (and should) easily be parameterised.
 247                 # XXX also TODO: the LD/ST modes which are different
 248                 # https://libre-soc.org/openpower/sv/ldst/
 249
 250                 # encode SV-GPR field into extra, v3.0field
 251                 if rtype == 'GPR':
 252                     sv_extra, field = get_extra_gpr(etype, regmode, field)
 253                     # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
 254                     # (and shrink to a single bit if ok)
 255                     if etype == 'EXTRA2':
 256                         if regmode == 'scalar':
 257                             # range is r0-r63 in increments of 1
 258                             assert (sv_extra >> 1) == 0, \
 259                                 "scalar GPR %s cannot fit into EXTRA2 %s" % \
 260                                     (rname, str(extras[extra_idx]))
 261                             # all good: encode as scalar
 262                             sv_extra = sv_extra & 0b01
 263                         else:
 264                             # range is r0-r127 in increments of 4
 265                             assert sv_extra & 0b01 == 0, \
 266                                 "vector field %s cannot fit into EXTRA2 %s" % \
 267                                     (rname, str(extras[extra_idx]))
 268                             # all good: encode as vector (bit 2 set)
 269                             sv_extra = 0b10 | (sv_extra >> 1)
 270                     elif regmode == 'vector':
 271                         # EXTRA3 vector bit needs marking
 272                         sv_extra |= 0b100
 273
 274                 # encode SV-CR 3-bit field into extra, v3.0field
 275                 elif rtype == 'CR_3bit':
 276                     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 277                     # now sanity-check (and shrink afterwards)
 278                     if etype == 'EXTRA2':
 279                         if regmode == 'scalar':
 280                             # range is CR0-CR15 in increments of 1
 281                             assert (sv_extra >> 1) == 0, \
 282                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 283                                     (rname, str(extras[extra_idx]))
 284                             # all good: encode as scalar
 285                             sv_extra = sv_extra & 0b01
 286                         else:
 287                             # range is CR0-CR127 in increments of 16
 288                             assert sv_extra & 0b111 == 0, \
 289                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 290                                     (rname, str(extras[extra_idx]))
 291                             # all good: encode as vector (bit 2 set)
 292                             sv_extra = 0b10 | (sv_extra >> 3)
 293                     else:
 294                         if regmode == 'scalar':
 295                             # range is CR0-CR31 in increments of 1
 296                             assert (sv_extra >> 2) == 0, \
 297                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 298                                     (rname, str(extras[extra_idx]))
 299                             # all good: encode as scalar
 300                             sv_extra = sv_extra & 0b11
 301                         else:
 302                             # range is CR0-CR127 in increments of 8
 303                             assert sv_extra & 0b11 == 0, \
 304                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 305                                     (rname, str(extras[extra_idx]))
 306                             # all good: encode as vector (bit 3 set)
 307                             sv_extra = 0b100 | (sv_extra >> 2)
 308
 309                 # encode SV-CR 5-bit field into extra, v3.0field
 310                 # *sigh* this is the same as 3-bit except the 2 LSBs are
 311                 # passed through
 312                 elif rtype == 'CR_5bit':
 313                     cr_subfield = field & 0b11
 314                     field = field >> 2 # strip bottom 2 bits
 315                     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 316                     # now sanity-check (and shrink afterwards)
 317                     if etype == 'EXTRA2':
 318                         if regmode == 'scalar':
 319                             # range is CR0-CR15 in increments of 1
 320                             assert (sv_extra >> 1) == 0, \
 321                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 322                                     (rname, str(extras[extra_idx]))
 323                             # all good: encode as scalar
 324                             sv_extra = sv_extra & 0b01
 325                         else:
 326                             # range is CR0-CR127 in increments of 16
 327                             assert sv_extra & 0b111 == 0, \
 328                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 329                                     (rname, str(extras[extra_idx]))
 330                             # all good: encode as vector (bit 2 set)
 331                             sv_extra = 0b10 | (sv_extra >> 3)
 332                     else:
 333                         if regmode == 'scalar':
 334                             # range is CR0-CR31 in increments of 1
 335                             assert (sv_extra >> 2) == 0, \
 336                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 337                                     (rname, str(extras[extra_idx]))
 338                             # all good: encode as scalar
 339                             sv_extra = sv_extra & 0b11
 340                         else:
 341                             # range is CR0-CR127 in increments of 8
 342                             assert sv_extra & 0b11 == 0, \
 343                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 344                                     (rname, str(extras[extra_idx]))
 345                             # all good: encode as vector (bit 3 set)
 346                             sv_extra = 0b100 | (sv_extra >> 2)
 347
 348                     # reconstruct the actual 5-bit CR field
 349                     field = (field << 2) | cr_subfield
 350
 351                 # capture the extra field info
 352                 print ("=>", "%5s" % bin(sv_extra), field)
 353                 extras[extra_idx] = sv_extra
 354
 355                 # append altered field value to v3.0b, differs for LDST
 356                 if ldst_imm:
 357                     v30b_newfields.append(("%s(%s)" % (immed, str(field))))
 358                 else:
 359                     v30b_newfields.append(str(field))
 360
 361             print ("new v3.0B fields", v30b_op, v30b_newfields)
 362             print ("extras", extras)
 363
 364             # rright.  now we have all the info. start creating SVP64 RM
 365             svp64_rm = SVP64RMFields()
 366
 367             # begin with EXTRA fields
 368             for idx, sv_extra in extras.items():
 369                 if idx is None: continue
 370                 if etype == 'EXTRA2':
 371                     svp64_rm.extra2[idx].eq(
 372                         SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE))
 373                 else:
 374                     svp64_rm.extra3[idx].eq(
 375                         SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE))
 376
 377             # parts of svp64_rm
 378             mmode = 0  # bit 0
 379             pmask = 0  # bits 1-3
 380             destwid = 0 # bits 4-5
 381             srcwid = 0 # bits 6-7
 382             subvl = 0   # bits 8-9
 383             smask = 0 # bits 16-18 but only for twin-predication
 384             mode = 0 # bits 19-23
 385
 386             has_pmask = False
 387             has_smask = False
 388
 389             saturation = None
 390             src_zero = 0
 391             dst_zero = 0
 392             sv_mode = None
 393
 394             mapreduce = False
 395             mapreduce_crm = False
 396             mapreduce_svm = False
 397
 398             predresult = False
 399             failfirst = False
 400
 401             # ok let's start identifying opcode augmentation fields
 402             for encmode in opmodes:
 403                 # predicate mask (dest)
 404                 if encmode.startswith("m="):
 405                     pme = encmode
 406                     pmmode, pmask = decode_predicate(encmode[2:])
 407                     mmode = pmmode
 408                     has_pmask = True
 409                 # predicate mask (src, twin-pred)
 410                 elif encmode.startswith("sm="):
 411                     sme = encmode
 412                     smmode, smask = decode_predicate(encmode[3:])
 413                     mmode = smmode
 414                     has_smask = True
 415                 # vec2/3/4
 416                 elif encmode.startswith("vec"):
 417                     subvl = decode_subvl(encmode[3:])
 418                 # elwidth
 419                 elif encmode.startswith("ew="):
 420                     destwid = decode_elwidth(encmode[3:])
 421                 elif encmode.startswith("sw="):
 422                     srcwid = decode_elwidth(encmode[3:])
 423                 # saturation
 424                 elif encmode == 'sats':
 425                     assert sv_mode is None
 426                     saturation = 1
 427                     sv_mode = 0b10
 428                 elif encmode == 'satu':
 429                     assert sv_mode is None
 430                     sv_mode = 0b10
 431                     saturation = 0
 432                 # predicate zeroing
 433                 elif encmode == 'sz':
 434                     src_zero = 1
 435                 elif encmode == 'dz':
 436                     dst_zero = 1
 437                 # failfirst
 438                 elif encmode.startswith("ff="):
 439                     assert sv_mode is None
 440                     sv_mode = 0b01
 441                     failfirst = decode_ffirst(encmode[3:])
 442                 # predicate-result, interestingly same as fail-first
 443                 elif encmode.startswith("pr="):
 444                     assert sv_mode is None
 445                     sv_mode = 0b11
 446                     predresult = decode_ffirst(encmode[3:])
 447                 # map-reduce mode
 448                 elif encmode == 'mr':
 449                     assert sv_mode is None
 450                     sv_mode = 0b00
 451                     mapreduce = True
 452                 elif encmode == 'crm': # CR on map-reduce
 453                     assert sv_mode is None
 454                     sv_mode = 0b00
 455                     mapreduce_crm = True
 456                 elif encmode == 'svm': # sub-vector mode
 457                     mapreduce_svm = True
 458
 459             # sanity-check that 2Pred mask is same mode
 460             if has_pmask and has_smask:
 461                 assert smmode == pmmode, \
 462                     "predicate masks %s and %s must be same reg type" % \
 463                         (pme, sme)
 464
 465             # sanity-check that twin-predication mask only specified in 2P mode
 466             if ptype == '1P':
 467                 assert has_smask == False, \
 468                     "source-mask can only be specified on Twin-predicate ops"
 469
 470             # construct the mode field, doing sanity-checking along the way
 471
 472             if mapreduce_svm:
 473                 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
 474                 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
 475
 476             if src_zero:
 477                 assert has_smask, "src zeroing requires a source predicate"
 478             if dst_zero:
 479                 assert has_pmask, "dest zeroing requires a dest predicate"
 480
 481             # "normal" mode
 482             if sv_mode is None:
 483                 mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
 484                 sv_mode = 0b00
 485
 486             # "mapreduce" modes
 487             elif sv_mode == 0b00:
 488                 mode |= (0b1<<2) # sets mapreduce
 489                 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
 490                 if mapreduce_crm:
 491                     mode |= (0b1<<4) # sets CRM mode
 492                     assert rc_mode, "CRM only allowed when Rc=1"
 493                 # bit of weird encoding to jam zero-pred or SVM mode in.
 494                 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
 495                 if subvl == 0:
 496                     mode |= (src_zero << 3) # predicate src-zeroing
 497                 elif mapreduce_svm:
 498                     mode |= (1 << 3) # SVM mode
 499
 500             # "failfirst" modes
 501             elif sv_mode == 0b01:
 502                 assert dst_zero == 0, "dest-zero not allowed in failfirst mode"
 503                 if failfirst == 'RC1':
 504                     mode |= (0b1<<4) # sets RC1 mode
 505                     mode |= (src_zero << 3) # predicate src-zeroing
 506                     assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
 507                 elif failfirst == '~RC1':
 508                     mode |= (0b1<<4) # sets RC1 mode...
 509                     mode |= (src_zero << 3) # predicate src-zeroing
 510                     mode |= (0b1<<2) # ... with inversion
 511                     assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
 512                 else:
 513                     assert src_zero == 0, "src-zero not allowed in ffirst BO"
 514                     assert rc_mode, "ffirst BO only possible when Rc=1"
 515                     mode |= (failfirst << 2) # set BO
 516
 517             # "saturation" modes
 518             elif sv_mode == 0b10:
 519                 mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
 520                 mode |= (saturation<<2) # sets signed/unsigned saturation
 521
 522             # "predicate-result" modes.  err... code-duplication from ffirst
 523             elif sv_mode == 0b11:
 524                 assert dst_zero == 0, "dest-zero not allowed in predresult mode"
 525                 if predresult == 'RC1':
 526                     mode |= (0b1<<4) # sets RC1 mode
 527                     mode |= (src_zero << 3) # predicate src-zeroing
 528                     assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
 529                 elif predresult == '~RC1':
 530                     mode |= (0b1<<4) # sets RC1 mode...
 531                     mode |= (src_zero << 3) # predicate src-zeroing
 532                     mode |= (0b1<<2) # ... with inversion
 533                     assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
 534                 else:
 535                     assert src_zero == 0, "src-zero not allowed in pr-mode BO"
 536                     assert rc_mode, "pr-mode BO only possible when Rc=1"
 537                     mode |= (predresult << 2) # set BO
 538
 539             # whewww.... modes all done :)
 540             # now put into svp64_rm
 541             mode |= sv_mode
 542             # mode: bits 19-23
 543             svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE))
 544
 545             # put in predicate masks into svp64_rm
 546             if ptype == '2P':
 547                 # source pred: bits 16-18
 548                 svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE))
 549             # mask mode: bit 0
 550             svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE))
 551             # 1-pred: bits 1-3
 552             svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE))
 553
 554             # and subvl: bits 8-9
 555             svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE))
 556
 557             # put in elwidths
 558             # srcwid: bits 6-7
 559             svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE))
 560             # destwid: bits 4-5
 561             svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE))
 562
 563             # nice debug printout. (and now for something completely different)
 564             # https://youtu.be/u0WOIwlXE9g?t=146
 565             svp64_rm_value = svp64_rm.spr.value
 566             print ("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
 567             print ("    mmode  0    :", bin(mmode))
 568             print ("    pmask  1-3  :", bin(pmask))
 569             print ("    dstwid 4-5  :", bin(destwid))
 570             print ("    srcwid 6-7  :", bin(srcwid))
 571             print ("    subvl  8-9  :", bin(subvl))
 572             print ("    mode   19-23:", bin(mode))
 573             offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
 574             for idx, sv_extra in extras.items():
 575                 if idx is None: continue
 576                 start = (10+idx*offs)
 577                 end = start + offs-1
 578                 print ("    extra%d %2d-%2d:" % (idx, start, end),
 579                         bin(sv_extra))
 580             if ptype == '2P':
 581                 print ("    smask  16-17:", bin(smask))
 582             print ()
 583
 584             # first, construct the prefix from its subfields
 585             svp64_prefix = SVP64PrefixFields()
 586             svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
 587             svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
 588             svp64_prefix.rm.eq(svp64_rm.spr)
 589
 590             # fiinally yield the svp64 prefix and the thingy.  v3.0b opcode
 591             rc = '.' if rc_mode else ''
 592             yield ".long 0x%x" % svp64_prefix.insn.value
 593             yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
 594             print ("new v3.0B fields", v30b_op, v30b_newfields)
 595
 596 if __name__ == '__main__':
 597     lst = ['slw 3, 1, 4',
 598                  'extsw 5, 3',
 599                  'sv.extsw 5, 3',
 600                  'sv.cmpi 5, 1, 3, 2',
 601                  'sv.setb 5, 31',
 602                  'sv.isel 64.v, 3, 2, 65.v',
 603                  'sv.setb/m=r3/sm=1<<r3 5, 31',
 604                  'sv.setb/vec2 5, 31',
 605                  'sv.setb/sw=8/ew=16 5, 31',
 606                  'sv.extsw./ff=eq 5, 31',
 607                  'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31',
 608                  'sv.extsw./pr=eq 5.v, 31',
 609                  'sv.add. 5.v, 2.v, 1.v',
 610                 ]
 611     lst += [
 612                  'sv.ld 5.v, 4(4.v)',
 613           ]
 614     isa = SVP64Asm(lst)
 615     print ("list", list(isa))
 616     csvs = SVP64RM()