src/soc/sv/trans/svp64.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4
   5 """SVP64 OpenPOWER v3.0B assembly translator
   6
   7 This class takes raw svp64 assembly mnemonics (aliases excluded) and
   8 creates an EXT001-encoded "svp64 prefix" followed by a v3.0B opcode.
   9
  10 It is very simple and straightforward, the only weirdness being the
  11 extraction of the register information and conversion to v3.0B numbering.
  12
  13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
  14 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
  15 """
  16
  17 import os, sys
  18 from collections import OrderedDict
  19
  20 from soc.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
  21                                     SV64P_PID_SIZE, SVP64RMFields,
  22                                     SVP64RM_EXTRA2_SPEC_SIZE,
  23                                     SVP64RM_EXTRA3_SPEC_SIZE,
  24                                     SVP64RM_MODE_SIZE, SVP64RM_SMASK_SIZE,
  25                                     SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE,
  26                                     SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE,
  27                                     SVP64RM_ELWIDTH_SIZE)
  28 from soc.decoder.pseudo.pagereader import ISA
  29 from soc.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
  30 from soc.decoder.selectable_int import SelectableInt
  31
  32
  33 # decode GPR into sv extra
  34 def  get_extra_gpr(etype, regmode, field):
  35     if regmode == 'scalar':
  36         # cut into 2-bits 5-bits SS FFFFF
  37         sv_extra = field >> 5
  38         field = field & 0b11111
  39     else:
  40         # cut into 5-bits 2-bits FFFFF SS
  41         sv_extra = field & 0b11
  42         field = field >> 2
  43     return sv_extra, field
  44
  45
  46 # decode 3-bit CR into sv extra
  47 def  get_extra_cr_3bit(etype, regmode, field):
  48     if regmode == 'scalar':
  49         # cut into 2-bits 3-bits SS FFF
  50         sv_extra = field >> 3
  51         field = field & 0b111
  52     else:
  53         # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
  54         sv_extra = field & 0b1111
  55         field = field >> 4
  56     return sv_extra, field
  57
  58
  59 # decodes SUBVL
  60 def decode_subvl(encoding):
  61     pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
  62     assert encoding in pmap, \
  63         "encoding %s for SUBVL not recognised" % encoding
  64     return pmap[encoding]
  65
  66
  67 # decodes elwidth
  68 def decode_elwidth(encoding):
  69     pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
  70     assert encoding in pmap, \
  71         "encoding %s for elwidth not recognised" % encoding
  72     return pmap[encoding]
  73
  74
  75 # decodes predicate register encoding
  76 def decode_predicate(encoding):
  77     pmap = { # integer
  78             '1<<r3': (0, 0b001),
  79             'r3'   : (0, 0b010),
  80             '~r3'   : (0, 0b011),
  81             'r10'   : (0, 0b100),
  82             '~r10'  : (0, 0b101),
  83             'r30'   : (0, 0b110),
  84             '~r30'  : (0, 0b111),
  85             # CR
  86             'lt'    : (1, 0b000),
  87             'nl'    : (1, 0b001), 'ge'    : (1, 0b001), # same value
  88             'gt'    : (1, 0b010),
  89             'ng'    : (1, 0b011), 'le'    : (1, 0b011), # same value
  90             'eq'    : (1, 0b100),
  91             'ne'    : (1, 0b101),
  92             'so'    : (1, 0b110), 'un'    : (1, 0b110), # same value
  93             'ns'    : (1, 0b111), 'nu'    : (1, 0b111), # same value
  94            }
  95     assert encoding in pmap, \
  96         "encoding %s for predicate not recognised" % encoding
  97     return pmap[encoding]
  98
  99
 100 # decodes "Mode" in similar way to BO field (supposed to, anyway)
 101 def decode_bo(encoding):
 102     pmap = { # TODO: double-check that these are the same as Branch BO
 103             'lt'    : 0b000,
 104             'nl'    : 0b001, 'ge'    : 0b001, # same value
 105             'gt'    : 0b010,
 106             'ng'    : 0b011, 'le'    : 0b011, # same value
 107             'eq'    : 0b100,
 108             'ne'    : 0b101,
 109             'so'    : 0b110, 'un'    : 0b110, # same value
 110             'ns'    : 0b111, 'nu'    : 0b111, # same value
 111            }
 112     assert encoding in pmap, \
 113         "encoding %s for BO Mode not recognised" % encoding
 114     return pmap[encoding]
 115
 116 # partial-decode fail-first mode
 117 def decode_ffirst(encoding):
 118     if encoding in ['RC1', '~RC1']:
 119         return encoding
 120     return decode_bo(encoding)
 121
 122
 123 def decode_reg(field):
 124     # decode the field number. "5.v" or "3.s" or "9"
 125     field = field.split(".")
 126     regmode = 'scalar' # default
 127     if len(field) == 2:
 128         if field[1] == 's':
 129             regmode = 'scalar'
 130         elif field[1] == 'v':
 131             regmode = 'vector'
 132     field = int(field[0]) # actual register number
 133     return field, regmode
 134
 135
 136 def decode_imm(field):
 137     ldst_imm = "(" in field and field[-1] == ')'
 138     if ldst_imm:
 139         return field[:-1].split("(")
 140     else:
 141         return None, field
 142
 143 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
 144 class SVP64Asm:
 145     def __init__(self, lst, bigendian=False):
 146         self.lst = lst
 147         self.trans = self.translate(lst)
 148         assert bigendian == False, "error, bigendian not supported yet"
 149
 150     def __iter__(self):
 151         yield from self.trans
 152
 153     def translate(self, lst):
 154         isa = ISA() # reads the v3.0B pseudo-code markdown files
 155         svp64 = SVP64RM() # reads the svp64 Remap entries for registers
 156         for insn in lst:
 157             # find first space, to get opcode
 158             ls = insn.split(' ')
 159             opcode = ls[0]
 160             # now find opcode fields
 161             fields = ''.join(ls[1:]).split(',')
 162             fields = list(map(str.strip, fields))
 163             print ("opcode, fields", ls, opcode, fields)
 164
 165             # sigh have to do setvl here manually for now...
 166             if opcode in ["setvl", "setvl."]:
 167                 insn = 22 << (31-5)          # opcode 22, bits 0-5
 168                 fields = list(map(int, fields))
 169                 insn |= fields[0] << (31-10) # RT       , bits 6-10
 170                 insn |= fields[1] << (31-15) # RA       , bits 11-15
 171                 insn |= fields[2] << (31-23) # SVi      , bits 16-23
 172                 insn |= fields[3] << (31-24) # vs       , bit  24
 173                 insn |= fields[4] << (31-25) # ms       , bit  25
 174                 insn |= 0b00000   << (31-30) # XO       , bits 26..30
 175                 if opcode == 'setvl.':
 176                     insn |= 1 << (31-31)     # Rc=1     , bit 31
 177                 print ("setvl", bin(insn))
 178                 yield ".long 0x%x" % insn
 179                 continue
 180
 181             # identify if is a svp64 mnemonic
 182             if not opcode.startswith('sv.'):
 183                 yield insn  # unaltered
 184                 continue
 185             opcode = opcode[3:] # strip leading "sv."
 186
 187             # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
 188             opmodes = opcode.split("/") # split at "/"
 189             v30b_op = opmodes.pop(0)    # first is the v3.0B
 190             # check instruction ends with dot
 191             rc_mode = v30b_op.endswith('.')
 192             if rc_mode:
 193                 v30b_op = v30b_op[:-1]
 194
 195             if v30b_op not in isa.instr:
 196                 raise Exception("opcode %s of '%s' not supported" % \
 197                                 (v30b_op, insn))
 198             if v30b_op not in svp64.instrs:
 199                 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
 200                                 (v30b_op, insn))
 201             v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
 202             rm = svp64.instrs[v30b_op]             # one row of the svp64 RM CSV
 203             print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
 204             print ("v3.0B regs", opcode, v30b_regs)
 205             print (rm)
 206
 207             # right.  the first thing to do is identify the ordering of
 208             # the registers, by name.  the EXTRA2/3 ordering is in
 209             # rm['0']..rm['3'] but those fields contain the names RA, BB
 210             # etc.  we have to read the pseudocode to understand which
 211             # reg is which in our instruction. sigh.
 212
 213             # first turn the svp64 rm into a "by name" dict, recording
 214             # which position in the RM EXTRA it goes into
 215             # also: record if the src or dest was a CR, for sanity-checking
 216             # (elwidth overrides on CRs are banned)
 217             decode = decode_extra(rm)
 218             dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
 219             svp64_reg_byname = {}
 220             svp64_reg_byname.update(svp64_src)
 221             svp64_reg_byname.update(svp64_dest)
 222
 223             print ("EXTRA field index, by regname", svp64_reg_byname)
 224
 225             # okaaay now we identify the field value (opcode N,N,N) with
 226             # the pseudo-code info (opcode RT, RA, RB)
 227             assert len(fields) == len(v30b_regs), \
 228                 "length of fields %s must match insn `%s`" % \
 229                         (str(v30b_regs), insn)
 230             opregfields = zip(fields, v30b_regs) # err that was easy
 231
 232             # now for each of those find its place in the EXTRA encoding
 233             extras = OrderedDict()
 234             for idx, (field, regname) in enumerate(opregfields):
 235                 imm, regname = decode_imm(regname)
 236                 extra = svp64_reg_byname.get(regname, None)
 237                 rtype = get_regtype(regname)
 238                 extras[extra] = (idx, field, regname, rtype, imm)
 239                 print ("    ", extra, extras[extra])
 240
 241             # great! got the extra fields in their associated positions:
 242             # also we know the register type. now to create the EXTRA encodings
 243             etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
 244             ptype = rm['Ptype'] # Predication type: Twin / Single
 245             extra_bits = 0
 246             v30b_newfields = []
 247             for extra_idx, (idx, field, rname, rtype, iname) in extras.items():
 248                 # is it a field we don't alter/examine?  if so just put it
 249                 # into newfields
 250                 if rtype is None:
 251                     v30b_newfields.append(field)
 252
 253                 # identify if this is a ld/st immediate(reg) thing
 254                 ldst_imm = "(" in field and field[-1] == ')'
 255                 if ldst_imm:
 256                     immed, field = field[:-1].split("(")
 257
 258                 field, regmode = decode_reg(field)
 259                 print ("    ", extra_idx, rname, rtype,
 260                                regmode, iname, field, end=" ")
 261
 262                 # see Mode field https://libre-soc.org/openpower/sv/svp64/
 263                 # XXX TODO: the following is a bit of a laborious repeated
 264                 # mess, which could (and should) easily be parameterised.
 265                 # XXX also TODO: the LD/ST modes which are different
 266                 # https://libre-soc.org/openpower/sv/ldst/
 267
 268                 # encode SV-GPR field into extra, v3.0field
 269                 if rtype == 'GPR':
 270                     sv_extra, field = get_extra_gpr(etype, regmode, field)
 271                     # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
 272                     # (and shrink to a single bit if ok)
 273                     if etype == 'EXTRA2':
 274                         if regmode == 'scalar':
 275                             # range is r0-r63 in increments of 1
 276                             assert (sv_extra >> 1) == 0, \
 277                                 "scalar GPR %s cannot fit into EXTRA2 %s" % \
 278                                     (rname, str(extras[extra_idx]))
 279                             # all good: encode as scalar
 280                             sv_extra = sv_extra & 0b01
 281                         else:
 282                             # range is r0-r127 in increments of 4
 283                             assert sv_extra & 0b01 == 0, \
 284                                 "vector field %s cannot fit into EXTRA2 %s" % \
 285                                     (rname, str(extras[extra_idx]))
 286                             # all good: encode as vector (bit 2 set)
 287                             sv_extra = 0b10 | (sv_extra >> 1)
 288                     elif regmode == 'vector':
 289                         # EXTRA3 vector bit needs marking
 290                         sv_extra |= 0b100
 291
 292                 # encode SV-CR 3-bit field into extra, v3.0field
 293                 elif rtype == 'CR_3bit':
 294                     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 295                     # now sanity-check (and shrink afterwards)
 296                     if etype == 'EXTRA2':
 297                         if regmode == 'scalar':
 298                             # range is CR0-CR15 in increments of 1
 299                             assert (sv_extra >> 1) == 0, \
 300                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 301                                     (rname, str(extras[extra_idx]))
 302                             # all good: encode as scalar
 303                             sv_extra = sv_extra & 0b01
 304                         else:
 305                             # range is CR0-CR127 in increments of 16
 306                             assert sv_extra & 0b111 == 0, \
 307                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 308                                     (rname, str(extras[extra_idx]))
 309                             # all good: encode as vector (bit 2 set)
 310                             sv_extra = 0b10 | (sv_extra >> 3)
 311                     else:
 312                         if regmode == 'scalar':
 313                             # range is CR0-CR31 in increments of 1
 314                             assert (sv_extra >> 2) == 0, \
 315                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 316                                     (rname, str(extras[extra_idx]))
 317                             # all good: encode as scalar
 318                             sv_extra = sv_extra & 0b11
 319                         else:
 320                             # range is CR0-CR127 in increments of 8
 321                             assert sv_extra & 0b11 == 0, \
 322                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 323                                     (rname, str(extras[extra_idx]))
 324                             # all good: encode as vector (bit 3 set)
 325                             sv_extra = 0b100 | (sv_extra >> 2)
 326
 327                 # encode SV-CR 5-bit field into extra, v3.0field
 328                 # *sigh* this is the same as 3-bit except the 2 LSBs are
 329                 # passed through
 330                 elif rtype == 'CR_5bit':
 331                     cr_subfield = field & 0b11
 332                     field = field >> 2 # strip bottom 2 bits
 333                     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 334                     # now sanity-check (and shrink afterwards)
 335                     if etype == 'EXTRA2':
 336                         if regmode == 'scalar':
 337                             # range is CR0-CR15 in increments of 1
 338                             assert (sv_extra >> 1) == 0, \
 339                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 340                                     (rname, str(extras[extra_idx]))
 341                             # all good: encode as scalar
 342                             sv_extra = sv_extra & 0b01
 343                         else:
 344                             # range is CR0-CR127 in increments of 16
 345                             assert sv_extra & 0b111 == 0, \
 346                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 347                                     (rname, str(extras[extra_idx]))
 348                             # all good: encode as vector (bit 2 set)
 349                             sv_extra = 0b10 | (sv_extra >> 3)
 350                     else:
 351                         if regmode == 'scalar':
 352                             # range is CR0-CR31 in increments of 1
 353                             assert (sv_extra >> 2) == 0, \
 354                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 355                                     (rname, str(extras[extra_idx]))
 356                             # all good: encode as scalar
 357                             sv_extra = sv_extra & 0b11
 358                         else:
 359                             # range is CR0-CR127 in increments of 8
 360                             assert sv_extra & 0b11 == 0, \
 361                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 362                                     (rname, str(extras[extra_idx]))
 363                             # all good: encode as vector (bit 3 set)
 364                             sv_extra = 0b100 | (sv_extra >> 2)
 365
 366                     # reconstruct the actual 5-bit CR field
 367                     field = (field << 2) | cr_subfield
 368
 369                 # capture the extra field info
 370                 print ("=>", "%5s" % bin(sv_extra), field)
 371                 extras[extra_idx] = sv_extra
 372
 373                 # append altered field value to v3.0b, differs for LDST
 374                 if ldst_imm:
 375                     v30b_newfields.append(("%s(%s)" % (immed, str(field))))
 376                 else:
 377                     v30b_newfields.append(str(field))
 378
 379             print ("new v3.0B fields", v30b_op, v30b_newfields)
 380             print ("extras", extras)
 381
 382             # rright.  now we have all the info. start creating SVP64 RM
 383             svp64_rm = SVP64RMFields()
 384
 385             # begin with EXTRA fields
 386             for idx, sv_extra in extras.items():
 387                 if idx is None: continue
 388                 if etype == 'EXTRA2':
 389                     svp64_rm.extra2[idx].eq(
 390                         SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE))
 391                 else:
 392                     svp64_rm.extra3[idx].eq(
 393                         SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE))
 394
 395             # parts of svp64_rm
 396             mmode = 0  # bit 0
 397             pmask = 0  # bits 1-3
 398             destwid = 0 # bits 4-5
 399             srcwid = 0 # bits 6-7
 400             subvl = 0   # bits 8-9
 401             smask = 0 # bits 16-18 but only for twin-predication
 402             mode = 0 # bits 19-23
 403
 404             has_pmask = False
 405             has_smask = False
 406
 407             saturation = None
 408             src_zero = 0
 409             dst_zero = 0
 410             sv_mode = None
 411
 412             mapreduce = False
 413             mapreduce_crm = False
 414             mapreduce_svm = False
 415
 416             predresult = False
 417             failfirst = False
 418
 419             # ok let's start identifying opcode augmentation fields
 420             for encmode in opmodes:
 421                 # predicate mask (dest)
 422                 if encmode.startswith("m="):
 423                     pme = encmode
 424                     pmmode, pmask = decode_predicate(encmode[2:])
 425                     mmode = pmmode
 426                     has_pmask = True
 427                 # predicate mask (src, twin-pred)
 428                 elif encmode.startswith("sm="):
 429                     sme = encmode
 430                     smmode, smask = decode_predicate(encmode[3:])
 431                     mmode = smmode
 432                     has_smask = True
 433                 # vec2/3/4
 434                 elif encmode.startswith("vec"):
 435                     subvl = decode_subvl(encmode[3:])
 436                 # elwidth
 437                 elif encmode.startswith("ew="):
 438                     destwid = decode_elwidth(encmode[3:])
 439                 elif encmode.startswith("sw="):
 440                     srcwid = decode_elwidth(encmode[3:])
 441                 # saturation
 442                 elif encmode == 'sats':
 443                     assert sv_mode is None
 444                     saturation = 1
 445                     sv_mode = 0b10
 446                 elif encmode == 'satu':
 447                     assert sv_mode is None
 448                     sv_mode = 0b10
 449                     saturation = 0
 450                 # predicate zeroing
 451                 elif encmode == 'sz':
 452                     src_zero = 1
 453                 elif encmode == 'dz':
 454                     dst_zero = 1
 455                 # failfirst
 456                 elif encmode.startswith("ff="):
 457                     assert sv_mode is None
 458                     sv_mode = 0b01
 459                     failfirst = decode_ffirst(encmode[3:])
 460                 # predicate-result, interestingly same as fail-first
 461                 elif encmode.startswith("pr="):
 462                     assert sv_mode is None
 463                     sv_mode = 0b11
 464                     predresult = decode_ffirst(encmode[3:])
 465                 # map-reduce mode
 466                 elif encmode == 'mr':
 467                     assert sv_mode is None
 468                     sv_mode = 0b00
 469                     mapreduce = True
 470                 elif encmode == 'crm': # CR on map-reduce
 471                     assert sv_mode is None
 472                     sv_mode = 0b00
 473                     mapreduce_crm = True
 474                 elif encmode == 'svm': # sub-vector mode
 475                     mapreduce_svm = True
 476
 477             # sanity-check that 2Pred mask is same mode
 478             if has_pmask and has_smask:
 479                 assert smmode == pmmode, \
 480                     "predicate masks %s and %s must be same reg type" % \
 481                         (pme, sme)
 482
 483             # sanity-check that twin-predication mask only specified in 2P mode
 484             if ptype == '1P':
 485                 assert has_smask == False, \
 486                     "source-mask can only be specified on Twin-predicate ops"
 487
 488             # construct the mode field, doing sanity-checking along the way
 489
 490             if mapreduce_svm:
 491                 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
 492                 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
 493
 494             if src_zero:
 495                 assert has_smask, "src zeroing requires a source predicate"
 496             if dst_zero:
 497                 assert has_pmask, "dest zeroing requires a dest predicate"
 498
 499             # "normal" mode
 500             if sv_mode is None:
 501                 mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
 502                 sv_mode = 0b00
 503
 504             # "mapreduce" modes
 505             elif sv_mode == 0b00:
 506                 mode |= (0b1<<2) # sets mapreduce
 507                 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
 508                 if mapreduce_crm:
 509                     mode |= (0b1<<4) # sets CRM mode
 510                     assert rc_mode, "CRM only allowed when Rc=1"
 511                 # bit of weird encoding to jam zero-pred or SVM mode in.
 512                 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
 513                 if subvl == 0:
 514                     mode |= (src_zero << 3) # predicate src-zeroing
 515                 elif mapreduce_svm:
 516                     mode |= (1 << 3) # SVM mode
 517
 518             # "failfirst" modes
 519             elif sv_mode == 0b01:
 520                 assert dst_zero == 0, "dest-zero not allowed in failfirst mode"
 521                 if failfirst == 'RC1':
 522                     mode |= (0b1<<4) # sets RC1 mode
 523                     mode |= (src_zero << 3) # predicate src-zeroing
 524                     assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
 525                 elif failfirst == '~RC1':
 526                     mode |= (0b1<<4) # sets RC1 mode...
 527                     mode |= (src_zero << 3) # predicate src-zeroing
 528                     mode |= (0b1<<2) # ... with inversion
 529                     assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
 530                 else:
 531                     assert src_zero == 0, "src-zero not allowed in ffirst BO"
 532                     assert rc_mode, "ffirst BO only possible when Rc=1"
 533                     mode |= (failfirst << 2) # set BO
 534
 535             # "saturation" modes
 536             elif sv_mode == 0b10:
 537                 mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
 538                 mode |= (saturation<<2) # sets signed/unsigned saturation
 539
 540             # "predicate-result" modes.  err... code-duplication from ffirst
 541             elif sv_mode == 0b11:
 542                 assert dst_zero == 0, "dest-zero not allowed in predresult mode"
 543                 if predresult == 'RC1':
 544                     mode |= (0b1<<4) # sets RC1 mode
 545                     mode |= (src_zero << 3) # predicate src-zeroing
 546                     assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
 547                 elif predresult == '~RC1':
 548                     mode |= (0b1<<4) # sets RC1 mode...
 549                     mode |= (src_zero << 3) # predicate src-zeroing
 550                     mode |= (0b1<<2) # ... with inversion
 551                     assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
 552                 else:
 553                     assert src_zero == 0, "src-zero not allowed in pr-mode BO"
 554                     assert rc_mode, "pr-mode BO only possible when Rc=1"
 555                     mode |= (predresult << 2) # set BO
 556
 557             # whewww.... modes all done :)
 558             # now put into svp64_rm
 559             mode |= sv_mode
 560             # mode: bits 19-23
 561             svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE))
 562
 563             # put in predicate masks into svp64_rm
 564             if ptype == '2P':
 565                 # source pred: bits 16-18
 566                 svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE))
 567             # mask mode: bit 0
 568             svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE))
 569             # 1-pred: bits 1-3
 570             svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE))
 571
 572             # and subvl: bits 8-9
 573             svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE))
 574
 575             # put in elwidths
 576             # srcwid: bits 6-7
 577             svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE))
 578             # destwid: bits 4-5
 579             svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE))
 580
 581             # nice debug printout. (and now for something completely different)
 582             # https://youtu.be/u0WOIwlXE9g?t=146
 583             svp64_rm_value = svp64_rm.spr.value
 584             print ("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
 585             print ("    mmode  0    :", bin(mmode))
 586             print ("    pmask  1-3  :", bin(pmask))
 587             print ("    dstwid 4-5  :", bin(destwid))
 588             print ("    srcwid 6-7  :", bin(srcwid))
 589             print ("    subvl  8-9  :", bin(subvl))
 590             print ("    mode   19-23:", bin(mode))
 591             offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
 592             for idx, sv_extra in extras.items():
 593                 if idx is None: continue
 594                 start = (10+idx*offs)
 595                 end = start + offs-1
 596                 print ("    extra%d %2d-%2d:" % (idx, start, end),
 597                         bin(sv_extra))
 598             if ptype == '2P':
 599                 print ("    smask  16-17:", bin(smask))
 600             print ()
 601
 602             # first, construct the prefix from its subfields
 603             svp64_prefix = SVP64PrefixFields()
 604             svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
 605             svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
 606             svp64_prefix.rm.eq(svp64_rm.spr)
 607
 608             # fiinally yield the svp64 prefix and the thingy.  v3.0b opcode
 609             rc = '.' if rc_mode else ''
 610             yield ".long 0x%x" % svp64_prefix.insn.value
 611             yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
 612             print ("new v3.0B fields", v30b_op, v30b_newfields)
 613
 614 if __name__ == '__main__':
 615     lst = ['slw 3, 1, 4',
 616                  'extsw 5, 3',
 617                  'sv.extsw 5, 3',
 618                  'sv.cmpi 5, 1, 3, 2',
 619                  'sv.setb 5, 31',
 620                  'sv.isel 64.v, 3, 2, 65.v',
 621                  'sv.setb/m=r3/sm=1<<r3 5, 31',
 622                  'sv.setb/vec2 5, 31',
 623                  'sv.setb/sw=8/ew=16 5, 31',
 624                  'sv.extsw./ff=eq 5, 31',
 625                  'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31',
 626                  'sv.extsw./pr=eq 5.v, 31',
 627                  'sv.add. 5.v, 2.v, 1.v',
 628                 ]
 629     lst += [
 630                  'sv.stw 5.v, 4(1.v)',
 631                  'sv.ld 5.v, 4(1.v)',
 632                  'setvl. 2, 3, 4, 1, 1',
 633           ]
 634     isa = SVP64Asm(lst)
 635     print ("list", list(isa))
 636     csvs = SVP64RM()