1 # this file has been generated by sv2nmigen
3 from nmigen
import Signal
, Module
, Const
, Cat
, Elaboratable
6 class axi_buffer_rab(Elaboratable
):
9 self
.clk
= Signal() # input
10 self
.rstn
= Signal() # input
11 self
.data_out
= Signal(DATA_WIDTH
) # output
12 self
.valid_out
= Signal() # output
13 self
.ready_in
= Signal() # input
14 self
.valid_in
= Signal() # input
15 self
.data_in
= Signal(DATA_WIDTH
) # input
16 self
.ready_out
= Signal() # output
18 def elaborate(self
, platform
=None):
20 m
.d
.comb
+= self
.full
.eq(self
.None)
21 m
.d
.comb
+= self
.data_out
.eq(self
.None)
22 m
.d
.comb
+= self
.valid_out
.eq(self
.None)
23 m
.d
.comb
+= self
.ready_out
.eq(self
.None)
26 # // Copyright 2018 ETH Zurich and University of Bologna.
27 # // Copyright and related rights are licensed under the Solderpad Hardware
28 # // License, Version 0.51 (the "License"); you may not use this file except in
29 # // compliance with the License. You may obtain a copy of the License at
30 # // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
31 # // or agreed to in writing, software, hardware and materials distributed under
32 # // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
33 # // CONDITIONS OF ANY KIND, either express or implied. See the License for the
34 # // specific language governing permissions and limitations under the License.
36 # //import CfMath::log2;
38 # module axi_buffer_rab
40 # // parameter DATA_WIDTH,
41 # // parameter BUFFER_DEPTH
48 # output logic [DATA_WIDTH-1:0] data_out,
49 # output logic valid_out,
50 # input logic ready_in,
53 # input logic valid_in,
54 # input logic [DATA_WIDTH-1:0] data_in,
55 # output logic ready_out
58 # localparam integer LOG_BUFFER_DEPTH = log2(BUFFER_DEPTH);
60 # // Internal data structures
61 # reg [LOG_BUFFER_DEPTH - 1 : 0] pointer_in; // location to which we last wrote
62 # reg [LOG_BUFFER_DEPTH - 1 : 0] pointer_out; // location from which we last sent
63 # reg [LOG_BUFFER_DEPTH : 0] elements; // number of elements in the buffer
64 # reg [DATA_WIDTH - 1 : 0] buffer [BUFFER_DEPTH - 1 : 0];
70 # assign full = (elements == BUFFER_DEPTH);
72 # always @(posedge clk or negedge rstn)
73 # begin: elements_sequential
78 # // ------------------
79 # // Are we filling up?
80 # // ------------------
82 # if (ready_in && valid_out && (!valid_in || full))
83 # elements <= elements - 1;
85 # else if ((!valid_out || !ready_in) && valid_in && !full)
86 # elements <= elements + 1;
87 # // Else, either one out and one in, or none out and none in - stays unchanged
91 # always @(posedge clk or negedge rstn)
92 # begin: buffers_sequential
95 # for (loop1 = 0 ; loop1 < BUFFER_DEPTH ; loop1 = loop1 + 1)
100 # // Update the memory
101 # if (valid_in && !full)
102 # buffer[pointer_in] <= data_in;
106 # always @(posedge clk or negedge rstn)
115 # // ------------------------------------
116 # // Check what to do with the input side
117 # // ------------------------------------
118 # // We have some input, increase by 1 the input pointer
119 # if (valid_in && !full)
121 # if (pointer_in == $unsigned(BUFFER_DEPTH - 1))
124 # pointer_in <= pointer_in + 1;
126 # // Else we don't have any input, the input pointer stays the same
128 # // -------------------------------------
129 # // Check what to do with the output side
130 # // -------------------------------------
131 # // We had pushed one flit out, we can try to go for the next one
132 # if (ready_in && valid_out)
134 # if (pointer_out == $unsigned(BUFFER_DEPTH - 1))
137 # pointer_out <= pointer_out + 1;
139 # // Else stay on the same output location
143 # // Update output ports
144 # assign data_out = buffer[pointer_out];
145 # assign valid_out = (elements != 0);
147 # assign ready_out = ~full;