svp64-primer/acronyms.tex

   1 \section{List of Acronyms}
   2 \begin{acronym}
   3         \acro{ASIC}{Application Specific Integrated Circuit}
   4         \acro{AVX-512}{Intel Advanced Vector Extensions 512-bit}
   5         \acro{CPU}{Central Processing Unit}
   6         \acro{DCT}{Discrete Cosine Transform}
   7         \acro{DSP}{Digital Signal Processors}
   8         \acro{DAXPY}{Double-Precision aX Plus Y ($aX+Y$)}
   9         \acro{FFT}{Fast Fourier Transform}
  10         \acro{IA-32}{Intel Architecture 32-bit or i386}
  11         \acro{ISA}{Instruction Set Architecture}
  12         \acro{MMX}{Intel's first SIMD implementation}
  13         \acro{RVV}{RISC-V Vector extension}
  14         \acro{SIMD}{Single Instruction Multiple Data}
  15         \acro{SWAR}{SIMD Within A Register (see Flynn's Taxonomy)}
  16         \acro{SV}{(Scalable) Simple Vectorisation or Simple-V}
  17         \acro{SVE2}{ARM Scalable Vector Extension version two}
  18         \acro{SVP64}{Simple-V with Prefixing of Power ISA, 64-bits in length}
  19         \acro{VLIW}{Very Long Instruction Word}
  20         \acro{VSX}{128-bit Packed SIMD Extension to the Power ISA}
  21 \end{acronym}