add page use ulx3s fpga gpio pins for Libre-SOC JTAG connections to STLINKV2
[libreriscv.git] / tplaten.mdwn
1 # Tobias Platen
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3 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=platen&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
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5 ## Pending
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7 ### NLNet 2019 Coriolis2 Layout proposal 2019-10-029 Date 20mar2020
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9 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> EUR200
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11 # Status tracking
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13 move things along from one stage to the next
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15 ## Currently working on
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17 * https://bugs.libre-soc.org/show_bug.cgi?id=465
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19 ## Completed
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21 completed but not yet submitted:
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23 ## Submitted for NLNet RFP
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25 submitted but not confirmed paid:
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27 ## Paid
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29 donation from NLNet confirmed received:
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