1 # // Copyright 2018 ETH Zurich and University of Bologna.
2 # // Copyright and related rights are licensed under the Solderpad Hardware
3 # // License, Version 0.51 (the "License"); you may not use this file except in
4 # // compliance with the License. You may obtain a copy of the License at
5 # // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
6 # // or agreed to in writing, software, hardware and materials distributed under
7 # // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
8 # // CONDITIONS OF ANY KIND, either express or implied. See the License for the
9 # // specific language governing permissions and limitations under the License.
13 # parameter ADDR_WIDTH_PHYS = 40,
14 # parameter ADDR_WIDTH_VIRT = 32
17 # input logic [ADDR_WIDTH_VIRT-1:0] cfg_min,
18 # input logic [ADDR_WIDTH_VIRT-1:0] cfg_max,
19 # input logic [ADDR_WIDTH_PHYS-1:0] cfg_offset,
20 # input logic cfg_wen,
21 # input logic cfg_ren,
23 # input logic in_trans_type,
24 # input logic [ADDR_WIDTH_VIRT-1:0] in_addr_min,
25 # input logic [ADDR_WIDTH_VIRT-1:0] in_addr_max,
26 # output logic out_hit,
27 # output logic out_prot,
28 # output logic [ADDR_WIDTH_PHYS-1:0] out_addr
30 # this file has been generated by sv2nmigen
32 from nmigen
import Signal
, Module
, Const
, Cat
, Elaboratable
35 class rab_slice(Elaboratable
):
37 def __init__(self
, params
): # pass config object
40 self
.cfg_min
= Signal(params
.ADDR_WIDTH_VIRT
) # input
41 self
.cfg_max
= Signal(params
.ADDR_WIDTH_VIRT
) # input
42 self
.cfg_offset
= Signal(params
.ADDR_WIDTH_PHYS
) # input
43 self
.cfg_wen
= Signal() # input
44 self
.cfg_ren
= Signal() # input
45 self
.cfg_en
= Signal() # input
46 self
.in_trans_type
= Signal() # input
47 self
.in_addr_min
= Signal(params
.ADDR_WIDTH_VIRT
) # input
48 self
.in_addr_max
= Signal(params
.ADDR_WIDTH_VIRT
) # input
49 self
.out_hit
= Signal() # output
50 self
.out_prot
= Signal() # output
51 self
.out_addr
= Signal(params
.ADDR_WIDTH_PHYS
) # output
53 def elaborate(self
, platform
=None):
55 min_above_min
= Signal()
56 min_below_max
= Signal()
57 max_below_max
= Signal()
59 # assign min_above_min = (in_addr_min >= cfg_min) ? 1'b1 : 1'b0;
60 # assign min_below_max = (in_addr_min <= cfg_max) ? 1'b1 : 1'b0;
61 # assign max_below_max = (in_addr_max <= cfg_max) ? 1'b1 : 1'b0;
62 # assign out_hit = cfg_en & min_above_min & min_below_max & max_below_max;
63 # assign out_prot = out_hit & ((in_trans_type & ~cfg_wen) | (~in_trans_type & ~cfg_ren));
64 # assign out_addr = in_addr_min - cfg_min + cfg_offset;
66 min_above_min
.eq(self
.in_addr_min
>= self
.cfg_min
),
67 min_below_max
.eq(self
.in_addr_min
<= self
.cfg_max
),
68 max_below_max
.eq(self
.in_addr_max
<= self
.cfg_max
),
69 self
.out_hit
.eq(self
.cfg_en
& min_above_min
&
70 min_below_max
& max_below_max
),
71 self
.out_prot
.eq(self
.out_hit
& (
72 (self
.in_trans_type
& ~self
.cfg_wen
) |
(~self
.in_trans_type
& ~self
.cfg_ren
))),
73 self
.out_addr
.eq(self
.in_addr_min
- self
.cfg_min
+ self
.cfg_offset
)