zfpacc_proposal.mdwn

   1 # FP Accuracy proposal
   2
   3 Credits:
   4
   5 * Bruce Hoult
   6 * Allen Baum
   7 * Dan Petroski
   8 * Jacob Lifshay
   9
  10 TODO: complete writeup
  11
  12 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-August/002400.html>
  13 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-August/002412.html>
  14
  15 Zfpacc: a proposal to allow implementations to dynamically set the
  16 bit-accuracy of floating-point results, trading speed (reduced latency)
  17 *at runtime* for accuracy (higher latency).  IEEE754 format is preserved:
  18 instruction operand and result format requirements are unmodified by
  19 this proposal.  Only ULP (Unit in Last Place) of the instruction *result*
  20 is permitted to meet alternative accuracy requirements, whilst still
  21 retaining the instruction's requested format.
  22
  23 This proposal is *only* suitable for adding pre-existing accuracy standards
  24 where it is clearly established, well in advance of applications being
  25 written that conform to that standard, that dealing with variations in
  26 accuracy across hardware implementations is the responsibility of the
  27 application writer.  This is the case for both Vulkan and OpenCL.
  28
  29 This proposal is *not* suitable for inclusion of "de-facto" (proprietary)
  30 accuracy standards (historic IBM Mainframe vs Ahmdahl incompatibility)
  31 where there was no prior agreement or notification to applications
  32 writers that variations in accuracy across hardware implementations
  33 would occur.  In the unlikely event that they *are* ever to be included
  34 (n the future, rather than as a Custom Extension, then, unlike Vulkan
  35 and OpenCL, they must **only** be added as "bit-for-bit compatible".
  36
  37 # Extension of FCSR
  38
  39 Zfpacc would use some of the the reserved bits of FCSR.  It would be treated
  40 very similarly to how dynamic frm is treated.
  41
  42 frm is treated as follows:
  43
  44 * Floating-point operations use either a static rounding mode encoded
  45   in the instruction, or a dynamic rounding mode held in frm.
  46 * Rounding modes are encoded as shown in Table 11.1 of the RISC-V ISA Spec
  47 * A value of 111 in the instruction’s rm field selects the dynamic rounding
  48   mode held in frm. If frm is set to an invalid value (101–111),
  49   any subsequent attempt to execute a floating-point operation with a
  50   dynamic rounding mode will raise an illegal instruction exception.
  51
  52 If we wish to support up to 4 accuracy modes, that would require 2 'fam'
  53 bits.  The Default would be IEEE754-compliant, encoded as 00.  This means
  54 that all current hardware would be compliant with the default mode.
  55
  56 Unsupported modes cause a trap to allow emulation where traps are supported.
  57 Emulation of unsupported modes would be required for UNIX platforms.
  58 As with frm, an implementation may choose to support any permutation
  59 of dynamic fam-instruction pairs. It will illegal-instruction trap upon
  60 executing an unsupported fam-instruction pair.  The implementation can
  61 then emulate the accuracy mode required.
  62
  63 If the bits are in FCSR, then the switch itself would be exposed to
  64 user mode.  User-mode would not be able to detect emulation vs hardware
  65 supported instructions, however (by design).  That would require some
  66 platform-specific code.
  67
  68 Emulation of unsupported modes would be required for unix platforms.
  69
  70 TODO:
  71
  72 A mechanism for user mode code to detect which modes are emulated
  73 (csr? syscall?) (if the supervisor decides to make the emulation visible)
  74 that would allow user code to switch to faster software implementations
  75 if it chooses to.
  76
  77 TODO:
  78
  79 Choose which accuracy modes are required
  80
  81     Which accuracy modes should be included is a question outside of
  82     my expertise and would require a literature review of instruction
  83     frequency in key workloads, PPA analysis of simple and advanced
  84     implementations, etc.
  85
  86 TODO: reduced accuracy
  87
  88     I don't see why Unix should be required to emulate some arbitrary
  89     reduced accuracy ML mode.  My guess would be that Unix Platform Spec
  90     requires support for IEEE, whereas arbitrary ML platform requires
  91     support for Mode XYZ.  Of course, implementations of either platform
  92     would be free to support any/all modes that they find valuable.
  93     Compiling for a specific platform means that support for required
  94     accuracy modes is guaranteed (and therefore does not need discovery
  95     sequences), while allowing portable code to execute discovery
  96     sequences to detect support for alternative accuracy modes.
  97
  98 # Dynamic accuracy CSR <a name="dynamic"></a>
  99
 100 FCSR to be modified to include accuracy bits:
 101
 102 | 31....11 | 10..8  | 7..5 | 4....0 |
 103 | -------- | ------ | ---- | ------ |
 104 | reserved | facc   | frm  | fflags |
 105
 106 The values for the field facc to include the following:
 107
 108 | facc  | mode    | description         |
 109 | ----- | ------- | ------------------- |
 110 | 0b000 | IEEE754 | correctly rounded   |
 111 | 0b010 | ULP<1   | Unit Last Place < 1 |
 112 | 0b100 | Vulkan  | Vulkan compliant    |
 113 | 0b110 | Appx    | Machine Learning
 114
 115 (TODO: review alternative idea: ULP0.5, ULP1, ULP2, ULP4, ULP16)
 116
 117 Notes:
 118
 119 * facc=0 to match current RISC-V behaviour, where these bits were formerly reserved and set to zero.
 120 * The format of the operands and result remain the same for
 121 all opcodes. The only change is in the *accuracy* of the result, not
 122 its format.
 123 * facc sets the *minimum* accuracy. It is acceptable to provide *more* accurate results than is requested by a given facc mode (although, clearly, the opportunity for reduced power and latency would be missed).
 124
 125 ## Discussion
 126
 127 maybe a solution would be to add an extra field to the fp control csr
 128 to allow selecting one of several accurate or fast modes:
 129
 130 - machine-learning-mode: fast as possible
 131   (maybe need additional requirements such as monotonicity for atanh?)
 132 - GPU-mode: accurate to within a few ULP
 133   (see Vulkan, OpenGL, and OpenCL specs for accuracy guidelines)
 134 - almost-accurate-mode: accurate to <1 ULP
 135      (would 0.51 or some other value be better?)
 136 - fully-accurate-mode: correctly rounded in all cases
 137 - maybe more modes?
 138
 139 extra mode suggestions:
 140
 141     it might be reasonable to add a mode saying you're prepared to accept
 142     worse then 0.5 ULP accuracy, perhaps with a few options: 1, 2, 4,
 143     16 or something like that.
 144
 145 Question: should better accuracy than is requested be permitted? Example:
 146 Ahmdahl-370 issues.
 147
 148 Comments:
 149
 150     Yes, embedded systems typically can do with 12, 16 or 32 bit
 151     accuracy. Rarely does it require 64 bits. But the idea of making
 152     a low power 32 bit FPU/DSP that can accommodate 64 bits is already
 153     being done in other designs such as PIC etc I believe. For embedded
 154     graphics 16 bit is more than adequate. In fact, Cornell had a very
 155     innovative 18-bit floating point format described here (useful for
 156     FPGA designs with 18-bit DSPs):
 157
 158     <https://people.ece.cornell.edu/land/courses/ece5760/FloatingPoint/index.html>
 159
 160     A very interesting GPU using the 18-bit FPU is also described here:
 161
 162     <https://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/f2008/ap328_sjp45/website/hardwaredesign.html>
 163
 164     There are also 8 and 9-bit floating point formats that could be useful
 165
 166     <https://en.wikipedia.org/wiki/Minifloat>
 167
 168 ### function accuracy in standards (opencl, vulkan)
 169
 170 [[resources]] for OpenCL and Vulkan
 171
 172 Vulkan requires full ieee754 precision for all F/D instructions except for fdiv and fsqrt.
 173
 174 <https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/chap40.html#spirvenv-precision-operation>
 175
 176 Source is here:
 177 <https://github.com/KhronosGroup/Vulkan-Docs/blob/master/appendices/spirvenv.txt#L1172>
 178
 179 OpenCL slightly different, suggest adding as an extra entry.
 180
 181 <https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html#relative-error-as-ulps>
 182
 183 Link, finds version 2.1 of opencl environment specification, table 8.4.1 however needs checking if it is the same as the above, which has "SPIRV" in it and is 2.2 not 2.1
 184
 185 https://www.google.com/search?q=opencl+environment+specification
 186
 187 2.1 superceded by 2.2
 188 <https://github.com/KhronosGroup/OpenCL-Docs/blob/master/env/numerical_compliance.asciidoc>
 189
 190 ### Compliance
 191
 192 Dan Petroski:
 193
 194     It’s a bit more complicated than that. Different FP
 195     representations/algorithms have different quantization ranges, so you
 196     can get more or less precise depending on how large the arguments are.
 197
 198     For instance, machine A can compute within ULP3 from 0 to 10000, but
 199     ULP2 from 10000 upwards. Machine B can compute within ULP2 from 0 to
 200     6000, then ULP3 for 6000+. How do you design a compliance suite which
 201     guarantees behavior across all fpaccs?
 202
 203 and from Allen Baum:
 204
 205     In the example above, you'd need a ratified spec with the defined
 206     ranges  (possbily per range and per op) - and then implementations
 207     would need to at least meet that spec (but could be more accurate)
 208
 209     so - not impossible, but a lot more work to write different kinds
 210     of tests than standard IEEE compatible test would have.
 211
 212     And, by the way, if you want it to be a ratified spec, it needs a
 213     compliance suite, and whoever has defined the spec is responsible
 214     for writing it.,
 215