zfpacc_proposal.mdwn

   1 # FP Accuracy proposal
   2
   3 TODO: writeup
   4 <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-August/002400.html>
   5
   6     A natural place for a standard reduced accuracy extension "Zfpacc"
   7     would be in the reserved bits of FCSR.  It could be treated very
   8     similarly to how dynamic frm is treated now. Currently, there are 5
   9     bits of fflags, 3 bits of frm and 24 Reserved bits. The L (decimal
  10     floating-point) extension will presumably use some, but not all of
  11     them. I'm unable to find any public proposals for L bit encodings
  12     in FCSR.
  13
  14     For reference, frm is treated as follows: Floating-point operations
  15     use either a static rounding mode encoded in the instruction, or
  16     a dynamic rounding mode held in frm. Rounding modes are encoded
  17     as shown in Table 11.1. A value of 111 in the instruction’s rm
  18     field selects the dynamic rounding mode held in frm. If frm is set
  19     to an invalid value (101–111), any subsequent attempt to execute
  20     a floating-point operation with a dynamic rounding mode will raise
  21     an illegal instruction exception.
  22
  23     Let's say that we wish to support up to 4 accuracy modes -- 2 'fam'
  24     bits.  Default would be IEEE-compliant, encoded as 00.  This means
  25     that all current hardware would be compliant with the default mode.
  26
  27     the unsupported modes would cause a trap to allow emulation where
  28     traps are supported. emulation of unsupported modes would be required
  29     for unix platforms.
  30
  31     As with frm, an implementation can choose to support any permutation
  32     of dynamic fam-instruction pairs. It will illegal-instruction
  33     trap upon executing an unsupported fam-instruction pair.
  34     The implementation can then emulate the accuracy mode required.
  35
  36     there would be a mechanism for user mode code to detect which modes
  37     are emulated (csr? syscall?) (if the supervisor decides to make the
  38     emulation visible) that would allow user code to switch to faster
  39     software implementations if it chooses to.
  40
  41     If the bits are in FCSR, then the switch itself would be exposed
  42     to user mode.  User-mode would not be able to detect emulation vs
  43     hardware supported instructions, however (by design).  That would
  44     require some platform-specific code.
  45
  46     Now, which accuracy modes should be included is a question outside
  47     of my expertise and would require a literature review of instruction
  48     frequency in key workloads, PPA analysis of simple and advanced
  49     implementations, etc.  (Thanks for the insights, Mitch!)
  50
  51     emulation of unsupported modes would be required for unix platforms.
  52
  53     I don't see why Unix should be required to emulate some arbitrary
  54     reduced accuracy ML mode.  My guess would be that Unix Platform Spec
  55     requires support for IEEE, whereas arbitrary ML platform requires
  56     support for Mode XYZ.  Of course, implementations of either platform
  57     would be free to support any/all modes that they find valuable.
  58     Compiling for a specific platform means that support for required
  59     accuracy modes is guaranteed (and therefore does not need discovery
  60     sequences), while allowing portable code to execute discovery
  61     sequences to detect support for alternative accuracy modes.