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add alternative pc_reset argument to issuer_verilog.py
[soc.git]
/
Makefile
diff --git
a/Makefile
b/Makefile
index e89ad1d9fe5807c568a2d20e3d48a4f91a0bd1ca..f318ae315da4e8b0b21fe6d2ab1f44fdb9817c1a 100644
(file)
--- a/
Makefile
+++ b/
Makefile
@@
-63,6
+63,12
@@
microwatt_external_core:
python3 src/soc/simple/issuer_verilog.py --microwatt-compat --enable-mmu \
external_core_top.v
python3 src/soc/simple/issuer_verilog.py --microwatt-compat --enable-mmu \
external_core_top.v
+microwatt_external_core_spi:
+ python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+ --enable-mmu \
+ --pc-reset 0x10000000 \
+ external_core_top.v
+
# build the litex libresoc SoC without 4k SRAMs
ls180_verilog_build: ls180_verilog
make -C soc/soc/litex/florent ls180
# build the litex libresoc SoC without 4k SRAMs
ls180_verilog_build: ls180_verilog
make -C soc/soc/litex/florent ls180