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modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)
[riscv-tests.git]
/
isa
/
macros
/
simplev
/
sv_test_macros.h
diff --git
a/isa/macros/simplev/sv_test_macros.h
b/isa/macros/simplev/sv_test_macros.h
index b3b06c03127fa0d0bf709b4797141890dd2bfdab..a480bd6648b763fef1c52adaa6363ba534413c89 100644
(file)
--- a/
isa/macros/simplev/sv_test_macros.h
+++ b/
isa/macros/simplev/sv_test_macros.h
@@
-22,8
+22,8
@@
#define CLR_SV_CSRS( ) csrrw x0, 0x4c0, 0
#define CLR_SV_PRED_CSRS( ) csrrw x0, 0x4c8, 0
#define CLR_SV_CSRS( ) csrrw x0, 0x4c0, 0
#define CLR_SV_PRED_CSRS( ) csrrw x0, 0x4c8, 0
-#define SET_SV_MVL( val ) csrrwi x0, 0x4f
2, val
-#define SET_SV_VL( val ) csrrwi x0, 0x4f0,
val
+#define SET_SV_MVL( val ) csrrwi x0, 0x4f
1, (val-1)
+#define SET_SV_VL( val ) csrrwi x0, 0x4f0,
(val-1)
#define SV_LD_DATA( reg, from, offs ) \
la x1, from; \
#define SV_LD_DATA( reg, from, offs ) \
la x1, from; \