modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index b3b06c03127fa0d0bf709b4797141890dd2bfdab..a480bd6648b763fef1c52adaa6363ba534413c89 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -22,8 +22,8 @@
 #define CLR_SV_CSRS( ) csrrw   x0, 0x4c0, 0
 #define CLR_SV_PRED_CSRS( ) csrrw   x0, 0x4c8, 0
 
-#define SET_SV_MVL( val ) csrrwi   x0, 0x4f2, val
-#define SET_SV_VL( val )  csrrwi   x0, 0x4f0, val
+#define SET_SV_MVL( val ) csrrwi   x0, 0x4f1, (val-1)
+#define SET_SV_VL( val )  csrrwi   x0, 0x4f0, (val-1)
 
 #define SV_LD_DATA( reg, from, offs ) \
         la      x1, from; \

diff --git a/isa/rv64uc/Makefrag.sv b/isa/rv64uc/Makefrag.sv
index 52571ae6d61d2dba03c85e4127016ff087d436db..b97e6a078c0fffcccc6ac6a28a22be53bae28180 100644 (file)
--- a/isa/rv64uc/Makefrag.sv
+++ b/isa/rv64uc/Makefrag.sv
@@ -8,6 +8,7 @@ rv64uc_sv_tests = \
        sv_c_lwsp \
        sv_c_lwsp_predication \
        sv_c_swsp \
+       sv_c_beqz \
 
 rv64uc_p_tests = $(addprefix rv64uc-p-, $(rv64uc_sv_tests))
 rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sv_tests))

diff --git a/isa/rv64uc/sv_c_beqz.S b/isa/rv64uc/sv_c_beqz.S
new file mode 100644 (file)
index 0000000..8cf7fe8
--- /dev/null
+++ b/isa/rv64uc/sv_c_beqz.S
@@ -0,0 +1,74 @@
+#include "riscv_test.h"
+#include "sv_test_macros.h"
+
+RVTEST_RV64U        # Define TVM used by program.
+
+
+# SV test: vector-vector add different rd and rs1
+#
+# sets up x6 and x7 with data, sets VL to 2, and carries out
+# an "x3 = 1 + x6".  which actually means "x3 = 1 + x6 *AND* x4 = 1 + x7"
+
+# Test code region.
+RVTEST_CODE_BEGIN   # Start of test code.
+
+  .align 2
+  .option push
+  .option norvc
+
+        li          a3, 0x3
+        li          a4, 0x0
+
+        SET_SV_MVL(2)
+        SET_SV_2CSRS( SV_REG_CSR(1, 10, 0, 3, 1),
+                      SV_REG_CSR(1, 0 , 0, 0, 1) )
+       SET_SV_2PREDCSRS(                              \
+                      SV_PRED_CSR(1, 10, 0, 0, 13, 0),  \
+                      SV_PRED_CSR(1,  0, 0, 0, 14, 0) );\
+
+        li          x3, 0 
+        li          x4, 0
+
+        SET_SV_VL(2)
+
+  .option push;
+  .option rvc; 
+  .align 2; 
+
+        c.beqz    a0,here
+
+  .option pop;
+
+here:
+
+        CLR_SV_CSRS()
+        SET_SV_VL(1)
+        SET_SV_MVL(1)
+
+        TEST_SV_IMM(a4, 0x3) 
+
+  .option pop;
+        RVTEST_PASS           # Signal success.
+fail:
+        RVTEST_FAIL
+RVTEST_CODE_END     # End of test code.
+
+# Input data section.
+# This section is optional, and this data is NOT saved in the output.
+.data
+        .align 3
+testdata:
+        .dword 1001
+        .dword 0
+        .dword 0
+        .dword 1002
+
+# Output data section.
+RVTEST_DATA_BEGIN   # Start of test output data region.
+        .align 3
+result:
+        .dword -1
+        .dword -1
+        .dword -1
+RVTEST_DATA_END     # End of test output data region.
+

diff --git a/isa/rv64uc/sv_c_lwsp.S b/isa/rv64uc/sv_c_lwsp.S
index e30d11abac647043d088657ce161e22b7b152be9..38dcaa2135ce134ce287e7d9c7374a248b389444 100644 (file)
--- a/isa/rv64uc/sv_c_lwsp.S
+++ b/isa/rv64uc/sv_c_lwsp.S
@@ -37,9 +37,9 @@ RVTEST_CODE_BEGIN
   .option pop
 
 
-        SET_SV_VL(0)
+        SET_SV_VL(1)
         CLR_SV_CSRS()
-        SET_SV_MVL(0)
+        SET_SV_MVL(1)
 
   mv sp, a1
 

diff --git a/isa/rv64uc/sv_c_lwsp_predication.S b/isa/rv64uc/sv_c_lwsp_predication.S
index a0a293434e492d9ae34277a71cd6b3855418fec1..0885dd7923cb9ac78a1df444637ab1b038fd87e8 100644 (file)
--- a/isa/rv64uc/sv_c_lwsp_predication.S
+++ b/isa/rv64uc/sv_c_lwsp_predication.S
@@ -45,9 +45,9 @@ RVTEST_CODE_BEGIN
   .option pop
 
 
-        SET_SV_VL(0)
+        SET_SV_VL(1)
         CLR_SV_CSRS()
-        SET_SV_MVL(0)
+        SET_SV_MVL(1)
 
   mv sp, a6
 

diff --git a/isa/rv64uc/sv_c_mv.S b/isa/rv64uc/sv_c_mv.S
index 11a042b920aa4fb18efb2b7763bb55d61924b981..ce8dd412a3e56572a7bca2b1f974f173f40da7a4 100644 (file)
--- a/isa/rv64uc/sv_c_mv.S
+++ b/isa/rv64uc/sv_c_mv.S
@@ -31,9 +31,9 @@ RVTEST_CODE_BEGIN   # Start of test code.
         c.mv    x3, x6
         .option norvc
 
-        SET_SV_VL(0)
+        SET_SV_VL(1)
         CLR_SV_CSRS()
-        SET_SV_MVL(0)
+        SET_SV_MVL(1)
 
         TEST_SV_IMM(x3, 1001) # should not be modified
         TEST_SV_IMM(x4, 41)

diff --git a/isa/rv64uc/sv_c_mv_predication.S b/isa/rv64uc/sv_c_mv_predication.S
index fc0bb7498ba41933cc260819773cd5560442e0aa..7345de0facb6800acd8eed103c0245e249392e99 100644 (file)
--- a/isa/rv64uc/sv_c_mv_predication.S
+++ b/isa/rv64uc/sv_c_mv_predication.S
@@ -28,9 +28,9 @@ RVTEST_RV64U        # Define TVM used by program.
         c.mv    x3, x6;                                \
         .option norvc;                                 \
                                                        \
-        SET_SV_VL(0);                                  \
+        SET_SV_VL(1);                                  \
         CLR_SV_CSRS();                                 \
-        SET_SV_MVL(0);                                 \
+        SET_SV_MVL(1);                                 \
                                                        \
         TEST_SV_IMM(x3, expect1);                      \
         TEST_SV_IMM(x4, expect2);                      \

diff --git a/isa/rv64uc/sv_c_swsp.S b/isa/rv64uc/sv_c_swsp.S
index 7990707e7c1ce2ac5a6f7936c3a4d69fa217ac2a..622ca9eb37f95e2d0d9d3326e06fe12b9491490a 100644 (file)
--- a/isa/rv64uc/sv_c_swsp.S
+++ b/isa/rv64uc/sv_c_swsp.S
@@ -37,9 +37,9 @@ RVTEST_CODE_BEGIN
   .option pop
 
 
-        SET_SV_VL(0)
+        SET_SV_VL(1)
         CLR_SV_CSRS()
-        SET_SV_MVL(0)
+        SET_SV_MVL(1)
 
   mv sp, a1
 

diff --git a/isa/rv64ud/sv_fadd.S b/isa/rv64ud/sv_fadd.S
index 9057dff8e1c2ef531fd871bffb9ef07512a9ee64..5818a2b8a59efe1c19faa446693b666e79d4bcb8 100644 (file)
--- a/isa/rv64ud/sv_fadd.S
+++ b/isa/rv64ud/sv_fadd.S
@@ -29,8 +29,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
         fadd.d f2, f2, f6;
 
         CLR_SV_CSRS()
-        SET_SV_VL(0)
-        SET_SV_MVL(0)
+        SET_SV_VL(1)
+        SET_SV_MVL(1)
 
         TEST_SV_FD(0, f1, testdata+64, 0) 
         TEST_SV_FD(0, f2, testdata+72, 0) 

diff --git a/isa/rv64ui/sv_addi.S b/isa/rv64ui/sv_addi.S
index b73db85a31c71660265897cc16f018842c04d91f..c0fdb5abbeaaba2454aa217ad634890cea2f9951 100644 (file)
--- a/isa/rv64ui/sv_addi.S
+++ b/isa/rv64ui/sv_addi.S
@@ -24,8 +24,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
         addi    x3, x3, 1
 
         CLR_SV_CSRS()
-        SET_SV_VL(0)
-        SET_SV_MVL(0)
+        SET_SV_VL(1)
+        SET_SV_MVL(1)
 
         TEST_SV_IMM(x2, 1001) # should not be modified
         TEST_SV_IMM(x3, 42)

diff --git a/isa/rv64ui/sv_addi_predicated.S b/isa/rv64ui/sv_addi_predicated.S
index 46246ea849eb0ebb92077526fc549dc4eaae4af5..8bea7f8f75b12b4bacbd4b0cf8e1bdbbb60ec7b4 100644 (file)
--- a/isa/rv64ui/sv_addi_predicated.S
+++ b/isa/rv64ui/sv_addi_predicated.S
@@ -20,8 +20,8 @@ RVTEST_RV64U        # Define TVM used by program.
         addi    x3, x3, 1;                              \
                                                         \
         CLR_SV_CSRS();                                  \
-        SET_SV_VL( 0);                                   \
-        SET_SV_MVL( 0);                                  \
+        SET_SV_VL( 1);                                   \
+        SET_SV_MVL( 1);                                  \
                                                         \
         TEST_SV_IMM( x2, 1001);                         \
         TEST_SV_IMM( x3, expect1);                       \

diff --git a/isa/rv64ui/sv_addi_redirect.S b/isa/rv64ui/sv_addi_redirect.S
index 74d41e0c57d32886266a36daa082cbe02ea520e0..aeb404d43dc94f60d2cd06d00908b15e0258197f 100644 (file)
--- a/isa/rv64ui/sv_addi_redirect.S
+++ b/isa/rv64ui/sv_addi_redirect.S
@@ -26,8 +26,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
         addi    x16, x16, 1
 
         CLR_SV_CSRS()
-        SET_SV_VL(0)
-        SET_SV_MVL(0)
+        SET_SV_VL(1)
+        SET_SV_MVL(1)
 
         TEST_SV_IMM(x2, 1001) # should not be modified
         TEST_SV_IMM(x3, 42)

diff --git a/isa/rv64ui/sv_addi_scalar_src.S b/isa/rv64ui/sv_addi_scalar_src.S
index e17df23dc92cfca61a2ff0a43b91c97a34e91955..edb0345febc8546daa14660aa5735e66c4437d1c 100644 (file)
--- a/isa/rv64ui/sv_addi_scalar_src.S
+++ b/isa/rv64ui/sv_addi_scalar_src.S
@@ -27,8 +27,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
         addi    x3, x6, 1 # x3 = x6+1 *AND* x4 = x6+1
 
         CLR_SV_CSRS()
-        SET_SV_VL(0)
-        SET_SV_MVL(0)
+        SET_SV_VL(1)
+        SET_SV_MVL(1)
 
         TEST_SV_IMM(x2, 1001) # should not be modified
         TEST_SV_IMM(x3, 42)

diff --git a/isa/rv64ui/sv_addi_vector_vector.S b/isa/rv64ui/sv_addi_vector_vector.S
index 8594ba7566f38efe007411888f50862eee5c6d60..b616e13ddd044db56bd4d5dec3f65d157664a79d 100644 (file)
--- a/isa/rv64ui/sv_addi_vector_vector.S
+++ b/isa/rv64ui/sv_addi_vector_vector.S
@@ -28,8 +28,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
         addi    x3, x6, 1
 
         CLR_SV_CSRS()
-        SET_SV_VL(0)
-        SET_SV_MVL(0)
+        SET_SV_VL(1)
+        SET_SV_MVL(1)
 
         TEST_SV_IMM(x2, 1001) # should not be modified
         TEST_SV_IMM(x3, 42)

diff --git a/isa/rv64ui/sv_beq.S b/isa/rv64ui/sv_beq.S
index 2c38e224b4ffb39d1e910f5f7cef5eb3f7eef852..d0129481c7a82dfa186989890fc45163dab4dcb0 100644 (file)
--- a/isa/rv64ui/sv_beq.S
+++ b/isa/rv64ui/sv_beq.S
@@ -34,8 +34,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
 here:
 
         CLR_SV_CSRS()
-        SET_SV_VL(0)
-        SET_SV_MVL(0)
+        SET_SV_VL(1)
+        SET_SV_MVL(1)
 
         TEST_SV_IMM(a4, 0x3)