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modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)
[riscv-tests.git]
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isa
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rv64ui
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sv_beq.S
2018-10-16
Luke Kenneth Casso...
modified VL and MVL CSRs to range from 1-XLEN rather...
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2018-10-09
Luke Kenneth Casso...
add sv vectorised predicated beq test
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