modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)

[riscv-tests.git] / isa / rv64ui / sv_beq.S

diff --git a/isa/rv64ui/sv_beq.S b/isa/rv64ui/sv_beq.S
index 2c38e224b4ffb39d1e910f5f7cef5eb3f7eef852..d0129481c7a82dfa186989890fc45163dab4dcb0 100644 (file)
--- a/isa/rv64ui/sv_beq.S
+++ b/isa/rv64ui/sv_beq.S
@@ -34,8 +34,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
 here:
 
         CLR_SV_CSRS()
-        SET_SV_VL(0)
-        SET_SV_MVL(0)
+        SET_SV_VL(1)
+        SET_SV_MVL(1)
 
         TEST_SV_IMM(a4, 0x3)