isa/rv64uc/sv_c_beqz.S

   1 #include "riscv_test.h"
   2 #include "sv_test_macros.h"
   3
   4 RVTEST_RV64U        # Define TVM used by program.
   5
   6
   7 # SV test: vector-vector add different rd and rs1
   8 #
   9 # sets up x6 and x7 with data, sets VL to 2, and carries out
  10 # an "x3 = 1 + x6".  which actually means "x3 = 1 + x6 *AND* x4 = 1 + x7"
  11
  12 # Test code region.
  13 RVTEST_CODE_BEGIN   # Start of test code.
  14
  15   .align 2
  16   .option push
  17   .option norvc
  18
  19         li          a3, 0x3
  20         li          a4, 0x0
  21
  22         SET_SV_MVL(2)
  23         SET_SV_2CSRS( SV_REG_CSR(1, 10, 0, 3, 1),
  24                       SV_REG_CSR(1, 0 , 0, 0, 1) )
  25        SET_SV_2PREDCSRS(                              \
  26                       SV_PRED_CSR(1, 10, 0, 0, 13, 0),  \
  27                       SV_PRED_CSR(1,  0, 0, 0, 14, 0) );\
  28
  29         li          x3, 0
  30         li          x4, 0
  31
  32         SET_SV_VL(2)
  33
  34   .option push;
  35   .option rvc;
  36   .align 2;
  37
  38         c.beqz    a0,here
  39
  40   .option pop;
  41
  42 here:
  43
  44         CLR_SV_CSRS()
  45         SET_SV_VL(1)
  46         SET_SV_MVL(1)
  47
  48         TEST_SV_IMM(a4, 0x3)
  49
  50   .option pop;
  51         RVTEST_PASS           # Signal success.
  52 fail:
  53         RVTEST_FAIL
  54 RVTEST_CODE_END     # End of test code.
  55
  56 # Input data section.
  57 # This section is optional, and this data is NOT saved in the output.
  58 .data
  59         .align 3
  60 testdata:
  61         .dword 1001
  62         .dword 0
  63         .dword 0
  64         .dword 1002
  65
  66 # Output data section.
  67 RVTEST_DATA_BEGIN   # Start of test output data region.
  68         .align 3
  69 result:
  70         .dword -1
  71         .dword -1
  72         .dword -1
  73 RVTEST_DATA_END     # End of test output data region.
  74