b73db85a31c71660265897cc16f018842c04d91f
[riscv-tests.git] / isa / rv64ui / sv_addi.S
1 #include "riscv_test.h"
2 #include "sv_test_macros.h"
3
4 RVTEST_RV64U # Define TVM used by program.
5
6
7 # SV test: vector-vector add
8 #
9 # sets up x3 and x4 with data, sets VL to 2, and carries out
10 # an "add 1 to x3". which actually means "add 1 to x3 *AND* add 1 to x4"
11
12 # Test code region.
13 RVTEST_CODE_BEGIN # Start of test code.
14
15 SV_LD_DATA( x2, testdata , 0)
16 SV_LD_DATA( x3, testdata+8 , 0)
17 SV_LD_DATA( x4, testdata+16, 0)
18 SV_LD_DATA( x5, testdata+24, 0)
19
20 SET_SV_MVL(2)
21 SET_SV_CSR(1, 3, 0, 3, 1)
22 SET_SV_VL(2)
23
24 addi x3, x3, 1
25
26 CLR_SV_CSRS()
27 SET_SV_VL(0)
28 SET_SV_MVL(0)
29
30 TEST_SV_IMM(x2, 1001) # should not be modified
31 TEST_SV_IMM(x3, 42)
32 TEST_SV_IMM(x4, 43)
33 TEST_SV_IMM(x5, 1002) # should not be modified
34
35 RVTEST_PASS # Signal success.
36 fail:
37 RVTEST_FAIL
38 RVTEST_CODE_END # End of test code.
39
40 # Input data section.
41 # This section is optional, and this data is NOT saved in the output.
42 .data
43 .align 3
44 testdata:
45 .dword 1001
46 .dword 41
47 .dword 42
48 .dword 1002
49
50 # Output data section.
51 RVTEST_DATA_BEGIN # Start of test output data region.
52 .align 3
53 result:
54 .dword -1
55 .dword -1
56 .dword -1
57 RVTEST_DATA_END # End of test output data region.
58