a0a293434e492d9ae34277a71cd6b3855418fec1
[riscv-tests.git] / isa / rv64uc / sv_c_lwsp_predication.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # sv_c_lwsp_predication.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test RVC c.lwsp with twin-predication.
8 #
9
10 #include "riscv_test.h"
11 #include "sv_test_macros.h"
12
13 RVTEST_RV64U
14 RVTEST_CODE_BEGIN
15
16 .align 2
17 .option push
18 .option norvc
19
20 li a2, 0
21 li a3, 0
22 li a4, 0
23 li a0, 0x6; // targetted by use of sp: means skip, copy, copy
24 li a1, 0x5; // targetted by use of a2: meanss a2, skip, a4
25
26
27 mv a6, sp
28 la sp, data;
29
30 SET_SV_MVL(3)
31 SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1),
32 SV_REG_CSR(1, 2, 0, 2, 1) )
33 SET_SV_2PREDCSRS(
34 SV_PRED_CSR(1, 2, 0, 0, 10, 0),
35 SV_PRED_CSR(1, 12, 0, 0, 11, 0) );
36
37
38 SET_SV_VL(3)
39
40 .option push;
41 .option rvc;
42 .align 2;
43 c.lwsp a2, 0(sp); # actually lw a2, 4(sp); lw a4 8(sp) due to twin-predication
44 #lw a2, 0(sp);
45 .option pop
46
47
48 SET_SV_VL(0)
49 CLR_SV_CSRS()
50 SET_SV_MVL(0)
51
52 mv sp, a6
53
54 TEST_SV_IMM(a2, 1002) # data[0] was skipped (a0 & 1 == 0)
55 TEST_SV_IMM(a3, 0) # a3 was skipped (a1 & 2 == 0)
56 TEST_SV_IMM(a4, 1005)
57
58 .option pop
59
60 RVTEST_PASS # Signal success.
61 fail:
62 RVTEST_FAIL
63
64 RVTEST_CODE_END # End of test code.
65
66 .data
67 data:
68 .word 1001;
69 .word 1002;
70 .word 1005;
71
72 RVTEST_DATA_BEGIN
73
74 RVTEST_DATA_END