isa/rv64ui/sv_beq.S

   1 #include "riscv_test.h"
   2 #include "sv_test_macros.h"
   3
   4 RVTEST_RV64U        # Define TVM used by program.
   5
   6
   7 # SV test: vector-vector add different rd and rs1
   8 #
   9 # sets up x6 and x7 with data, sets VL to 2, and carries out
  10 # an "x3 = 1 + x6".  which actually means "x3 = 1 + x6 *AND* x4 = 1 + x7"
  11
  12 # Test code region.
  13 RVTEST_CODE_BEGIN   # Start of test code.
  14
  15         li          a3, 0x3
  16         li          a4, 0x0
  17
  18         SET_SV_MVL(2)
  19         SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1),
  20                       SV_REG_CSR(1, 6, 0, 6, 1) )
  21        SET_SV_2PREDCSRS(                              \
  22                       SV_PRED_CSR(1, 3, 0, 0, 13, 0),  \
  23                       SV_PRED_CSR(1, 6, 0, 0, 14, 0) );\
  24
  25         li          x6, 1
  26         li          x7, 1
  27
  28         li          x3, 1
  29         li          x4, 1
  30
  31         SET_SV_VL(2)
  32
  33         beq    x3,x6,here
  34 here:
  35
  36         CLR_SV_CSRS()
  37         SET_SV_VL(1)
  38         SET_SV_MVL(1)
  39
  40         TEST_SV_IMM(a4, 0x3)
  41
  42         RVTEST_PASS           # Signal success.
  43 fail:
  44         RVTEST_FAIL
  45 RVTEST_CODE_END     # End of test code.
  46
  47 # Input data section.
  48 # This section is optional, and this data is NOT saved in the output.
  49 .data
  50         .align 3
  51 testdata:
  52         .dword 1001
  53         .dword 41
  54         .dword 42
  55         .dword 1002
  56
  57 # Output data section.
  58 RVTEST_DATA_BEGIN   # Start of test output data region.
  59         .align 3
  60 result:
  61         .dword -1
  62         .dword -1
  63         .dword -1
  64 RVTEST_DATA_END     # End of test output data region.
  65