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modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)
2018-10-16 Luke Kenneth Casson... modified VL and MVL CSRs to range from 1-XLEN rather...
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2018-10-09 Luke Kenneth Casson... add sv vectorised predicated beq test
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2018-10-09 Luke Kenneth Casson... alter unit tests to match change in CSR table format
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2018-10-07 Luke Kenneth Casson... add cleanup and comments to sv lwsp pred test
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2018-10-07 Luke Kenneth Casson... add predicated version of c.lwsp sv unit test
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2018-10-07 Luke Kenneth Casson... add 3rd register to c.swsp
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2018-10-07 Luke Kenneth Casson... add 3 registers to sv c.lwsp
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2018-10-07 Luke Kenneth Casson... add s.swsp sv test
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2018-10-06 Luke Kenneth Casson... add sv c_lwsp unit test
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2018-10-05 Luke Kenneth Casson... whoops overwrote x2
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2018-10-04 Luke Kenneth Casson... add twin-predicated sv c_mv unit test (no zeroing)
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2018-10-04 Luke Kenneth Casson... add sv c.mv twin-predication unit test
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2018-10-02 Luke Kenneth Casson... actually sv vector-vector add worked fine
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2018-10-02 Luke Kenneth Casson... add rv64ud sv fadd test, shows flaw in loop for 3-arg...
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2018-10-01 Luke Kenneth Casson... add vector-vector sv add
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2018-10-01 Luke Kenneth Casson... add sv addi predicated unit test, including inversion...
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2018-10-01 Luke Kenneth Casson... add extra sv test comments
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2018-10-01 Luke Kenneth Casson... update sv test comments
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2018-10-01 Luke Kenneth Casson... add sv scalar src test which highlighted flaw in spike-sv
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2018-10-01 Luke Kenneth Casson... add redirection sv unit test
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2018-10-01 Luke Kenneth Casson... augment sv_addi test using macros
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2018-10-01 Luke Kenneth Casson... add first unit test for simple-v
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