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actually sv vector-vector add worked fine
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 2 Oct 2018 11:22:33 +0000 (12:22 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 2 Oct 2018 11:22:33 +0000 (12:22 +0100)
(forgot to set CSR on 2nd register)

isa/rv64ud/sv_fadd.S patch | blob | history

diff --git a/isa/rv64ud/sv_fadd.S b/isa/rv64ud/sv_fadd.S
index f456119c8721f0cbb8f99ae062bf89dfa3b5475e..9ef208271f6aff174e91e822209dd09bee9bd993 100644 (file)
--- a/isa/rv64ud/sv_fadd.S
+++ b/isa/rv64ud/sv_fadd.S
@@ -22,7 +22,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
         SV_FLD_DATA( f8, testdata+56, 0)
 
         SET_SV_MVL(2)
-        SET_SV_CSR(0, 2, 0, 2, 1, 0)
+        SET_SV_2CSRS( SV_REG_CSR(0, 2, 0, 2, 1, 0),
+                      SV_REG_CSR(0, 6, 0, 6, 1, 0) )
         SET_SV_VL(2)
 
         fadd.d f2, f2, f6;