isa/rv64ud/sv_fadd.S

   1 #include "riscv_test.h"
   2 #include "sv_test_macros.h"
   3
   4 RVTEST_RV64UF
   5
   6
   7 # SV test: vector-vector fadd
   8 #
   9 # sets up x3 and x4 with data, sets VL to 2, and carries out
  10 # an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
  11
  12 # Test code region.
  13 RVTEST_CODE_BEGIN   # Start of test code.
  14
  15         SV_FLD_DATA( f1, testdata   , 0)
  16         SV_FLD_DATA( f2, testdata+8 , 0)
  17         SV_FLD_DATA( f3, testdata+16, 0)
  18         SV_FLD_DATA( f4, testdata+24, 0)
  19         SV_FLD_DATA( f5, testdata+32, 0)
  20         SV_FLD_DATA( f6, testdata+40, 0)
  21         SV_FLD_DATA( f7, testdata+48, 0)
  22         SV_FLD_DATA( f8, testdata+56, 0)
  23
  24         SET_SV_MVL(2)
  25         SET_SV_CSR(0, 2, 0, 2, 1, 0)
  26         SET_SV_VL(2)
  27
  28         fadd.d f2, f2, f6;
  29
  30         CLR_SV_CSRS()
  31         SET_SV_VL(0)
  32         SET_SV_MVL(0)
  33
  34         TEST_SV_FD(0, f1, testdata+64, 0)
  35         TEST_SV_FD(0, f2, testdata+72, 0)
  36         TEST_SV_FD(0, f3, testdata+80, 0)
  37         TEST_SV_FD(0, f4, testdata+88, 0)
  38
  39         RVTEST_PASS           # Signal success.
  40 fail:
  41         RVTEST_FAIL
  42 RVTEST_CODE_END     # End of test code.
  43
  44 # Input data section.
  45 # This section is optional, and this data is NOT saved in the output.
  46 .data
  47         .align 3
  48 testdata:
  49         .double 1001.0
  50         .double 41.0
  51         .double 42.0
  52         .double 1002.0
  53         .double 1001.0
  54         .double 1.0
  55         .double 2.0
  56         .double 1002.0
  57         .double 1001.0
  58         .double 42.0
  59         .double 44.0
  60         .double 1002.0
  61
  62 # Output data section.
  63 RVTEST_DATA_BEGIN   # Start of test output data region.
  64         .align 3
  65 result:
  66         .dword -1
  67         .dword -1
  68         .dword -1
  69 RVTEST_DATA_END     # End of test output data region.
  70